blob: f341b4f367cbac7c508017b149754906d2d83475 [file] [log] [blame]
Dave Gerlach96571ec2021-04-23 11:27:32 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM642: SoC specific initialization
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 * Keerthy <j-keerthy@ti.com>
7 * Dave Gerlach <d-gerlach@ti.com>
8 */
9
Aswath Govindraju70bc5e32021-06-04 22:00:33 +053010#include <fdt_support.h>
Dave Gerlach96571ec2021-04-23 11:27:32 -050011#include <spl.h>
12#include <asm/io.h>
Keerthy05d670e2021-04-23 11:27:33 -050013#include <asm/arch/hardware.h>
Andrew Davisf1799852023-04-06 11:38:16 -050014#include "sysfw-loader.h"
Dave Gerlach96571ec2021-04-23 11:27:32 -050015#include "common.h"
Dave Gerlach8e0689b2021-04-23 11:27:36 -050016#include <linux/soc/ti/ti_sci_protocol.h>
17#include <dm.h>
18#include <dm/uclass-internal.h>
19#include <dm/pinctrl.h>
Dave Gerlacha89f7a42021-04-23 11:27:37 -050020#include <mmc.h>
Lokesh Vutla17ad6e02021-05-06 16:44:52 +053021#include <dm/root.h>
Nitin Yadav2eda10a2023-04-06 13:29:36 +053022#include <command.h>
Dave Gerlach96571ec2021-04-23 11:27:32 -050023
Hari Nagallad383c5e2022-03-09 14:42:30 -060024#define CTRLMMR_MCU_RST_CTRL 0x04518170
Dave Gerlach96571ec2021-04-23 11:27:32 -050025
Nitin Yadav2eda10a2023-04-06 13:29:36 +053026#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178)
27#define COLD_BOOT 0
28#define SW_POR_MCU BIT(24)
29#define SW_POR_MAIN BIT(25)
30
Dave Gerlacheaef1292021-04-23 11:27:34 -050031static void ctrl_mmr_unlock(void)
32{
33 /* Unlock all PADCFG_MMR1 module registers */
34 mmr_unlock(PADCFG_MMR1_BASE, 1);
35
Hari Nagallad383c5e2022-03-09 14:42:30 -060036 /* Unlock all MCU_CTRL_MMR0 module registers */
37 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
38 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
39 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
40 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
41 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
42 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
43
Dave Gerlacheaef1292021-04-23 11:27:34 -050044 /* Unlock all CTRL_MMR0 module registers */
45 mmr_unlock(CTRL_MMR0_BASE, 0);
46 mmr_unlock(CTRL_MMR0_BASE, 1);
47 mmr_unlock(CTRL_MMR0_BASE, 2);
48 mmr_unlock(CTRL_MMR0_BASE, 3);
49 mmr_unlock(CTRL_MMR0_BASE, 5);
50 mmr_unlock(CTRL_MMR0_BASE, 6);
Christian Gmeiner33a9d8e2022-05-12 08:21:01 +020051
52 /* Unlock all MCU_PADCFG_MMR1 module registers */
53 mmr_unlock(MCU_PADCFG_MMR1_BASE, 1);
Dave Gerlacheaef1292021-04-23 11:27:34 -050054}
55
Dave Gerlachb27a9f22021-04-23 11:27:35 -050056/*
57 * This uninitialized global variable would normal end up in the .bss section,
58 * but the .bss is cleared between writing and reading this variable, so move
59 * it to the .data section.
60 */
61u32 bootindex __section(".data");
Marek BehĂșn4bebdd32021-05-20 13:23:52 +020062static struct rom_extended_boot_data bootdata __section(".data");
Dave Gerlachb27a9f22021-04-23 11:27:35 -050063
64static void store_boot_info_from_rom(void)
65{
66 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
Bryan Brattlof270537c2022-11-22 13:28:11 -060067 memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
Dave Gerlachb27a9f22021-04-23 11:27:35 -050068 sizeof(struct rom_extended_boot_data));
69}
70
Dave Gerlacha89f7a42021-04-23 11:27:37 -050071#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
72void k3_mmc_stop_clock(void)
73{
74 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
75 struct mmc *mmc = find_mmc_device(0);
76
77 if (!mmc)
78 return;
79
80 mmc->saved_clock = mmc->clock;
81 mmc_set_clock(mmc, 0, true);
82 }
83}
84
85void k3_mmc_restart_clock(void)
86{
87 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
88 struct mmc *mmc = find_mmc_device(0);
89
90 if (!mmc)
91 return;
92
93 mmc_set_clock(mmc, mmc->saved_clock, false);
94 }
95}
96#else
97void k3_mmc_stop_clock(void) {}
98void k3_mmc_restart_clock(void) {}
99#endif
100
Lokesh Vutla17ad6e02021-05-06 16:44:52 +0530101#ifdef CONFIG_SPL_OF_LIST
102void do_dt_magic(void)
103{
104 int ret, rescan;
105
Andrew Davis2dde9a72023-04-06 11:38:17 -0500106 /* Perform board detection */
107 do_board_detect();
Lokesh Vutla17ad6e02021-05-06 16:44:52 +0530108
109 /*
110 * Board detection has been done.
111 * Let us see if another dtb wouldn't be a better match
112 * for our board
113 */
114 if (IS_ENABLED(CONFIG_CPU_V7R)) {
115 ret = fdtdec_resetup(&rescan);
116 if (!ret && rescan) {
117 dm_uninit();
118 dm_init_and_scan(true);
119 }
120 }
121}
122#endif
123
Aswath Govindraju70bc5e32021-06-04 22:00:33 +0530124#if CONFIG_IS_ENABLED(USB_STORAGE)
125static int fixup_usb_boot(const void *fdt_blob)
126{
127 int ret = 0;
128
129 switch (spl_boot_device()) {
130 case BOOT_DEVICE_USB:
131 /*
132 * If the boot mode is host, fixup the dr_mode to host
133 * before cdns3 bind takes place
134 */
135 ret = fdt_find_and_setprop((void *)fdt_blob,
136 "/bus@f4000/cdns-usb@f900000/usb@f400000",
137 "dr_mode", "host", 5, 0);
138 if (ret)
139 printf("%s: fdt_find_and_setprop() failed:%d\n",
140 __func__, ret);
141 fallthrough;
142 default:
143 break;
144 }
145
146 return ret;
147}
148
149int fdtdec_board_setup(const void *fdt_blob)
150{
151 /* Can use the pointer from the function parameters */
152 return fixup_usb_boot(fdt_blob);
153}
154#endif
155
Hari Nagallad383c5e2022-03-09 14:42:30 -0600156#if defined(CONFIG_ESM_K3)
157static void enable_mcu_esm_reset(void)
158{
159 /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */
160 u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
161
162 stat &= 0xFFFDFFFF;
163 writel(stat, CTRLMMR_MCU_RST_CTRL);
164}
165#endif
166
Dave Gerlach96571ec2021-04-23 11:27:32 -0500167void board_init_f(ulong dummy)
168{
Hari Nagallad383c5e2022-03-09 14:42:30 -0600169#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3)
Dave Gerlach8e0689b2021-04-23 11:27:36 -0500170 struct udevice *dev;
171 int ret;
Nitin Yadav2eda10a2023-04-06 13:29:36 +0530172 int rst_src;
Dave Gerlach8e0689b2021-04-23 11:27:36 -0500173#endif
174
Dave Gerlach96571ec2021-04-23 11:27:32 -0500175#if defined(CONFIG_CPU_V7R)
176 setup_k3_mpu_regions();
177#endif
178
Dave Gerlachb27a9f22021-04-23 11:27:35 -0500179 /*
180 * Cannot delay this further as there is a chance that
181 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
182 */
183 store_boot_info_from_rom();
184
Dave Gerlacheaef1292021-04-23 11:27:34 -0500185 ctrl_mmr_unlock();
186
Dave Gerlach96571ec2021-04-23 11:27:32 -0500187 /* Init DM early */
188 spl_early_init();
189
190 preloader_console_init();
Dave Gerlach8e0689b2021-04-23 11:27:36 -0500191
192#if defined(CONFIG_K3_LOAD_SYSFW)
193 /*
194 * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
195 * regardless of the result of pinctrl. Do this without probing the
196 * device, but instead by searching the device that would request the
197 * given sequence number if probed. The UART will be used by the system
198 * firmware (SYSFW) image for various purposes and SYSFW depends on us
199 * to initialize its pin settings.
200 */
201 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
202 if (!ret)
203 pinctrl_select_state(dev, "default");
204
205 /*
206 * Load, start up, and configure system controller firmware.
207 * This will determine whether or not ROM has already loaded
208 * system firmware and if so, will only perform needed config
209 * and not attempt to load firmware again.
210 */
Dave Gerlacha89f7a42021-04-23 11:27:37 -0500211 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock,
212 k3_mmc_restart_clock);
Dave Gerlach8e0689b2021-04-23 11:27:36 -0500213#endif
214
Nitin Yadav2eda10a2023-04-06 13:29:36 +0530215#if defined(CONFIG_CPU_V7R)
216 /*
217 * Errata ID i2331 CPSW: A device lockup can occur during the second
218 * read of any CPSW subsystem register after any MAIN domain power on
219 * reset (POR). A MAIN domain POR occurs using the hardware MCU_PORz
220 * signal, or via software using CTRLMMR_RST_CTRL.SW_MAIN_POR or
221 * CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR. After these resets, the processor
222 * and internal bus structures may get into a state which is only
223 * recoverable with full device reset using MCU_PORz.
224 * Workaround(s): To avoid the lockup, a warm reset should be issued
225 * after a MAIN domain POR and before any access to the CPSW registers.
226 * The warm reset realigns internal clocks and prevents the lockup from
227 * happening.
228 */
Andrew Davisa13596a2024-04-18 12:58:28 -0500229 ret = uclass_get_device_by_driver(UCLASS_FIRMWARE, DM_DRIVER_GET(ti_sci), &dev);
Nitin Yadav2eda10a2023-04-06 13:29:36 +0530230 if (ret)
231 printf("\n%s:uclass device error [%d]\n",__func__,ret);
232
233 rst_src = readl(CTRLMMR_MCU_RST_SRC);
234 if (rst_src == COLD_BOOT || rst_src & (SW_POR_MCU | SW_POR_MAIN)) {
235 printf("Resetting on cold boot to workaround ErrataID:i2331\n");
236 printf("Please resend tiboot3.bin in case of UART/DFU boot\n");
237 do_reset(NULL, 0, 0, NULL);
238 }
239#endif
240
Dave Gerlach8e0689b2021-04-23 11:27:36 -0500241 /* Output System Firmware version info */
242 k3_sysfw_print_ver();
Dave Gerlachad38f512021-05-04 18:00:53 -0500243
Christian Gmeinerfe8b5452023-03-28 16:13:14 +0200244 do_dt_magic();
245
Hari Nagallad383c5e2022-03-09 14:42:30 -0600246#if defined(CONFIG_ESM_K3)
247 /* Probe/configure ESM0 */
248 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
249 if (ret)
250 printf("esm main init failed: %d\n", ret);
251
252 /* Probe/configure MCUESM */
253 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
254 if (ret)
255 printf("esm mcu init failed: %d\n", ret);
256
257 enable_mcu_esm_reset();
258#endif
259
Dave Gerlachad38f512021-05-04 18:00:53 -0500260#if defined(CONFIG_K3_AM64_DDRSS)
261 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
262 if (ret)
263 panic("DRAM init failed: %d\n", ret);
264#endif
Vignesh Raghavendra82cc43e2021-12-24 12:55:32 +0530265 if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
266 spl_boot_device() == BOOT_DEVICE_ETHERNET) {
267 struct udevice *cpswdev;
268
269 if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev))
270 printf("Failed to probe am65_cpsw_nuss driver\n");
271 }
Dave Gerlach96571ec2021-04-23 11:27:32 -0500272}
Keerthy05d670e2021-04-23 11:27:33 -0500273
Andre Przywara3cb12ef2021-07-12 11:06:49 +0100274u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
Keerthy05d670e2021-04-23 11:27:33 -0500275{
276 switch (boot_device) {
277 case BOOT_DEVICE_MMC1:
278 return MMCSD_MODE_EMMCBOOT;
279
280 case BOOT_DEVICE_MMC2:
281 return MMCSD_MODE_FS;
282
283 default:
284 return MMCSD_MODE_RAW;
285 }
286}
287
Keerthy05d670e2021-04-23 11:27:33 -0500288u32 spl_boot_device(void)
289{
Wadim Egorov6cf1d9d2024-04-24 14:43:20 +0200290 return get_boot_device();
Keerthy05d670e2021-04-23 11:27:33 -0500291}