blob: b2c3774854e70f09b3b46515850b4a92f38573a5 [file] [log] [blame]
Dave Gerlach96571ec2021-04-23 11:27:32 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM642: SoC specific initialization
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 * Keerthy <j-keerthy@ti.com>
7 * Dave Gerlach <d-gerlach@ti.com>
8 */
9
10#include <common.h>
11#include <spl.h>
12#include <asm/io.h>
Keerthy05d670e2021-04-23 11:27:33 -050013#include <asm/arch/hardware.h>
Dave Gerlach8e0689b2021-04-23 11:27:36 -050014#include <asm/arch/sysfw-loader.h>
15#include <asm/arch/sys_proto.h>
Dave Gerlach96571ec2021-04-23 11:27:32 -050016#include "common.h"
Dave Gerlach8e0689b2021-04-23 11:27:36 -050017#include <asm/arch/sys_proto.h>
18#include <linux/soc/ti/ti_sci_protocol.h>
19#include <dm.h>
20#include <dm/uclass-internal.h>
21#include <dm/pinctrl.h>
Dave Gerlach96571ec2021-04-23 11:27:32 -050022
23#if defined(CONFIG_SPL_BUILD)
24
Dave Gerlacheaef1292021-04-23 11:27:34 -050025static void ctrl_mmr_unlock(void)
26{
27 /* Unlock all PADCFG_MMR1 module registers */
28 mmr_unlock(PADCFG_MMR1_BASE, 1);
29
30 /* Unlock all CTRL_MMR0 module registers */
31 mmr_unlock(CTRL_MMR0_BASE, 0);
32 mmr_unlock(CTRL_MMR0_BASE, 1);
33 mmr_unlock(CTRL_MMR0_BASE, 2);
34 mmr_unlock(CTRL_MMR0_BASE, 3);
35 mmr_unlock(CTRL_MMR0_BASE, 5);
36 mmr_unlock(CTRL_MMR0_BASE, 6);
37}
38
Dave Gerlachb27a9f22021-04-23 11:27:35 -050039/*
40 * This uninitialized global variable would normal end up in the .bss section,
41 * but the .bss is cleared between writing and reading this variable, so move
42 * it to the .data section.
43 */
44u32 bootindex __section(".data");
45static struct rom_extended_boot_data bootdata __section(.data);
46
47static void store_boot_info_from_rom(void)
48{
49 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
50 memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
51 sizeof(struct rom_extended_boot_data));
52}
53
Dave Gerlach96571ec2021-04-23 11:27:32 -050054void board_init_f(ulong dummy)
55{
Dave Gerlach8e0689b2021-04-23 11:27:36 -050056#if defined(CONFIG_K3_LOAD_SYSFW)
57 struct udevice *dev;
58 int ret;
59#endif
60
Dave Gerlach96571ec2021-04-23 11:27:32 -050061#if defined(CONFIG_CPU_V7R)
62 setup_k3_mpu_regions();
63#endif
64
Dave Gerlachb27a9f22021-04-23 11:27:35 -050065 /*
66 * Cannot delay this further as there is a chance that
67 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
68 */
69 store_boot_info_from_rom();
70
Dave Gerlacheaef1292021-04-23 11:27:34 -050071 ctrl_mmr_unlock();
72
Dave Gerlach96571ec2021-04-23 11:27:32 -050073 /* Init DM early */
74 spl_early_init();
75
76 preloader_console_init();
Dave Gerlach8e0689b2021-04-23 11:27:36 -050077
78#if defined(CONFIG_K3_LOAD_SYSFW)
79 /*
80 * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
81 * regardless of the result of pinctrl. Do this without probing the
82 * device, but instead by searching the device that would request the
83 * given sequence number if probed. The UART will be used by the system
84 * firmware (SYSFW) image for various purposes and SYSFW depends on us
85 * to initialize its pin settings.
86 */
87 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
88 if (!ret)
89 pinctrl_select_state(dev, "default");
90
91 /*
92 * Load, start up, and configure system controller firmware.
93 * This will determine whether or not ROM has already loaded
94 * system firmware and if so, will only perform needed config
95 * and not attempt to load firmware again.
96 */
97 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), NULL, NULL);
98#endif
99
100 /* Output System Firmware version info */
101 k3_sysfw_print_ver();
Dave Gerlach96571ec2021-04-23 11:27:32 -0500102}
Keerthy05d670e2021-04-23 11:27:33 -0500103
104u32 spl_boot_mode(const u32 boot_device)
105{
106 switch (boot_device) {
107 case BOOT_DEVICE_MMC1:
108 return MMCSD_MODE_EMMCBOOT;
109
110 case BOOT_DEVICE_MMC2:
111 return MMCSD_MODE_FS;
112
113 default:
114 return MMCSD_MODE_RAW;
115 }
116}
117
118static u32 __get_backup_bootmedia(u32 main_devstat)
119{
120 u32 bkup_bootmode =
121 (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
122 MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
123 u32 bkup_bootmode_cfg =
124 (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
125 MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
126
127 switch (bkup_bootmode) {
128 case BACKUP_BOOT_DEVICE_UART:
129 return BOOT_DEVICE_UART;
130
131 case BACKUP_BOOT_DEVICE_USB:
132 return BOOT_DEVICE_USB;
133
134 case BACKUP_BOOT_DEVICE_ETHERNET:
135 return BOOT_DEVICE_ETHERNET;
136
137 case BACKUP_BOOT_DEVICE_MMC:
138 if (bkup_bootmode_cfg)
139 return BOOT_DEVICE_MMC2;
140 return BOOT_DEVICE_MMC1;
141
142 case BACKUP_BOOT_DEVICE_SPI:
143 return BOOT_DEVICE_SPI;
144
145 case BACKUP_BOOT_DEVICE_I2C:
146 return BOOT_DEVICE_I2C;
147 };
148
149 return BOOT_DEVICE_RAM;
150}
151
152static u32 __get_primary_bootmedia(u32 main_devstat)
153{
154 u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
155 MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
156 u32 bootmode_cfg =
157 (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
158 MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
159
160 switch (bootmode) {
161 case BOOT_DEVICE_OSPI:
162 fallthrough;
163 case BOOT_DEVICE_QSPI:
164 fallthrough;
165 case BOOT_DEVICE_XSPI:
166 fallthrough;
167 case BOOT_DEVICE_SPI:
168 return BOOT_DEVICE_SPI;
169
170 case BOOT_DEVICE_ETHERNET_RGMII:
171 fallthrough;
172 case BOOT_DEVICE_ETHERNET_RMII:
173 return BOOT_DEVICE_ETHERNET;
174
175 case BOOT_DEVICE_EMMC:
176 return BOOT_DEVICE_MMC1;
177
178 case BOOT_DEVICE_MMC:
179 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
180 MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
181 return BOOT_DEVICE_MMC2;
182 return BOOT_DEVICE_MMC1;
183
184 case BOOT_DEVICE_NOBOOT:
185 return BOOT_DEVICE_RAM;
186 }
187
188 return bootmode;
189}
190
191u32 spl_boot_device(void)
192{
193 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
194
195 if (bootindex == K3_PRIMARY_BOOTMODE)
196 return __get_primary_bootmedia(devstat);
197 else
198 return __get_backup_bootmedia(devstat);
199}
Dave Gerlach96571ec2021-04-23 11:27:32 -0500200#endif