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Heiko Schocher60301192010-02-22 16:43:02 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * (C) Copyright 2009
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
Holger Brunck2ef42952012-07-05 05:37:46 +00009 * (C) Copyright 2011-2012
10 * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
11 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
Holger Brunck1f974e92011-06-16 18:11:15 +053012 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher60301192010-02-22 16:43:02 +053014 */
15
16/*
17 * for linking errors see
18 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
19 */
20
Holger Brunck1f974e92011-06-16 18:11:15 +053021#ifndef _CONFIG_KM_KIRKWOOD_H
22#define _CONFIG_KM_KIRKWOOD_H
Heiko Schocher60301192010-02-22 16:43:02 +053023
Holger Brunckb693ce82012-07-05 05:05:06 +000024/* KM_KIRKWOOD */
Holger Brunck9f03a382012-05-25 01:57:13 +000025#if defined(CONFIG_KM_KIRKWOOD)
Holger Brunckf065ce02012-07-05 05:05:02 +000026#define CONFIG_HOSTNAME km_kirkwood
Holger Brunckb693ce82012-07-05 05:05:06 +000027#define CONFIG_KM_DISABLE_PCIE
Heiko Schocher8cfad362012-10-25 11:07:00 +020028#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckb693ce82012-07-05 05:05:06 +000029
30/* KM_KIRKWOOD_PCI */
Holger Brunck9f03a382012-05-25 01:57:13 +000031#elif defined(CONFIG_KM_KIRKWOOD_PCI)
Holger Brunckf065ce02012-07-05 05:05:02 +000032#define CONFIG_HOSTNAME km_kirkwood_pci
Heiko Schocher8cfad362012-10-25 11:07:00 +020033#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckb693ce82012-07-05 05:05:06 +000034#define CONFIG_KM_FPGA_CONFIG
Holger Brunck4dd3bcf2014-08-15 10:51:48 +020035#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
36#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Holger Brunckb693ce82012-07-05 05:05:06 +000037
Karlheinz Jerg34544ea2013-09-18 09:32:48 +020038/* KM_KIRKWOOD_128M16 */
39#elif defined(CONFIG_KM_KIRKWOOD_128M16)
Karlheinz Jerg34544ea2013-09-18 09:32:48 +020040#define CONFIG_HOSTNAME km_kirkwood_128m16
41#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamadad6acdf22014-03-11 11:05:17 +090042#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
Karlheinz Jerg34544ea2013-09-18 09:32:48 +020043#define CONFIG_KM_DISABLE_PCIE
Holger Brunck7d8f2dc2013-10-07 15:10:03 +020044#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Karlheinz Jerg34544ea2013-09-18 09:32:48 +020045
Gerlando Falauto29ff59a2014-02-13 16:43:00 +010046/* KM_NUSA / KM_SUGP1 */
47#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
Heiko Schocher8cfad362012-10-25 11:07:00 +020048#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Gerlando Falauto29ff59a2014-02-13 16:43:00 +010049
50# if defined(CONFIG_KM_NUSA)
Holger Brunckf065ce02012-07-05 05:05:02 +000051#define CONFIG_HOSTNAME kmnusa
Gerlando Falauto29ff59a2014-02-13 16:43:00 +010052# elif defined(CONFIG_KM_SUGP1)
Gerlando Falauto29ff59a2014-02-13 16:43:00 +010053#define CONFIG_HOSTNAME kmsugp1
54#define KM_PCIE_RESET_MPP7
55#endif
56
Holger Brunck2ef42952012-07-05 05:37:46 +000057#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamadad6acdf22014-03-11 11:05:17 +090058#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
Holger Brunck2ef42952012-07-05 05:37:46 +000059#define CONFIG_KM_ENV_IS_IN_SPI_NOR
60#define CONFIG_KM_FPGA_CONFIG
61#define CONFIG_KM_PIGGY4_88E6352
Valentin Longchamp88874812012-08-16 01:25:20 +000062#define CONFIG_MV88E6352_SWITCH
63#define CONFIG_KM_MVEXTSW_ADDR 0x10
Holger Brunck2ef42952012-07-05 05:37:46 +000064
Holger Brunckd896d0d2012-07-05 05:05:03 +000065/* KM_MGCOGE3UN */
66#elif defined(CONFIG_KM_MGCOGE3UN)
Holger Brunckd896d0d2012-07-05 05:05:03 +000067#define CONFIG_HOSTNAME mgcoge3un
Heiko Schocher8cfad362012-10-25 11:07:00 +020068#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckd896d0d2012-07-05 05:05:03 +000069#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamadad6acdf22014-03-11 11:05:17 +090070#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
Holger Brunckd896d0d2012-07-05 05:05:03 +000071#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
72#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
73#define CONFIG_KM_DISABLE_PCIE
74#define CONFIG_KM_PIGGY4_88E6061
75
76/* KMCOGE5UN */
Holger Brunckf065ce02012-07-05 05:05:02 +000077#elif defined(CONFIG_KM_COGE5UN)
Heiko Schocher8cfad362012-10-25 11:07:00 +020078#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckf065ce02012-07-05 05:05:02 +000079#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamadad6acdf22014-03-11 11:05:17 +090080#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
Holger Brunckf065ce02012-07-05 05:05:02 +000081#define CONFIG_KM_ENV_IS_IN_SPI_NOR
82#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
83#define CONFIG_HOSTNAME kmcoge5un
84#define CONFIG_KM_DISABLE_PCIE
85#define CONFIG_KM_PIGGY4_88E6352
Holger Brunckc9caa7f2012-07-05 05:05:04 +000086
87/* KM_PORTL2 */
88#elif defined(CONFIG_KM_PORTL2)
Holger Brunckc9caa7f2012-07-05 05:05:04 +000089#define CONFIG_HOSTNAME portl2
Heiko Schocher8cfad362012-10-25 11:07:00 +020090#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckc9caa7f2012-07-05 05:05:04 +000091#define CONFIG_KM_PIGGY4_88E6061
92
Holger Brunckac552d52013-01-15 22:51:22 +000093/* KM_SUV31 */
94#elif defined(CONFIG_KM_SUV31)
Heiko Schocher479a4cf2013-01-29 08:53:15 +010095#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckac552d52013-01-15 22:51:22 +000096#define CONFIG_HOSTNAME kmsuv31
Holger Brunck7bffb3f2014-01-27 16:58:24 +010097#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamadad6acdf22014-03-11 11:05:17 +090098#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
Holger Brunckac552d52013-01-15 22:51:22 +000099#define CONFIG_KM_ENV_IS_IN_SPI_NOR
100#define CONFIG_KM_FPGA_CONFIG
Holger Brunck4dd3bcf2014-08-15 10:51:48 +0200101#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
102#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Holger Brunck2ef42952012-07-05 05:37:46 +0000103#else
104#error ("Board unsupported")
Holger Brunck1f974e92011-06-16 18:11:15 +0530105#endif
Heiko Schocher60301192010-02-22 16:43:02 +0530106
Holger Brunck2ef42952012-07-05 05:37:46 +0000107/* include common defines/options for all arm based Keymile boards */
108#include "km/km_arm.h"
109
Holger Brunck2ef42952012-07-05 05:37:46 +0000110#if defined(CONFIG_KM_PIGGY4_88E6352)
111/*
112 * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
113 * an Marvell 88E6352 simple switch.
114 * In this case we have to change the default settings for the etherent mac.
115 * There is NO ethernet phy. The ARM and Switch are conencted directly over
116 * RGMII in MAC-MAC mode
117 * In this case 1GBit full duplex and autoneg off
118 */
119#define PORT_SERIAL_CONTROL_VALUE ( \
120 MVGBE_FORCE_LINK_PASS | \
121 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
122 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
123 MVGBE_ADV_NO_FLOW_CTRL | \
124 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
125 MVGBE_FORCE_BP_MODE_NO_JAM | \
126 (1 << 9) /* Reserved bit has to be 1 */ | \
127 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
128 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
129 MVGBE_DTE_ADV_0 | \
130 MVGBE_MIIPHY_MAC_MODE | \
131 MVGBE_AUTO_NEG_NO_CHANGE | \
132 MVGBE_MAX_RX_PACKET_1552BYTE | \
133 MVGBE_CLR_EXT_LOOPBACK | \
134 MVGBE_SET_FULL_DUPLEX_MODE | \
135 MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
136 MVGBE_SET_GMII_SPEED_TO_1000 |\
137 MVGBE_SET_MII_SPEED_TO_100)
138
139#endif
Heiko Schochere4533af2011-03-08 10:53:51 +0100140
Holger Brunckd896d0d2012-07-05 05:05:03 +0000141#ifdef CONFIG_KM_PIGGY4_88E6061
142/*
143 * Some keymile boards like mgcoge3un have their PIGGY4 connected via
144 * an Marvell 88E6061 simple switch.
145 * In this case we have to change the default settings for the
146 * ethernet phy connected to the kirkwood.
147 * In this case 100MB full duplex and autoneg off
148 */
149#define PORT_SERIAL_CONTROL_VALUE ( \
150 MVGBE_FORCE_LINK_PASS | \
151 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
152 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
153 MVGBE_ADV_NO_FLOW_CTRL | \
154 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
155 MVGBE_FORCE_BP_MODE_NO_JAM | \
156 (1 << 9) /* Reserved bit has to be 1 */ | \
157 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
158 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
159 MVGBE_DTE_ADV_0 | \
160 MVGBE_MIIPHY_MAC_MODE | \
161 MVGBE_AUTO_NEG_NO_CHANGE | \
162 MVGBE_MAX_RX_PACKET_1552BYTE | \
163 MVGBE_CLR_EXT_LOOPBACK | \
164 MVGBE_SET_FULL_DUPLEX_MODE | \
165 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
166 MVGBE_SET_GMII_SPEED_TO_10_100 |\
167 MVGBE_SET_MII_SPEED_TO_100)
168#endif
169
Holger Brunckd896d0d2012-07-05 05:05:03 +0000170#ifdef CONFIG_KM_DISABLE_PCI
171#undef CONFIG_KIRKWOOD_PCIE_INIT
172#endif
Valentin Longchamp6633fed2012-07-05 05:05:05 +0000173
Holger Brunck1f974e92011-06-16 18:11:15 +0530174#endif /* _CONFIG_KM_KIRKWOOD */