blob: c850285645b22ae14184d84319840b18c0bf27c1 [file] [log] [blame]
Andy Flemingad347bb2008-10-30 16:41:01 -05001/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Andy Flemingad347bb2008-10-30 16:41:01 -05008 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -060013#include <dm.h>
14#include <dm/device-internal.h>
Stephen Warrenbf0c7852014-05-23 12:47:06 -060015#include <errno.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050016#include <mmc.h>
17#include <part.h>
18#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060019#include <memalign.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050020#include <linux/list.h>
Rabin Vincent69d4e2c2009-04-05 13:30:54 +053021#include <div64.h>
Paul Burton8d30cc92013-09-09 15:30:26 +010022#include "mmc_private.h"
Andy Flemingad347bb2008-10-30 16:41:01 -050023
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +020024__weak int board_mmc_getwp(struct mmc *mmc)
Nikita Kiryanov020f2612012-12-03 02:19:46 +000025{
26 return -1;
27}
28
29int mmc_getwp(struct mmc *mmc)
30{
31 int wp;
32
33 wp = board_mmc_getwp(mmc);
34
Peter Korsgaardf7b15102013-03-21 04:00:03 +000035 if (wp < 0) {
Pantelis Antoniou2c850462014-03-11 19:34:20 +020036 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
Peter Korsgaardf7b15102013-03-21 04:00:03 +000038 else
39 wp = 0;
40 }
Nikita Kiryanov020f2612012-12-03 02:19:46 +000041
42 return wp;
43}
44
Jeroen Hofstee47726302014-07-10 22:46:28 +020045__weak int board_mmc_getcd(struct mmc *mmc)
46{
Stefano Babic6e00edf2010-02-05 15:04:43 +010047 return -1;
48}
49
Paul Burton8d30cc92013-09-09 15:30:26 +010050int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
Andy Flemingad347bb2008-10-30 16:41:01 -050051{
Raffaele Recalcati894b1e22011-03-11 02:01:14 +000052 int ret;
Marek Vasutdccb6082012-03-15 18:41:35 +000053
Marek Vasutdccb6082012-03-15 18:41:35 +000054#ifdef CONFIG_MMC_TRACE
Raffaele Recalcati894b1e22011-03-11 02:01:14 +000055 int i;
56 u8 *ptr;
57
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
Pantelis Antoniou2c850462014-03-11 19:34:20 +020060 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
Bin Meng8d1ad1e2016-03-17 21:53:14 -070061 if (ret) {
62 printf("\t\tRET\t\t\t %d\n", ret);
63 } else {
64 switch (cmd->resp_type) {
65 case MMC_RSP_NONE:
66 printf("\t\tMMC_RSP_NONE\n");
67 break;
68 case MMC_RSP_R1:
69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
70 cmd->response[0]);
71 break;
72 case MMC_RSP_R1b:
73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
74 cmd->response[0]);
75 break;
76 case MMC_RSP_R2:
77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
78 cmd->response[0]);
79 printf("\t\t \t\t 0x%08X \n",
80 cmd->response[1]);
81 printf("\t\t \t\t 0x%08X \n",
82 cmd->response[2]);
83 printf("\t\t \t\t 0x%08X \n",
84 cmd->response[3]);
Raffaele Recalcati894b1e22011-03-11 02:01:14 +000085 printf("\n");
Bin Meng8d1ad1e2016-03-17 21:53:14 -070086 printf("\t\t\t\t\tDUMPING DATA\n");
87 for (i = 0; i < 4; i++) {
88 int j;
89 printf("\t\t\t\t\t%03d - ", i*4);
90 ptr = (u8 *)&cmd->response[i];
91 ptr += 3;
92 for (j = 0; j < 4; j++)
93 printf("%02X ", *ptr--);
94 printf("\n");
95 }
96 break;
97 case MMC_RSP_R3:
98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
99 cmd->response[0]);
100 break;
101 default:
102 printf("\t\tERROR MMC rsp not supported\n");
103 break;
Bin Meng4a4ef872016-03-17 21:53:13 -0700104 }
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000105 }
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000106#else
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200107 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000108#endif
Marek Vasutdccb6082012-03-15 18:41:35 +0000109 return ret;
Andy Flemingad347bb2008-10-30 16:41:01 -0500110}
111
Paul Burton8d30cc92013-09-09 15:30:26 +0100112int mmc_send_status(struct mmc *mmc, int timeout)
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000113{
114 struct mmc_cmd cmd;
Jan Kloetzke31789322012-02-05 22:29:12 +0000115 int err, retries = 5;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000116#ifdef CONFIG_MMC_TRACE
117 int status;
118#endif
119
120 cmd.cmdidx = MMC_CMD_SEND_STATUS;
121 cmd.resp_type = MMC_RSP_R1;
Marek Vasutc4427392011-08-10 09:24:48 +0200122 if (!mmc_host_is_spi(mmc))
123 cmd.cmdarg = mmc->rca << 16;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000124
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500125 while (1) {
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000126 err = mmc_send_cmd(mmc, &cmd, NULL);
Jan Kloetzke31789322012-02-05 22:29:12 +0000127 if (!err) {
128 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
129 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
130 MMC_STATE_PRG)
131 break;
132 else if (cmd.response[0] & MMC_STATUS_MASK) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100133#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Jan Kloetzke31789322012-02-05 22:29:12 +0000134 printf("Status Error: 0x%08X\n",
135 cmd.response[0]);
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100136#endif
Jan Kloetzke31789322012-02-05 22:29:12 +0000137 return COMM_ERR;
138 }
139 } else if (--retries < 0)
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000140 return err;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000141
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500142 if (timeout-- <= 0)
143 break;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000144
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500145 udelay(1000);
146 }
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000147
Raffaele Recalcati894b1e22011-03-11 02:01:14 +0000148#ifdef CONFIG_MMC_TRACE
149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
150 printf("CURR STATE:%d\n", status);
151#endif
Jongman Heo1be00d92012-06-03 21:32:13 +0000152 if (timeout <= 0) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100153#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000154 printf("Timeout waiting card ready\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100155#endif
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000156 return TIMEOUT;
157 }
158
159 return 0;
160}
161
Paul Burton8d30cc92013-09-09 15:30:26 +0100162int mmc_set_blocklen(struct mmc *mmc, int len)
Andy Flemingad347bb2008-10-30 16:41:01 -0500163{
164 struct mmc_cmd cmd;
165
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -0600166 if (mmc->ddr_mode)
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900167 return 0;
168
Andy Flemingad347bb2008-10-30 16:41:01 -0500169 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
170 cmd.resp_type = MMC_RSP_R1;
171 cmd.cmdarg = len;
Andy Flemingad347bb2008-10-30 16:41:01 -0500172
173 return mmc_send_cmd(mmc, &cmd, NULL);
174}
175
Sascha Silbe4bdf6fd2013-06-14 13:07:25 +0200176static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
Kim Phillips87ea3892012-10-29 13:34:43 +0000177 lbaint_t blkcnt)
Andy Flemingad347bb2008-10-30 16:41:01 -0500178{
179 struct mmc_cmd cmd;
180 struct mmc_data data;
181
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700182 if (blkcnt > 1)
183 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
184 else
185 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
Andy Flemingad347bb2008-10-30 16:41:01 -0500186
187 if (mmc->high_capacity)
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700188 cmd.cmdarg = start;
Andy Flemingad347bb2008-10-30 16:41:01 -0500189 else
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700190 cmd.cmdarg = start * mmc->read_bl_len;
Andy Flemingad347bb2008-10-30 16:41:01 -0500191
192 cmd.resp_type = MMC_RSP_R1;
Andy Flemingad347bb2008-10-30 16:41:01 -0500193
194 data.dest = dst;
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700195 data.blocks = blkcnt;
Andy Flemingad347bb2008-10-30 16:41:01 -0500196 data.blocksize = mmc->read_bl_len;
197 data.flags = MMC_DATA_READ;
198
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700199 if (mmc_send_cmd(mmc, &cmd, &data))
200 return 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500201
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700202 if (blkcnt > 1) {
203 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
204 cmd.cmdarg = 0;
205 cmd.resp_type = MMC_RSP_R1b;
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700206 if (mmc_send_cmd(mmc, &cmd, NULL)) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100207#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700208 printf("mmc fail to send stop cmd\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100209#endif
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700210 return 0;
211 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500212 }
213
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700214 return blkcnt;
Andy Flemingad347bb2008-10-30 16:41:01 -0500215}
216
Simon Glass59bc6f22016-05-01 13:52:41 -0600217#ifdef CONFIG_BLK
Simon Glass62e293a2016-06-12 23:30:15 -0600218ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
Simon Glass59bc6f22016-05-01 13:52:41 -0600219#else
Simon Glass62e293a2016-06-12 23:30:15 -0600220ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
221 void *dst)
Simon Glass59bc6f22016-05-01 13:52:41 -0600222#endif
Andy Flemingad347bb2008-10-30 16:41:01 -0500223{
Simon Glass59bc6f22016-05-01 13:52:41 -0600224#ifdef CONFIG_BLK
225 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
226#endif
Simon Glass2f26fff2016-02-29 15:25:51 -0700227 int dev_num = block_dev->devnum;
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700228 int err;
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700229 lbaint_t cur, blocks_todo = blkcnt;
230
231 if (blkcnt == 0)
232 return 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500233
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700234 struct mmc *mmc = find_mmc_device(dev_num);
Andy Flemingad347bb2008-10-30 16:41:01 -0500235 if (!mmc)
236 return 0;
237
Simon Glass11f2bb62016-05-01 13:52:29 -0600238 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700239 if (err < 0)
240 return 0;
241
Simon Glasse5db1152016-05-01 13:52:35 -0600242 if ((start + blkcnt) > block_dev->lba) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100243#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Sascha Silbe4bdf6fd2013-06-14 13:07:25 +0200244 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
Simon Glasse5db1152016-05-01 13:52:35 -0600245 start + blkcnt, block_dev->lba);
Paul Burton6a7c5ba2013-09-04 16:12:25 +0100246#endif
Lei Wene1cc9c82010-09-13 22:07:27 +0800247 return 0;
248 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500249
Simon Glassa4343c42015-06-23 15:38:50 -0600250 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
251 debug("%s: Failed to set blocklen\n", __func__);
Andy Flemingad347bb2008-10-30 16:41:01 -0500252 return 0;
Simon Glassa4343c42015-06-23 15:38:50 -0600253 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500254
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700255 do {
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200256 cur = (blocks_todo > mmc->cfg->b_max) ?
257 mmc->cfg->b_max : blocks_todo;
Simon Glassa4343c42015-06-23 15:38:50 -0600258 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
259 debug("%s: Failed to read blocks\n", __func__);
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700260 return 0;
Simon Glassa4343c42015-06-23 15:38:50 -0600261 }
Alagu Sankarc25d1b92010-10-25 07:23:56 -0700262 blocks_todo -= cur;
263 start += cur;
264 dst += cur * mmc->read_bl_len;
265 } while (blocks_todo > 0);
Andy Flemingad347bb2008-10-30 16:41:01 -0500266
267 return blkcnt;
268}
269
Kim Phillips87ea3892012-10-29 13:34:43 +0000270static int mmc_go_idle(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -0500271{
272 struct mmc_cmd cmd;
273 int err;
274
275 udelay(1000);
276
277 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
278 cmd.cmdarg = 0;
279 cmd.resp_type = MMC_RSP_NONE;
Andy Flemingad347bb2008-10-30 16:41:01 -0500280
281 err = mmc_send_cmd(mmc, &cmd, NULL);
282
283 if (err)
284 return err;
285
286 udelay(2000);
287
288 return 0;
289}
290
Kim Phillips87ea3892012-10-29 13:34:43 +0000291static int sd_send_op_cond(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -0500292{
293 int timeout = 1000;
294 int err;
295 struct mmc_cmd cmd;
296
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500297 while (1) {
Andy Flemingad347bb2008-10-30 16:41:01 -0500298 cmd.cmdidx = MMC_CMD_APP_CMD;
299 cmd.resp_type = MMC_RSP_R1;
300 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500301
302 err = mmc_send_cmd(mmc, &cmd, NULL);
303
304 if (err)
305 return err;
306
307 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
308 cmd.resp_type = MMC_RSP_R3;
Stefano Babicf8e9a212010-01-20 18:20:39 +0100309
310 /*
311 * Most cards do not answer if some reserved bits
312 * in the ocr are set. However, Some controller
313 * can set bit 7 (reserved for low voltages), but
314 * how to manage low voltages SD card is not yet
315 * specified.
316 */
Thomas Chou1254c3d2010-12-24 13:12:21 +0000317 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200318 (mmc->cfg->voltages & 0xff8000);
Andy Flemingad347bb2008-10-30 16:41:01 -0500319
320 if (mmc->version == SD_VERSION_2)
321 cmd.cmdarg |= OCR_HCS;
322
323 err = mmc_send_cmd(mmc, &cmd, NULL);
324
325 if (err)
326 return err;
327
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500328 if (cmd.response[0] & OCR_BUSY)
329 break;
Andy Flemingad347bb2008-10-30 16:41:01 -0500330
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500331 if (timeout-- <= 0)
332 return UNUSABLE_ERR;
333
334 udelay(1000);
335 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500336
337 if (mmc->version != SD_VERSION_2)
338 mmc->version = SD_VERSION_1_0;
339
Thomas Chou1254c3d2010-12-24 13:12:21 +0000340 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
341 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
342 cmd.resp_type = MMC_RSP_R3;
343 cmd.cmdarg = 0;
Thomas Chou1254c3d2010-12-24 13:12:21 +0000344
345 err = mmc_send_cmd(mmc, &cmd, NULL);
346
347 if (err)
348 return err;
349 }
350
Rabin Vincentb6eed942009-04-05 13:30:56 +0530351 mmc->ocr = cmd.response[0];
Andy Flemingad347bb2008-10-30 16:41:01 -0500352
353 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
354 mmc->rca = 0;
355
356 return 0;
357}
358
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500359static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
Andy Flemingad347bb2008-10-30 16:41:01 -0500360{
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500361 struct mmc_cmd cmd;
Andy Flemingad347bb2008-10-30 16:41:01 -0500362 int err;
363
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500364 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
365 cmd.resp_type = MMC_RSP_R3;
366 cmd.cmdarg = 0;
Rob Herring5fd3edd2015-03-23 17:56:59 -0500367 if (use_arg && !mmc_host_is_spi(mmc))
368 cmd.cmdarg = OCR_HCS |
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200369 (mmc->cfg->voltages &
Andrew Gabbasovec600d12015-03-19 07:44:03 -0500370 (mmc->ocr & OCR_VOLTAGE_MASK)) |
371 (mmc->ocr & OCR_ACCESS_MODE);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000372
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500373 err = mmc_send_cmd(mmc, &cmd, NULL);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000374 if (err)
375 return err;
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500376 mmc->ocr = cmd.response[0];
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000377 return 0;
378}
379
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +0200380static int mmc_send_op_cond(struct mmc *mmc)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000381{
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000382 int err, i;
383
Andy Flemingad347bb2008-10-30 16:41:01 -0500384 /* Some cards seem to need this */
385 mmc_go_idle(mmc);
386
Raffaele Recalcati1df837e2011-03-11 02:01:13 +0000387 /* Asking to the card its capabilities */
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000388 for (i = 0; i < 2; i++) {
Andrew Gabbasovfafa6a02015-03-19 07:44:04 -0500389 err = mmc_send_op_cond_iter(mmc, i != 0);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000390 if (err)
391 return err;
Wolfgang Denk80f70212011-05-19 22:21:41 +0200392
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000393 /* exit if not busy (flag seems to be inverted) */
Andrew Gabbasovec600d12015-03-19 07:44:03 -0500394 if (mmc->ocr & OCR_BUSY)
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -0500395 break;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000396 }
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -0500397 mmc->op_cond_pending = 1;
398 return 0;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000399}
Wolfgang Denk80f70212011-05-19 22:21:41 +0200400
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +0200401static int mmc_complete_op_cond(struct mmc *mmc)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000402{
403 struct mmc_cmd cmd;
404 int timeout = 1000;
405 uint start;
406 int err;
Wolfgang Denk80f70212011-05-19 22:21:41 +0200407
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000408 mmc->op_cond_pending = 0;
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500409 if (!(mmc->ocr & OCR_BUSY)) {
410 start = get_timer(0);
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500411 while (1) {
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500412 err = mmc_send_op_cond_iter(mmc, 1);
413 if (err)
414 return err;
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500415 if (mmc->ocr & OCR_BUSY)
416 break;
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500417 if (get_timer(start) > timeout)
418 return UNUSABLE_ERR;
419 udelay(100);
Andrew Gabbasov034857c2015-03-19 07:44:06 -0500420 }
Andrew Gabbasov5a513ca2015-03-19 07:44:05 -0500421 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500422
Thomas Chou1254c3d2010-12-24 13:12:21 +0000423 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
424 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
425 cmd.resp_type = MMC_RSP_R3;
426 cmd.cmdarg = 0;
Thomas Chou1254c3d2010-12-24 13:12:21 +0000427
428 err = mmc_send_cmd(mmc, &cmd, NULL);
429
430 if (err)
431 return err;
Andrew Gabbasovec600d12015-03-19 07:44:03 -0500432
433 mmc->ocr = cmd.response[0];
Thomas Chou1254c3d2010-12-24 13:12:21 +0000434 }
435
Andy Flemingad347bb2008-10-30 16:41:01 -0500436 mmc->version = MMC_VERSION_UNKNOWN;
Andy Flemingad347bb2008-10-30 16:41:01 -0500437
438 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
Stephen Warrenf6545f12014-01-30 16:11:12 -0700439 mmc->rca = 1;
Andy Flemingad347bb2008-10-30 16:41:01 -0500440
441 return 0;
442}
443
444
Kim Phillips87ea3892012-10-29 13:34:43 +0000445static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
Andy Flemingad347bb2008-10-30 16:41:01 -0500446{
447 struct mmc_cmd cmd;
448 struct mmc_data data;
449 int err;
450
451 /* Get the Card Status Register */
452 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
453 cmd.resp_type = MMC_RSP_R1;
454 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500455
Yoshihiro Shimodaf6bec732012-06-07 19:09:11 +0000456 data.dest = (char *)ext_csd;
Andy Flemingad347bb2008-10-30 16:41:01 -0500457 data.blocks = 1;
Simon Glassa09c2b72013-04-03 08:54:30 +0000458 data.blocksize = MMC_MAX_BLOCK_LEN;
Andy Flemingad347bb2008-10-30 16:41:01 -0500459 data.flags = MMC_DATA_READ;
460
461 err = mmc_send_cmd(mmc, &cmd, &data);
462
463 return err;
464}
465
Simon Glass84f9df92016-06-12 23:30:18 -0600466int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
Andy Flemingad347bb2008-10-30 16:41:01 -0500467{
468 struct mmc_cmd cmd;
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000469 int timeout = 1000;
470 int ret;
Andy Flemingad347bb2008-10-30 16:41:01 -0500471
472 cmd.cmdidx = MMC_CMD_SWITCH;
473 cmd.resp_type = MMC_RSP_R1b;
474 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000475 (index << 16) |
476 (value << 8);
Andy Flemingad347bb2008-10-30 16:41:01 -0500477
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000478 ret = mmc_send_cmd(mmc, &cmd, NULL);
479
480 /* Waiting for the ready status */
Jan Kloetzke4e929dd2012-02-05 22:29:11 +0000481 if (!ret)
482 ret = mmc_send_status(mmc, timeout);
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000483
484 return ret;
485
Andy Flemingad347bb2008-10-30 16:41:01 -0500486}
487
Kim Phillips87ea3892012-10-29 13:34:43 +0000488static int mmc_change_freq(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -0500489{
Simon Glassa09c2b72013-04-03 08:54:30 +0000490 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
Andy Flemingad347bb2008-10-30 16:41:01 -0500491 char cardtype;
492 int err;
493
Andrew Gabbasovccb7b042014-12-25 10:22:25 -0600494 mmc->card_caps = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500495
Thomas Chou1254c3d2010-12-24 13:12:21 +0000496 if (mmc_host_is_spi(mmc))
497 return 0;
498
Andy Flemingad347bb2008-10-30 16:41:01 -0500499 /* Only version 4 supports high-speed */
500 if (mmc->version < MMC_VERSION_4)
501 return 0;
502
Andrew Gabbasovccb7b042014-12-25 10:22:25 -0600503 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
504
Andy Flemingad347bb2008-10-30 16:41:01 -0500505 err = mmc_send_ext_csd(mmc, ext_csd);
506
507 if (err)
508 return err;
509
Lei Wen217467f2011-10-03 20:35:10 +0000510 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
Andy Flemingad347bb2008-10-30 16:41:01 -0500511
512 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
513
514 if (err)
Heiko Schocher9016ab92016-06-07 08:31:21 +0200515 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -0500516
517 /* Now check to see that it worked */
518 err = mmc_send_ext_csd(mmc, ext_csd);
519
520 if (err)
521 return err;
522
523 /* No high-speed support */
Lei Wen217467f2011-10-03 20:35:10 +0000524 if (!ext_csd[EXT_CSD_HS_TIMING])
Andy Flemingad347bb2008-10-30 16:41:01 -0500525 return 0;
526
527 /* High Speed is set, there are two types: 52MHz and 26MHz */
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900528 if (cardtype & EXT_CSD_CARD_TYPE_52) {
Andrew Gabbasov95a37132014-12-01 06:59:10 -0600529 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900530 mmc->card_caps |= MMC_MODE_DDR_52MHz;
Andy Flemingad347bb2008-10-30 16:41:01 -0500531 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900532 } else {
Andy Flemingad347bb2008-10-30 16:41:01 -0500533 mmc->card_caps |= MMC_MODE_HS;
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900534 }
Andy Flemingad347bb2008-10-30 16:41:01 -0500535
536 return 0;
537}
538
Stephen Warrene315ae82013-06-11 15:14:01 -0600539static int mmc_set_capacity(struct mmc *mmc, int part_num)
540{
541 switch (part_num) {
542 case 0:
543 mmc->capacity = mmc->capacity_user;
544 break;
545 case 1:
546 case 2:
547 mmc->capacity = mmc->capacity_boot;
548 break;
549 case 3:
550 mmc->capacity = mmc->capacity_rpmb;
551 break;
552 case 4:
553 case 5:
554 case 6:
555 case 7:
556 mmc->capacity = mmc->capacity_gp[part_num - 4];
557 break;
558 default:
559 return -1;
560 }
561
Simon Glasse5db1152016-05-01 13:52:35 -0600562 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Stephen Warrene315ae82013-06-11 15:14:01 -0600563
564 return 0;
565}
566
Simon Glass62e293a2016-06-12 23:30:15 -0600567int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
Lei Wen31b99802011-05-02 16:26:26 +0000568{
Stephen Warrene315ae82013-06-11 15:14:01 -0600569 int ret;
Lei Wen31b99802011-05-02 16:26:26 +0000570
Stephen Warrene315ae82013-06-11 15:14:01 -0600571 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
572 (mmc->part_config & ~PART_ACCESS_MASK)
573 | (part_num & PART_ACCESS_MASK));
Peter Bigot45fde892014-09-02 18:31:23 -0500574
575 /*
576 * Set the capacity if the switch succeeded or was intended
577 * to return to representing the raw device.
578 */
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700579 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
Peter Bigot45fde892014-09-02 18:31:23 -0500580 ret = mmc_set_capacity(mmc, part_num);
Simon Glass984db5d2016-05-01 13:52:37 -0600581 mmc_get_blk_desc(mmc)->hwpart = part_num;
Stephen Warren1e0f92a2015-12-07 11:38:49 -0700582 }
Stephen Warrene315ae82013-06-11 15:14:01 -0600583
Peter Bigot45fde892014-09-02 18:31:23 -0500584 return ret;
Lei Wen31b99802011-05-02 16:26:26 +0000585}
586
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100587int mmc_hwpart_config(struct mmc *mmc,
588 const struct mmc_hwpart_conf *conf,
589 enum mmc_hwpart_conf_mode mode)
590{
591 u8 part_attrs = 0;
592 u32 enh_size_mult;
593 u32 enh_start_addr;
594 u32 gp_size_mult[4];
595 u32 max_enh_size_mult;
596 u32 tot_enh_size_mult = 0;
Diego Santa Cruz80200272014-12-23 10:50:31 +0100597 u8 wr_rel_set;
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100598 int i, pidx, err;
599 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
600
601 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
602 return -EINVAL;
603
604 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
605 printf("eMMC >= 4.4 required for enhanced user data area\n");
606 return -EMEDIUMTYPE;
607 }
608
609 if (!(mmc->part_support & PART_SUPPORT)) {
610 printf("Card does not support partitioning\n");
611 return -EMEDIUMTYPE;
612 }
613
614 if (!mmc->hc_wp_grp_size) {
615 printf("Card does not define HC WP group size\n");
616 return -EMEDIUMTYPE;
617 }
618
619 /* check partition alignment and total enhanced size */
620 if (conf->user.enh_size) {
621 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
622 conf->user.enh_start % mmc->hc_wp_grp_size) {
623 printf("User data enhanced area not HC WP group "
624 "size aligned\n");
625 return -EINVAL;
626 }
627 part_attrs |= EXT_CSD_ENH_USR;
628 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
629 if (mmc->high_capacity) {
630 enh_start_addr = conf->user.enh_start;
631 } else {
632 enh_start_addr = (conf->user.enh_start << 9);
633 }
634 } else {
635 enh_size_mult = 0;
636 enh_start_addr = 0;
637 }
638 tot_enh_size_mult += enh_size_mult;
639
640 for (pidx = 0; pidx < 4; pidx++) {
641 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
642 printf("GP%i partition not HC WP group size "
643 "aligned\n", pidx+1);
644 return -EINVAL;
645 }
646 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
647 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
648 part_attrs |= EXT_CSD_ENH_GP(pidx);
649 tot_enh_size_mult += gp_size_mult[pidx];
650 }
651 }
652
653 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
654 printf("Card does not support enhanced attribute\n");
655 return -EMEDIUMTYPE;
656 }
657
658 err = mmc_send_ext_csd(mmc, ext_csd);
659 if (err)
660 return err;
661
662 max_enh_size_mult =
663 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
664 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
665 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
666 if (tot_enh_size_mult > max_enh_size_mult) {
667 printf("Total enhanced size exceeds maximum (%u > %u)\n",
668 tot_enh_size_mult, max_enh_size_mult);
669 return -EMEDIUMTYPE;
670 }
671
Diego Santa Cruz80200272014-12-23 10:50:31 +0100672 /* The default value of EXT_CSD_WR_REL_SET is device
673 * dependent, the values can only be changed if the
674 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
675 * changed only once and before partitioning is completed. */
676 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
677 if (conf->user.wr_rel_change) {
678 if (conf->user.wr_rel_set)
679 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
680 else
681 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
682 }
683 for (pidx = 0; pidx < 4; pidx++) {
684 if (conf->gp_part[pidx].wr_rel_change) {
685 if (conf->gp_part[pidx].wr_rel_set)
686 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
687 else
688 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
689 }
690 }
691
692 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
693 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
694 puts("Card does not support host controlled partition write "
695 "reliability settings\n");
696 return -EMEDIUMTYPE;
697 }
698
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100699 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
700 EXT_CSD_PARTITION_SETTING_COMPLETED) {
701 printf("Card already partitioned\n");
702 return -EPERM;
703 }
704
705 if (mode == MMC_HWPART_CONF_CHECK)
706 return 0;
707
708 /* Partitioning requires high-capacity size definitions */
709 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
710 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
711 EXT_CSD_ERASE_GROUP_DEF, 1);
712
713 if (err)
714 return err;
715
716 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
717
718 /* update erase group size to be high-capacity */
719 mmc->erase_grp_size =
720 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
721
722 }
723
724 /* all OK, write the configuration */
725 for (i = 0; i < 4; i++) {
726 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
727 EXT_CSD_ENH_START_ADDR+i,
728 (enh_start_addr >> (i*8)) & 0xFF);
729 if (err)
730 return err;
731 }
732 for (i = 0; i < 3; i++) {
733 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
734 EXT_CSD_ENH_SIZE_MULT+i,
735 (enh_size_mult >> (i*8)) & 0xFF);
736 if (err)
737 return err;
738 }
739 for (pidx = 0; pidx < 4; pidx++) {
740 for (i = 0; i < 3; i++) {
741 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
742 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
743 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
744 if (err)
745 return err;
746 }
747 }
748 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
749 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
750 if (err)
751 return err;
752
753 if (mode == MMC_HWPART_CONF_SET)
754 return 0;
755
Diego Santa Cruz80200272014-12-23 10:50:31 +0100756 /* The WR_REL_SET is a write-once register but shall be
757 * written before setting PART_SETTING_COMPLETED. As it is
758 * write-once we can only write it when completing the
759 * partitioning. */
760 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
761 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
762 EXT_CSD_WR_REL_SET, wr_rel_set);
763 if (err)
764 return err;
765 }
766
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100767 /* Setting PART_SETTING_COMPLETED confirms the partition
768 * configuration but it only becomes effective after power
769 * cycle, so we do not adjust the partition related settings
770 * in the mmc struct. */
771
772 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
773 EXT_CSD_PARTITION_SETTING,
774 EXT_CSD_PARTITION_SETTING_COMPLETED);
775 if (err)
776 return err;
777
778 return 0;
779}
780
Thierry Redingb9c8b772012-01-02 01:15:37 +0000781int mmc_getcd(struct mmc *mmc)
782{
783 int cd;
784
785 cd = board_mmc_getcd(mmc);
786
Peter Korsgaardf7b15102013-03-21 04:00:03 +0000787 if (cd < 0) {
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200788 if (mmc->cfg->ops->getcd)
789 cd = mmc->cfg->ops->getcd(mmc);
Peter Korsgaardf7b15102013-03-21 04:00:03 +0000790 else
791 cd = 1;
792 }
Thierry Redingb9c8b772012-01-02 01:15:37 +0000793
794 return cd;
795}
796
Kim Phillips87ea3892012-10-29 13:34:43 +0000797static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
Andy Flemingad347bb2008-10-30 16:41:01 -0500798{
799 struct mmc_cmd cmd;
800 struct mmc_data data;
801
802 /* Switch the frequency */
803 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
804 cmd.resp_type = MMC_RSP_R1;
805 cmd.cmdarg = (mode << 31) | 0xffffff;
806 cmd.cmdarg &= ~(0xf << (group * 4));
807 cmd.cmdarg |= value << (group * 4);
Andy Flemingad347bb2008-10-30 16:41:01 -0500808
809 data.dest = (char *)resp;
810 data.blocksize = 64;
811 data.blocks = 1;
812 data.flags = MMC_DATA_READ;
813
814 return mmc_send_cmd(mmc, &cmd, &data);
815}
816
817
Kim Phillips87ea3892012-10-29 13:34:43 +0000818static int sd_change_freq(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -0500819{
820 int err;
821 struct mmc_cmd cmd;
Anton staaf9b00f0d2011-10-03 13:54:59 +0000822 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
823 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
Andy Flemingad347bb2008-10-30 16:41:01 -0500824 struct mmc_data data;
825 int timeout;
826
827 mmc->card_caps = 0;
828
Thomas Chou1254c3d2010-12-24 13:12:21 +0000829 if (mmc_host_is_spi(mmc))
830 return 0;
831
Andy Flemingad347bb2008-10-30 16:41:01 -0500832 /* Read the SCR to find out if this card supports higher speeds */
833 cmd.cmdidx = MMC_CMD_APP_CMD;
834 cmd.resp_type = MMC_RSP_R1;
835 cmd.cmdarg = mmc->rca << 16;
Andy Flemingad347bb2008-10-30 16:41:01 -0500836
837 err = mmc_send_cmd(mmc, &cmd, NULL);
838
839 if (err)
840 return err;
841
842 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
843 cmd.resp_type = MMC_RSP_R1;
844 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -0500845
846 timeout = 3;
847
848retry_scr:
Anton staaf9b00f0d2011-10-03 13:54:59 +0000849 data.dest = (char *)scr;
Andy Flemingad347bb2008-10-30 16:41:01 -0500850 data.blocksize = 8;
851 data.blocks = 1;
852 data.flags = MMC_DATA_READ;
853
854 err = mmc_send_cmd(mmc, &cmd, &data);
855
856 if (err) {
857 if (timeout--)
858 goto retry_scr;
859
860 return err;
861 }
862
Yauhen Kharuzhy6e8edf42009-05-07 00:43:30 +0300863 mmc->scr[0] = __be32_to_cpu(scr[0]);
864 mmc->scr[1] = __be32_to_cpu(scr[1]);
Andy Flemingad347bb2008-10-30 16:41:01 -0500865
866 switch ((mmc->scr[0] >> 24) & 0xf) {
Bin Meng4a4ef872016-03-17 21:53:13 -0700867 case 0:
868 mmc->version = SD_VERSION_1_0;
869 break;
870 case 1:
871 mmc->version = SD_VERSION_1_10;
872 break;
873 case 2:
874 mmc->version = SD_VERSION_2;
875 if ((mmc->scr[0] >> 15) & 0x1)
876 mmc->version = SD_VERSION_3;
877 break;
878 default:
879 mmc->version = SD_VERSION_1_0;
880 break;
Andy Flemingad347bb2008-10-30 16:41:01 -0500881 }
882
Alagu Sankar24bb5ab2010-05-12 15:08:24 +0530883 if (mmc->scr[0] & SD_DATA_4BIT)
884 mmc->card_caps |= MMC_MODE_4BIT;
885
Andy Flemingad347bb2008-10-30 16:41:01 -0500886 /* Version 1.0 doesn't support switching */
887 if (mmc->version == SD_VERSION_1_0)
888 return 0;
889
890 timeout = 4;
891 while (timeout--) {
892 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
Anton staaf9b00f0d2011-10-03 13:54:59 +0000893 (u8 *)switch_status);
Andy Flemingad347bb2008-10-30 16:41:01 -0500894
895 if (err)
896 return err;
897
898 /* The high-speed function is busy. Try again */
Yauhen Kharuzhy6e8edf42009-05-07 00:43:30 +0300899 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
Andy Flemingad347bb2008-10-30 16:41:01 -0500900 break;
901 }
902
Andy Flemingad347bb2008-10-30 16:41:01 -0500903 /* If high-speed isn't supported, we return */
Yauhen Kharuzhy6e8edf42009-05-07 00:43:30 +0300904 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
Andy Flemingad347bb2008-10-30 16:41:01 -0500905 return 0;
906
Macpaul Lin24e92ec2011-11-28 16:31:09 +0000907 /*
908 * If the host doesn't support SD_HIGHSPEED, do not switch card to
909 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
910 * This can avoid furthur problem when the card runs in different
911 * mode between the host.
912 */
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200913 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
914 (mmc->cfg->host_caps & MMC_MODE_HS)))
Macpaul Lin24e92ec2011-11-28 16:31:09 +0000915 return 0;
916
Anton staaf9b00f0d2011-10-03 13:54:59 +0000917 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
Andy Flemingad347bb2008-10-30 16:41:01 -0500918
919 if (err)
920 return err;
921
Yauhen Kharuzhy6e8edf42009-05-07 00:43:30 +0300922 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
Andy Flemingad347bb2008-10-30 16:41:01 -0500923 mmc->card_caps |= MMC_MODE_HS;
924
925 return 0;
926}
927
928/* frequency bases */
929/* divided by 10 to be nice to platforms without floating point */
Mike Frysingerb588caf2010-10-20 01:15:53 +0000930static const int fbase[] = {
Andy Flemingad347bb2008-10-30 16:41:01 -0500931 10000,
932 100000,
933 1000000,
934 10000000,
935};
936
937/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
938 * to platforms without floating point.
939 */
Simon Glass03317cc2016-05-14 14:02:57 -0600940static const u8 multipliers[] = {
Andy Flemingad347bb2008-10-30 16:41:01 -0500941 0, /* reserved */
942 10,
943 12,
944 13,
945 15,
946 20,
947 25,
948 30,
949 35,
950 40,
951 45,
952 50,
953 55,
954 60,
955 70,
956 80,
957};
958
Kim Phillips87ea3892012-10-29 13:34:43 +0000959static void mmc_set_ios(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -0500960{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200961 if (mmc->cfg->ops->set_ios)
962 mmc->cfg->ops->set_ios(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -0500963}
964
965void mmc_set_clock(struct mmc *mmc, uint clock)
966{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200967 if (clock > mmc->cfg->f_max)
968 clock = mmc->cfg->f_max;
Andy Flemingad347bb2008-10-30 16:41:01 -0500969
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200970 if (clock < mmc->cfg->f_min)
971 clock = mmc->cfg->f_min;
Andy Flemingad347bb2008-10-30 16:41:01 -0500972
973 mmc->clock = clock;
974
975 mmc_set_ios(mmc);
976}
977
Kim Phillips87ea3892012-10-29 13:34:43 +0000978static void mmc_set_bus_width(struct mmc *mmc, uint width)
Andy Flemingad347bb2008-10-30 16:41:01 -0500979{
980 mmc->bus_width = width;
981
982 mmc_set_ios(mmc);
983}
984
Kim Phillips87ea3892012-10-29 13:34:43 +0000985static int mmc_startup(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -0500986{
Stephen Warrene315ae82013-06-11 15:14:01 -0600987 int err, i;
Andy Flemingad347bb2008-10-30 16:41:01 -0500988 uint mult, freq;
Yoshihiro Shimoda7d88de52011-07-04 22:13:26 +0000989 u64 cmult, csize, capacity;
Andy Flemingad347bb2008-10-30 16:41:01 -0500990 struct mmc_cmd cmd;
Simon Glassa09c2b72013-04-03 08:54:30 +0000991 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
992 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000993 int timeout = 1000;
Diego Santa Cruzcea8c5c2014-12-23 10:50:20 +0100994 bool has_parts = false;
Diego Santa Cruza7a75992014-12-23 10:50:27 +0100995 bool part_completed;
Simon Glasse5db1152016-05-01 13:52:35 -0600996 struct blk_desc *bdesc;
Andy Flemingad347bb2008-10-30 16:41:01 -0500997
Thomas Chou1254c3d2010-12-24 13:12:21 +0000998#ifdef CONFIG_MMC_SPI_CRC_ON
999 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1000 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1001 cmd.resp_type = MMC_RSP_R1;
1002 cmd.cmdarg = 1;
Thomas Chou1254c3d2010-12-24 13:12:21 +00001003 err = mmc_send_cmd(mmc, &cmd, NULL);
1004
1005 if (err)
1006 return err;
1007 }
1008#endif
1009
Andy Flemingad347bb2008-10-30 16:41:01 -05001010 /* Put the Card in Identify Mode */
Thomas Chou1254c3d2010-12-24 13:12:21 +00001011 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1012 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
Andy Flemingad347bb2008-10-30 16:41:01 -05001013 cmd.resp_type = MMC_RSP_R2;
1014 cmd.cmdarg = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -05001015
1016 err = mmc_send_cmd(mmc, &cmd, NULL);
1017
1018 if (err)
1019 return err;
1020
1021 memcpy(mmc->cid, cmd.response, 16);
1022
1023 /*
1024 * For MMC cards, set the Relative Address.
1025 * For SD cards, get the Relatvie Address.
1026 * This also puts the cards into Standby State
1027 */
Thomas Chou1254c3d2010-12-24 13:12:21 +00001028 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1029 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1030 cmd.cmdarg = mmc->rca << 16;
1031 cmd.resp_type = MMC_RSP_R6;
Andy Flemingad347bb2008-10-30 16:41:01 -05001032
Thomas Chou1254c3d2010-12-24 13:12:21 +00001033 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Flemingad347bb2008-10-30 16:41:01 -05001034
Thomas Chou1254c3d2010-12-24 13:12:21 +00001035 if (err)
1036 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -05001037
Thomas Chou1254c3d2010-12-24 13:12:21 +00001038 if (IS_SD(mmc))
1039 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1040 }
Andy Flemingad347bb2008-10-30 16:41:01 -05001041
1042 /* Get the Card-Specific Data */
1043 cmd.cmdidx = MMC_CMD_SEND_CSD;
1044 cmd.resp_type = MMC_RSP_R2;
1045 cmd.cmdarg = mmc->rca << 16;
Andy Flemingad347bb2008-10-30 16:41:01 -05001046
1047 err = mmc_send_cmd(mmc, &cmd, NULL);
1048
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +00001049 /* Waiting for the ready status */
1050 mmc_send_status(mmc, timeout);
1051
Andy Flemingad347bb2008-10-30 16:41:01 -05001052 if (err)
1053 return err;
1054
Rabin Vincentb6eed942009-04-05 13:30:56 +05301055 mmc->csd[0] = cmd.response[0];
1056 mmc->csd[1] = cmd.response[1];
1057 mmc->csd[2] = cmd.response[2];
1058 mmc->csd[3] = cmd.response[3];
Andy Flemingad347bb2008-10-30 16:41:01 -05001059
1060 if (mmc->version == MMC_VERSION_UNKNOWN) {
Rabin Vincentbdf7a682009-04-05 13:30:55 +05301061 int version = (cmd.response[0] >> 26) & 0xf;
Andy Flemingad347bb2008-10-30 16:41:01 -05001062
1063 switch (version) {
Bin Meng4a4ef872016-03-17 21:53:13 -07001064 case 0:
1065 mmc->version = MMC_VERSION_1_2;
1066 break;
1067 case 1:
1068 mmc->version = MMC_VERSION_1_4;
1069 break;
1070 case 2:
1071 mmc->version = MMC_VERSION_2_2;
1072 break;
1073 case 3:
1074 mmc->version = MMC_VERSION_3;
1075 break;
1076 case 4:
1077 mmc->version = MMC_VERSION_4;
1078 break;
1079 default:
1080 mmc->version = MMC_VERSION_1_2;
1081 break;
Andy Flemingad347bb2008-10-30 16:41:01 -05001082 }
1083 }
1084
1085 /* divide frequency by 10, since the mults are 10x bigger */
Rabin Vincentbdf7a682009-04-05 13:30:55 +05301086 freq = fbase[(cmd.response[0] & 0x7)];
1087 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
Andy Flemingad347bb2008-10-30 16:41:01 -05001088
1089 mmc->tran_speed = freq * mult;
1090
Markus Niebel03951412013-12-16 13:40:46 +01001091 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
Rabin Vincentb6eed942009-04-05 13:30:56 +05301092 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
Andy Flemingad347bb2008-10-30 16:41:01 -05001093
1094 if (IS_SD(mmc))
1095 mmc->write_bl_len = mmc->read_bl_len;
1096 else
Rabin Vincentb6eed942009-04-05 13:30:56 +05301097 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
Andy Flemingad347bb2008-10-30 16:41:01 -05001098
1099 if (mmc->high_capacity) {
1100 csize = (mmc->csd[1] & 0x3f) << 16
1101 | (mmc->csd[2] & 0xffff0000) >> 16;
1102 cmult = 8;
1103 } else {
1104 csize = (mmc->csd[1] & 0x3ff) << 2
1105 | (mmc->csd[2] & 0xc0000000) >> 30;
1106 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1107 }
1108
Stephen Warrene315ae82013-06-11 15:14:01 -06001109 mmc->capacity_user = (csize + 1) << (cmult + 2);
1110 mmc->capacity_user *= mmc->read_bl_len;
1111 mmc->capacity_boot = 0;
1112 mmc->capacity_rpmb = 0;
1113 for (i = 0; i < 4; i++)
1114 mmc->capacity_gp[i] = 0;
Andy Flemingad347bb2008-10-30 16:41:01 -05001115
Simon Glassa09c2b72013-04-03 08:54:30 +00001116 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1117 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
Andy Flemingad347bb2008-10-30 16:41:01 -05001118
Simon Glassa09c2b72013-04-03 08:54:30 +00001119 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1120 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
Andy Flemingad347bb2008-10-30 16:41:01 -05001121
Markus Niebel03951412013-12-16 13:40:46 +01001122 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1123 cmd.cmdidx = MMC_CMD_SET_DSR;
1124 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1125 cmd.resp_type = MMC_RSP_NONE;
1126 if (mmc_send_cmd(mmc, &cmd, NULL))
1127 printf("MMC: SET_DSR failed\n");
1128 }
1129
Andy Flemingad347bb2008-10-30 16:41:01 -05001130 /* Select the card, and put it into Transfer Mode */
Thomas Chou1254c3d2010-12-24 13:12:21 +00001131 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1132 cmd.cmdidx = MMC_CMD_SELECT_CARD;
Ajay Bhargav4a32fba2011-10-05 03:13:23 +00001133 cmd.resp_type = MMC_RSP_R1;
Thomas Chou1254c3d2010-12-24 13:12:21 +00001134 cmd.cmdarg = mmc->rca << 16;
Thomas Chou1254c3d2010-12-24 13:12:21 +00001135 err = mmc_send_cmd(mmc, &cmd, NULL);
Andy Flemingad347bb2008-10-30 16:41:01 -05001136
Thomas Chou1254c3d2010-12-24 13:12:21 +00001137 if (err)
1138 return err;
1139 }
Andy Flemingad347bb2008-10-30 16:41:01 -05001140
Lei Wenea526762011-06-22 17:03:31 +00001141 /*
1142 * For SD, its erase group is always one sector
1143 */
1144 mmc->erase_grp_size = 1;
Lei Wen31b99802011-05-02 16:26:26 +00001145 mmc->part_config = MMCPART_NOAVAILABLE;
Sukumar Ghorai232293c2010-09-20 18:29:29 +05301146 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1147 /* check ext_csd version and capacity */
1148 err = mmc_send_ext_csd(mmc, ext_csd);
Diego Santa Cruzca25e062014-12-23 10:50:28 +01001149 if (err)
1150 return err;
1151 if (ext_csd[EXT_CSD_REV] >= 2) {
Yoshihiro Shimoda7d88de52011-07-04 22:13:26 +00001152 /*
1153 * According to the JEDEC Standard, the value of
1154 * ext_csd's capacity is valid if the value is more
1155 * than 2GB
1156 */
Lei Wen217467f2011-10-03 20:35:10 +00001157 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1158 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1159 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1160 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
Simon Glassa09c2b72013-04-03 08:54:30 +00001161 capacity *= MMC_MAX_BLOCK_LEN;
Łukasz Majewski237823e2011-07-05 02:19:44 +00001162 if ((capacity >> 20) > 2 * 1024)
Stephen Warrene315ae82013-06-11 15:14:01 -06001163 mmc->capacity_user = capacity;
Sukumar Ghorai232293c2010-09-20 18:29:29 +05301164 }
Lei Wen31b99802011-05-02 16:26:26 +00001165
Jaehoon Chung6108ef62013-01-29 19:31:16 +00001166 switch (ext_csd[EXT_CSD_REV]) {
1167 case 1:
1168 mmc->version = MMC_VERSION_4_1;
1169 break;
1170 case 2:
1171 mmc->version = MMC_VERSION_4_2;
1172 break;
1173 case 3:
1174 mmc->version = MMC_VERSION_4_3;
1175 break;
1176 case 5:
1177 mmc->version = MMC_VERSION_4_41;
1178 break;
1179 case 6:
1180 mmc->version = MMC_VERSION_4_5;
1181 break;
Markus Niebel32f53b62014-11-18 15:13:53 +01001182 case 7:
1183 mmc->version = MMC_VERSION_5_0;
1184 break;
Stefan Wahren1243cd82016-06-16 17:54:06 +00001185 case 8:
1186 mmc->version = MMC_VERSION_5_1;
1187 break;
Jaehoon Chung6108ef62013-01-29 19:31:16 +00001188 }
1189
Diego Santa Cruza7a75992014-12-23 10:50:27 +01001190 /* The partition data may be non-zero but it is only
1191 * effective if PARTITION_SETTING_COMPLETED is set in
1192 * EXT_CSD, so ignore any data if this bit is not set,
1193 * except for enabling the high-capacity group size
1194 * definition (see below). */
1195 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1196 EXT_CSD_PARTITION_SETTING_COMPLETED);
1197
Diego Santa Cruzcea8c5c2014-12-23 10:50:20 +01001198 /* store the partition info of emmc */
1199 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1200 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1201 ext_csd[EXT_CSD_BOOT_MULT])
1202 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
Diego Santa Cruza7a75992014-12-23 10:50:27 +01001203 if (part_completed &&
1204 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
Diego Santa Cruzcea8c5c2014-12-23 10:50:20 +01001205 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1206
1207 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1208
1209 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1210
1211 for (i = 0; i < 4; i++) {
1212 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
Diego Santa Cruza7a75992014-12-23 10:50:27 +01001213 uint mult = (ext_csd[idx + 2] << 16) +
Diego Santa Cruzcea8c5c2014-12-23 10:50:20 +01001214 (ext_csd[idx + 1] << 8) + ext_csd[idx];
Diego Santa Cruza7a75992014-12-23 10:50:27 +01001215 if (mult)
1216 has_parts = true;
1217 if (!part_completed)
1218 continue;
1219 mmc->capacity_gp[i] = mult;
Diego Santa Cruzcea8c5c2014-12-23 10:50:20 +01001220 mmc->capacity_gp[i] *=
1221 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1222 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
Diego Santa Cruze5a2a3a2014-12-23 10:50:21 +01001223 mmc->capacity_gp[i] <<= 19;
Diego Santa Cruzcea8c5c2014-12-23 10:50:20 +01001224 }
1225
Diego Santa Cruza7a75992014-12-23 10:50:27 +01001226 if (part_completed) {
1227 mmc->enh_user_size =
1228 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1229 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1230 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1231 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1232 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1233 mmc->enh_user_size <<= 19;
1234 mmc->enh_user_start =
1235 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1236 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1237 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1238 ext_csd[EXT_CSD_ENH_START_ADDR];
1239 if (mmc->high_capacity)
1240 mmc->enh_user_start <<= 9;
1241 }
Diego Santa Cruz3b62d842014-12-23 10:50:22 +01001242
Lei Wenea526762011-06-22 17:03:31 +00001243 /*
Oliver Metzb3f14092013-10-01 20:32:07 +02001244 * Host needs to enable ERASE_GRP_DEF bit if device is
1245 * partitioned. This bit will be lost every time after a reset
1246 * or power off. This will affect erase size.
Lei Wenea526762011-06-22 17:03:31 +00001247 */
Diego Santa Cruza7a75992014-12-23 10:50:27 +01001248 if (part_completed)
Diego Santa Cruzcea8c5c2014-12-23 10:50:20 +01001249 has_parts = true;
Oliver Metzb3f14092013-10-01 20:32:07 +02001250 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
Diego Santa Cruzcea8c5c2014-12-23 10:50:20 +01001251 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1252 has_parts = true;
1253 if (has_parts) {
Oliver Metzb3f14092013-10-01 20:32:07 +02001254 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1255 EXT_CSD_ERASE_GROUP_DEF, 1);
1256
1257 if (err)
1258 return err;
Hannes Petermaier15e874d2014-08-08 09:47:22 +02001259 else
1260 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
Diego Santa Cruz61b78fe2014-12-23 10:50:25 +01001261 }
Oliver Metzb3f14092013-10-01 20:32:07 +02001262
Diego Santa Cruz61b78fe2014-12-23 10:50:25 +01001263 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
Oliver Metzb3f14092013-10-01 20:32:07 +02001264 /* Read out group size from ext_csd */
Lei Wen217467f2011-10-03 20:35:10 +00001265 mmc->erase_grp_size =
Diego Santa Cruz747f6fa2014-12-23 10:50:24 +01001266 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
Markus Niebel6d398922014-11-18 15:11:42 +01001267 /*
1268 * if high capacity and partition setting completed
1269 * SEC_COUNT is valid even if it is smaller than 2 GiB
1270 * JEDEC Standard JESD84-B45, 6.2.4
1271 */
Diego Santa Cruza7a75992014-12-23 10:50:27 +01001272 if (mmc->high_capacity && part_completed) {
Markus Niebel6d398922014-11-18 15:11:42 +01001273 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1274 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1275 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1276 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1277 capacity *= MMC_MAX_BLOCK_LEN;
1278 mmc->capacity_user = capacity;
1279 }
Simon Glassa09c2b72013-04-03 08:54:30 +00001280 } else {
Oliver Metzb3f14092013-10-01 20:32:07 +02001281 /* Calculate the group size from the csd value. */
Lei Wenea526762011-06-22 17:03:31 +00001282 int erase_gsz, erase_gmul;
1283 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1284 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1285 mmc->erase_grp_size = (erase_gsz + 1)
1286 * (erase_gmul + 1);
1287 }
Diego Santa Cruz61b78fe2014-12-23 10:50:25 +01001288
1289 mmc->hc_wp_grp_size = 1024
1290 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1291 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
Diego Santa Cruz37a50b92014-12-23 10:50:33 +01001292
1293 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
Sukumar Ghorai232293c2010-09-20 18:29:29 +05301294 }
1295
Simon Glasse5db1152016-05-01 13:52:35 -06001296 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
Stephen Warrene315ae82013-06-11 15:14:01 -06001297 if (err)
1298 return err;
1299
Andy Flemingad347bb2008-10-30 16:41:01 -05001300 if (IS_SD(mmc))
1301 err = sd_change_freq(mmc);
1302 else
1303 err = mmc_change_freq(mmc);
1304
1305 if (err)
1306 return err;
1307
1308 /* Restrict card's capabilities by what the host can do */
Pantelis Antoniou2c850462014-03-11 19:34:20 +02001309 mmc->card_caps &= mmc->cfg->host_caps;
Andy Flemingad347bb2008-10-30 16:41:01 -05001310
1311 if (IS_SD(mmc)) {
1312 if (mmc->card_caps & MMC_MODE_4BIT) {
1313 cmd.cmdidx = MMC_CMD_APP_CMD;
1314 cmd.resp_type = MMC_RSP_R1;
1315 cmd.cmdarg = mmc->rca << 16;
Andy Flemingad347bb2008-10-30 16:41:01 -05001316
1317 err = mmc_send_cmd(mmc, &cmd, NULL);
1318 if (err)
1319 return err;
1320
1321 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1322 cmd.resp_type = MMC_RSP_R1;
1323 cmd.cmdarg = 2;
Andy Flemingad347bb2008-10-30 16:41:01 -05001324 err = mmc_send_cmd(mmc, &cmd, NULL);
1325 if (err)
1326 return err;
1327
1328 mmc_set_bus_width(mmc, 4);
1329 }
1330
1331 if (mmc->card_caps & MMC_MODE_HS)
Jaehoon Chunge1d4c7b2012-03-26 21:16:03 +00001332 mmc->tran_speed = 50000000;
Andy Flemingad347bb2008-10-30 16:41:01 -05001333 else
Jaehoon Chunge1d4c7b2012-03-26 21:16:03 +00001334 mmc->tran_speed = 25000000;
Andrew Gabbasovccb7b042014-12-25 10:22:25 -06001335 } else if (mmc->version >= MMC_VERSION_4) {
1336 /* Only version 4 of MMC supports wider bus widths */
Andy Flemingeb766ad2012-10-31 19:02:38 +00001337 int idx;
1338
1339 /* An array of possible bus widths in order of preference */
1340 static unsigned ext_csd_bits[] = {
Jaehoon Chung38ce30b2014-05-16 13:59:54 +09001341 EXT_CSD_DDR_BUS_WIDTH_8,
1342 EXT_CSD_DDR_BUS_WIDTH_4,
Andy Flemingeb766ad2012-10-31 19:02:38 +00001343 EXT_CSD_BUS_WIDTH_8,
1344 EXT_CSD_BUS_WIDTH_4,
1345 EXT_CSD_BUS_WIDTH_1,
1346 };
1347
1348 /* An array to map CSD bus widths to host cap bits */
1349 static unsigned ext_to_hostcaps[] = {
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001350 [EXT_CSD_DDR_BUS_WIDTH_4] =
1351 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1352 [EXT_CSD_DDR_BUS_WIDTH_8] =
1353 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
Andy Flemingeb766ad2012-10-31 19:02:38 +00001354 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1355 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1356 };
1357
1358 /* An array to map chosen bus width to an integer */
1359 static unsigned widths[] = {
Jaehoon Chung38ce30b2014-05-16 13:59:54 +09001360 8, 4, 8, 4, 1,
Andy Flemingeb766ad2012-10-31 19:02:38 +00001361 };
1362
1363 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1364 unsigned int extw = ext_csd_bits[idx];
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001365 unsigned int caps = ext_to_hostcaps[extw];
Andy Flemingeb766ad2012-10-31 19:02:38 +00001366
1367 /*
Andrew Gabbasovc1b2cf02014-12-25 10:22:24 -06001368 * If the bus width is still not changed,
1369 * don't try to set the default again.
1370 * Otherwise, recover from switch attempts
1371 * by switching to 1-bit bus width.
1372 */
1373 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1374 mmc->bus_width == 1) {
1375 err = 0;
1376 break;
1377 }
1378
1379 /*
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001380 * Check to make sure the card and controller support
1381 * these capabilities
Andy Flemingeb766ad2012-10-31 19:02:38 +00001382 */
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001383 if ((mmc->card_caps & caps) != caps)
Andy Flemingeb766ad2012-10-31 19:02:38 +00001384 continue;
1385
Andy Flemingad347bb2008-10-30 16:41:01 -05001386 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
Andy Flemingeb766ad2012-10-31 19:02:38 +00001387 EXT_CSD_BUS_WIDTH, extw);
Andy Flemingad347bb2008-10-30 16:41:01 -05001388
1389 if (err)
Lei Wen4f5a6a52011-10-03 20:35:11 +00001390 continue;
Andy Flemingad347bb2008-10-30 16:41:01 -05001391
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001392 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
Andy Flemingeb766ad2012-10-31 19:02:38 +00001393 mmc_set_bus_width(mmc, widths[idx]);
Andy Flemingad347bb2008-10-30 16:41:01 -05001394
Lei Wen4f5a6a52011-10-03 20:35:11 +00001395 err = mmc_send_ext_csd(mmc, test_csd);
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001396
1397 if (err)
1398 continue;
Andy Flemingad347bb2008-10-30 16:41:01 -05001399
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001400 /* Only compare read only fields */
1401 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1402 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1403 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1404 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1405 ext_csd[EXT_CSD_REV]
1406 == test_csd[EXT_CSD_REV] &&
1407 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1408 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1409 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1410 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
Lei Wen4f5a6a52011-10-03 20:35:11 +00001411 break;
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001412 else
1413 err = SWITCH_ERR;
Andy Flemingad347bb2008-10-30 16:41:01 -05001414 }
1415
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001416 if (err)
1417 return err;
1418
Andy Flemingad347bb2008-10-30 16:41:01 -05001419 if (mmc->card_caps & MMC_MODE_HS) {
1420 if (mmc->card_caps & MMC_MODE_HS_52MHz)
Jaehoon Chunge1d4c7b2012-03-26 21:16:03 +00001421 mmc->tran_speed = 52000000;
Andy Flemingad347bb2008-10-30 16:41:01 -05001422 else
Jaehoon Chunge1d4c7b2012-03-26 21:16:03 +00001423 mmc->tran_speed = 26000000;
1424 }
Andy Flemingad347bb2008-10-30 16:41:01 -05001425 }
1426
Jaehoon Chunge1d4c7b2012-03-26 21:16:03 +00001427 mmc_set_clock(mmc, mmc->tran_speed);
1428
Andrew Gabbasov532663b2014-12-01 06:59:11 -06001429 /* Fix the block length for DDR mode */
1430 if (mmc->ddr_mode) {
1431 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1432 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1433 }
1434
Andy Flemingad347bb2008-10-30 16:41:01 -05001435 /* fill in device description */
Simon Glasse5db1152016-05-01 13:52:35 -06001436 bdesc = mmc_get_blk_desc(mmc);
1437 bdesc->lun = 0;
1438 bdesc->hwpart = 0;
1439 bdesc->type = 0;
1440 bdesc->blksz = mmc->read_bl_len;
1441 bdesc->log2blksz = LOG2(bdesc->blksz);
1442 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
Sjoerd Simonsd67754f2015-12-04 23:27:40 +01001443#if !defined(CONFIG_SPL_BUILD) || \
1444 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1445 !defined(CONFIG_USE_TINY_PRINTF))
Simon Glasse5db1152016-05-01 13:52:35 -06001446 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
Taylor Hutt7367ec22012-10-20 17:15:59 +00001447 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1448 (mmc->cid[3] >> 16) & 0xffff);
Simon Glasse5db1152016-05-01 13:52:35 -06001449 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
Taylor Hutt7367ec22012-10-20 17:15:59 +00001450 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1451 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1452 (mmc->cid[2] >> 24) & 0xff);
Simon Glasse5db1152016-05-01 13:52:35 -06001453 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
Taylor Hutt7367ec22012-10-20 17:15:59 +00001454 (mmc->cid[2] >> 16) & 0xf);
Paul Burton6a7c5ba2013-09-04 16:12:25 +01001455#else
Simon Glasse5db1152016-05-01 13:52:35 -06001456 bdesc->vendor[0] = 0;
1457 bdesc->product[0] = 0;
1458 bdesc->revision[0] = 0;
Paul Burton6a7c5ba2013-09-04 16:12:25 +01001459#endif
Mikhail Kshevetskiy5cbfa8e7a2012-07-09 08:53:38 +00001460#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
Simon Glasse5db1152016-05-01 13:52:35 -06001461 part_init(bdesc);
Mikhail Kshevetskiy5cbfa8e7a2012-07-09 08:53:38 +00001462#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001463
1464 return 0;
1465}
1466
Kim Phillips87ea3892012-10-29 13:34:43 +00001467static int mmc_send_if_cond(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05001468{
1469 struct mmc_cmd cmd;
1470 int err;
1471
1472 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1473 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
Pantelis Antoniou2c850462014-03-11 19:34:20 +02001474 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
Andy Flemingad347bb2008-10-30 16:41:01 -05001475 cmd.resp_type = MMC_RSP_R7;
Andy Flemingad347bb2008-10-30 16:41:01 -05001476
1477 err = mmc_send_cmd(mmc, &cmd, NULL);
1478
1479 if (err)
1480 return err;
1481
Rabin Vincentb6eed942009-04-05 13:30:56 +05301482 if ((cmd.response[0] & 0xff) != 0xaa)
Andy Flemingad347bb2008-10-30 16:41:01 -05001483 return UNUSABLE_ERR;
1484 else
1485 mmc->version = SD_VERSION_2;
1486
1487 return 0;
1488}
1489
Paul Kocialkowski2439fe92014-11-08 20:55:45 +01001490/* board-specific MMC power initializations. */
1491__weak void board_mmc_power_init(void)
1492{
1493}
1494
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001495int mmc_start_init(struct mmc *mmc)
Andy Flemingad347bb2008-10-30 16:41:01 -05001496{
Macpaul Lin028bde12011-11-14 23:35:39 +00001497 int err;
Andy Flemingad347bb2008-10-30 16:41:01 -05001498
Pantelis Antoniouc9e75912014-02-26 19:28:45 +02001499 /* we pretend there's no card when init is NULL */
Pantelis Antoniou2c850462014-03-11 19:34:20 +02001500 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
Thierry Redingb9c8b772012-01-02 01:15:37 +00001501 mmc->has_init = 0;
Paul Burton6a7c5ba2013-09-04 16:12:25 +01001502#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Thierry Redingb9c8b772012-01-02 01:15:37 +00001503 printf("MMC: no card present\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +01001504#endif
Thierry Redingb9c8b772012-01-02 01:15:37 +00001505 return NO_CARD_ERR;
1506 }
1507
Lei Wen31b99802011-05-02 16:26:26 +00001508 if (mmc->has_init)
1509 return 0;
1510
Yangbo Lub124f8a2015-04-22 13:57:00 +08001511#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1512 mmc_adapter_card_type_ident();
1513#endif
Paul Kocialkowski2439fe92014-11-08 20:55:45 +01001514 board_mmc_power_init();
1515
Pantelis Antoniouc9e75912014-02-26 19:28:45 +02001516 /* made sure it's not NULL earlier */
Pantelis Antoniou2c850462014-03-11 19:34:20 +02001517 err = mmc->cfg->ops->init(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05001518
1519 if (err)
1520 return err;
1521
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -06001522 mmc->ddr_mode = 0;
Ilya Yanok8459aab2009-06-29 17:53:16 +04001523 mmc_set_bus_width(mmc, 1);
1524 mmc_set_clock(mmc, 1);
1525
Andy Flemingad347bb2008-10-30 16:41:01 -05001526 /* Reset the Card */
1527 err = mmc_go_idle(mmc);
1528
1529 if (err)
1530 return err;
1531
Lei Wen31b99802011-05-02 16:26:26 +00001532 /* The internal partition reset to user partition(0) at every CMD0*/
Simon Glasse5db1152016-05-01 13:52:35 -06001533 mmc_get_blk_desc(mmc)->hwpart = 0;
Lei Wen31b99802011-05-02 16:26:26 +00001534
Andy Flemingad347bb2008-10-30 16:41:01 -05001535 /* Test for SD version 2 */
Macpaul Lin028bde12011-11-14 23:35:39 +00001536 err = mmc_send_if_cond(mmc);
Andy Flemingad347bb2008-10-30 16:41:01 -05001537
Andy Flemingad347bb2008-10-30 16:41:01 -05001538 /* Now try to get the SD card's operating condition */
1539 err = sd_send_op_cond(mmc);
1540
1541 /* If the command timed out, we check for an MMC card */
1542 if (err == TIMEOUT) {
1543 err = mmc_send_op_cond(mmc);
1544
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05001545 if (err) {
Paul Burton6a7c5ba2013-09-04 16:12:25 +01001546#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
Andy Flemingad347bb2008-10-30 16:41:01 -05001547 printf("Card did not respond to voltage select!\n");
Paul Burton6a7c5ba2013-09-04 16:12:25 +01001548#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001549 return UNUSABLE_ERR;
1550 }
1551 }
1552
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05001553 if (!err)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001554 mmc->init_in_progress = 1;
1555
1556 return err;
1557}
1558
1559static int mmc_complete_init(struct mmc *mmc)
1560{
1561 int err = 0;
1562
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05001563 mmc->init_in_progress = 0;
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001564 if (mmc->op_cond_pending)
1565 err = mmc_complete_op_cond(mmc);
1566
1567 if (!err)
1568 err = mmc_startup(mmc);
Lei Wen31b99802011-05-02 16:26:26 +00001569 if (err)
1570 mmc->has_init = 0;
1571 else
1572 mmc->has_init = 1;
1573 return err;
Andy Flemingad347bb2008-10-30 16:41:01 -05001574}
1575
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001576int mmc_init(struct mmc *mmc)
1577{
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05001578 int err = 0;
Mateusz Zalegada351782014-04-29 20:15:30 +02001579 unsigned start;
Simon Glass59bc6f22016-05-01 13:52:41 -06001580#ifdef CONFIG_DM_MMC
1581 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001582
Simon Glass59bc6f22016-05-01 13:52:41 -06001583 upriv->mmc = mmc;
1584#endif
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001585 if (mmc->has_init)
1586 return 0;
Mateusz Zalegada351782014-04-29 20:15:30 +02001587
1588 start = get_timer(0);
1589
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001590 if (!mmc->init_in_progress)
1591 err = mmc_start_init(mmc);
1592
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -05001593 if (!err)
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001594 err = mmc_complete_init(mmc);
1595 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1596 return err;
1597}
1598
Markus Niebel03951412013-12-16 13:40:46 +01001599int mmc_set_dsr(struct mmc *mmc, u16 val)
1600{
1601 mmc->dsr = val;
1602 return 0;
1603}
1604
Jeroen Hofstee47726302014-07-10 22:46:28 +02001605/* CPU-specific MMC initializations */
1606__weak int cpu_mmc_init(bd_t *bis)
Andy Flemingad347bb2008-10-30 16:41:01 -05001607{
1608 return -1;
1609}
1610
Jeroen Hofstee47726302014-07-10 22:46:28 +02001611/* board-specific MMC initializations. */
1612__weak int board_mmc_init(bd_t *bis)
1613{
1614 return -1;
1615}
Andy Flemingad347bb2008-10-30 16:41:01 -05001616
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001617void mmc_set_preinit(struct mmc *mmc, int preinit)
1618{
1619 mmc->preinit = preinit;
1620}
1621
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06001622#if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1623static int mmc_probe(bd_t *bis)
1624{
1625 return 0;
1626}
1627#elif defined(CONFIG_DM_MMC)
1628static int mmc_probe(bd_t *bis)
1629{
Simon Glass547cb342015-12-29 05:22:49 -07001630 int ret, i;
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06001631 struct uclass *uc;
Simon Glass547cb342015-12-29 05:22:49 -07001632 struct udevice *dev;
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06001633
1634 ret = uclass_get(UCLASS_MMC, &uc);
1635 if (ret)
1636 return ret;
1637
Simon Glass547cb342015-12-29 05:22:49 -07001638 /*
1639 * Try to add them in sequence order. Really with driver model we
1640 * should allow holes, but the current MMC list does not allow that.
1641 * So if we request 0, 1, 3 we will get 0, 1, 2.
1642 */
1643 for (i = 0; ; i++) {
1644 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1645 if (ret == -ENODEV)
1646 break;
1647 }
1648 uclass_foreach_dev(dev, uc) {
1649 ret = device_probe(dev);
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06001650 if (ret)
Simon Glass547cb342015-12-29 05:22:49 -07001651 printf("%s - probe failed: %d\n", dev->name, ret);
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06001652 }
1653
1654 return 0;
1655}
1656#else
1657static int mmc_probe(bd_t *bis)
1658{
1659 if (board_mmc_init(bis) < 0)
1660 cpu_mmc_init(bis);
1661
1662 return 0;
1663}
1664#endif
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +00001665
Andy Flemingad347bb2008-10-30 16:41:01 -05001666int mmc_initialize(bd_t *bis)
1667{
Daniel Kochmański13df57b2015-05-29 16:55:43 +02001668 static int initialized = 0;
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06001669 int ret;
Daniel Kochmański13df57b2015-05-29 16:55:43 +02001670 if (initialized) /* Avoid initializing mmc multiple times */
1671 return 0;
1672 initialized = 1;
1673
Simon Glasse5db1152016-05-01 13:52:35 -06001674#ifndef CONFIG_BLK
1675 mmc_list_init();
1676#endif
Sjoerd Simonsdf8aa522015-08-30 16:55:45 -06001677 ret = mmc_probe(bis);
1678 if (ret)
1679 return ret;
Andy Flemingad347bb2008-10-30 16:41:01 -05001680
Ying Zhang9ff70262013-08-16 15:16:11 +08001681#ifndef CONFIG_SPL_BUILD
Andy Flemingad347bb2008-10-30 16:41:01 -05001682 print_mmc_devices(',');
Ying Zhang9ff70262013-08-16 15:16:11 +08001683#endif
Andy Flemingad347bb2008-10-30 16:41:01 -05001684
Simon Glasse5db1152016-05-01 13:52:35 -06001685 mmc_do_preinit();
Andy Flemingad347bb2008-10-30 16:41:01 -05001686 return 0;
1687}