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git01.mediatek.com / filogic / uboot / 83c83eff41c21b8ddc0d110efbd35f1ea0e0c353 / . / drivers / power / regulator / as3722_regulator.c
blob: 8d60965fe9ac2dab11ee0c885704379f4e013c59 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]2/*
3 * Copyright (C) 2017 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 *
6 * Placeholder regulator driver for as3722.
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]7 */
8
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]9#include <dm.h>
10#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]11#include <log.h>
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]12#include <power/as3722.h>
13#include <power/pmic.h>
14#include <power/regulator.h>
15
Marcel Ziswileree107b32018-05-08 17:34:08 +0200[diff] [blame]16#define AS3722_LDO_CONTROL0_MAX_INDEX 7
17
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]18static int stepdown_get_value(struct udevice *dev)
19{
20 return -ENOSYS;
21}
22
23static int stepdown_set_value(struct udevice *dev, int uvolt)
24{
25 return -ENOSYS;
26}
27
28static int stepdown_set_enable(struct udevice *dev, bool enable)
29{
30 struct udevice *pmic = dev_get_parent(dev);
31 int sd = dev->driver_data;
32 int ret;
33
34 ret = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
35 if (ret < 0) {
36 debug("%s: failed to write SD control register: %d", __func__,
37 ret);
38 return ret;
39 }
40
41 return 0;
42}
43
44static int stepdown_get_enable(struct udevice *dev)
45{
46 struct udevice *pmic = dev_get_parent(dev);
47 int sd = dev->driver_data;
48 int ret;
49
50 ret = pmic_reg_read(pmic, AS3722_SD_CONTROL);
51 if (ret < 0) {
52 debug("%s: failed to read SD control register: %d", __func__,
53 ret);
54 return ret;
55 }
56
57 return ret & (1 << sd) ? true : false;
58}
59
60static int ldo_get_value(struct udevice *dev)
61{
62 return -ENOSYS;
63}
64
65static int ldo_set_value(struct udevice *dev, int uvolt)
66{
67 return -ENOSYS;
68}
69
70static int ldo_set_enable(struct udevice *dev, bool enable)
71{
72 struct udevice *pmic = dev_get_parent(dev);
Marcel Ziswileree107b32018-05-08 17:34:08 +0200[diff] [blame]73 u8 ctrl_reg = AS3722_LDO_CONTROL0;
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]74 int ldo = dev->driver_data;
75 int ret;
76
Marcel Ziswileree107b32018-05-08 17:34:08 +0200[diff] [blame]77 if (ldo > AS3722_LDO_CONTROL0_MAX_INDEX) {
78 ctrl_reg = AS3722_LDO_CONTROL1;
79 ldo -= 8;
80 }
81
82 ret = pmic_clrsetbits(pmic, ctrl_reg, !enable << ldo, enable << ldo);
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]83 if (ret < 0) {
84 debug("%s: failed to write LDO control register: %d", __func__,
85 ret);
86 return ret;
87 }
88
89 return 0;
90}
91
92static int ldo_get_enable(struct udevice *dev)
93{
94 struct udevice *pmic = dev_get_parent(dev);
Marcel Ziswileree107b32018-05-08 17:34:08 +0200[diff] [blame]95 u8 ctrl_reg = AS3722_LDO_CONTROL0;
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]96 int ldo = dev->driver_data;
97 int ret;
98
Marcel Ziswileree107b32018-05-08 17:34:08 +0200[diff] [blame]99 if (ldo > AS3722_LDO_CONTROL0_MAX_INDEX) {
100 ctrl_reg = AS3722_LDO_CONTROL1;
101 ldo -= 8;
102 }
103
104 ret = pmic_reg_read(pmic, ctrl_reg);
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]105 if (ret < 0) {
106 debug("%s: failed to read SD control register: %d", __func__,
107 ret);
108 return ret;
109 }
110
111 return ret & (1 << ldo) ? true : false;
112}
113
114static int as3722_stepdown_probe(struct udevice *dev)
115{
Simon Glass71fa5b42020-12-03 16:55:18 -0700[diff] [blame]116 struct dm_regulator_uclass_plat *uc_pdata;
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]117
Simon Glass71fa5b42020-12-03 16:55:18 -0700[diff] [blame]118 uc_pdata = dev_get_uclass_plat(dev);
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]119
120 uc_pdata->type = REGULATOR_TYPE_BUCK;
121
122 return 0;
123}
124
125static int as3722_ldo_probe(struct udevice *dev)
126{
Simon Glass71fa5b42020-12-03 16:55:18 -0700[diff] [blame]127 struct dm_regulator_uclass_plat *uc_pdata;
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]128
Simon Glass71fa5b42020-12-03 16:55:18 -0700[diff] [blame]129 uc_pdata = dev_get_uclass_plat(dev);
Simon Glass8f189512017-07-25 08:30:10 -0600[diff] [blame]130
131 uc_pdata->type = REGULATOR_TYPE_LDO;
132
133 return 0;
134}
135
136static const struct dm_regulator_ops as3722_stepdown_ops = {
137 .get_value = stepdown_get_value,
138 .set_value = stepdown_set_value,
139 .get_enable = stepdown_get_enable,
140 .set_enable = stepdown_set_enable,
141};
142
143static const struct dm_regulator_ops as3722_ldo_ops = {
144 .get_value = ldo_get_value,
145 .set_value = ldo_set_value,
146 .get_enable = ldo_get_enable,
147 .set_enable = ldo_set_enable,
148};
149
150U_BOOT_DRIVER(as3722_stepdown) = {
151 .name = "as3722_stepdown",
152 .id = UCLASS_REGULATOR,
153 .ops = &as3722_stepdown_ops,
154 .probe = as3722_stepdown_probe,
155};
156
157U_BOOT_DRIVER(as3722_ldo) = {
158 .name = "as3722_ldo",
159 .id = UCLASS_REGULATOR,
160 .ops = &as3722_ldo_ops,
161 .probe = as3722_ldo_probe,
162};