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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hu0e58b512015-10-26 19:47:50 +08002/*
3 * LayerScape Internal Memory Map
4 *
Pankaj Bansal338baa32019-02-08 10:29:58 +00005 * Copyright 2017-2019 NXP
Mingkai Hu0e58b512015-10-26 19:47:50 +08006 * Copyright 2014 Freescale Semiconductor, Inc.
Mingkai Hu0e58b512015-10-26 19:47:50 +08007 */
8
9#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
10#define __ARCH_FSL_LSCH3_IMMAP_H_
11
12#define CONFIG_SYS_IMMR 0x01000000
13#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
15#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
16#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
Priyanka Jainef76b2e2018-10-29 09:17:09 +000018#ifdef CONFIG_ARCH_LX2160A
19#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
20#else
Mingkai Hu0e58b512015-10-26 19:47:50 +080021#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
Priyanka Jainef76b2e2018-10-29 09:17:09 +000022#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +080023#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
25#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
Yuan Yao52ae4fd2016-12-01 10:13:52 +080026#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
Mingkai Hu0e58b512015-10-26 19:47:50 +080027#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
Priyanka Jain88c25662018-10-29 09:11:29 +000028#ifndef CONFIG_NXP_LSCH3_2
Mingkai Hu0e58b512015-10-26 19:47:50 +080029#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
Priyanka Jain88c25662018-10-29 09:11:29 +000030#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +080031#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
32#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
Priyanka Jain3d31ec72016-11-17 12:29:52 +053033#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
34#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
Mingkai Hu0e58b512015-10-26 19:47:50 +080035#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
36 0x18A0)
Yunhui Cui3dfb82a2016-06-08 10:31:42 +080037#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
Priyanka Jain96b001f2016-11-17 12:29:51 +053038#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
Mingkai Hu0e58b512015-10-26 19:47:50 +080039
40#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
41#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
42#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
43#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
44
Mingkai Hu0e58b512015-10-26 19:47:50 +080045#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
46#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
47#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
48#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
49
50#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
51#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
52#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
53#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
Priyanka Jain88c25662018-10-29 09:11:29 +000054#ifdef CONFIG_NXP_LSCH3_2
55#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000)
56#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000)
57#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000)
58#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000)
59#endif
Priyanka Jaind1587182017-04-25 10:12:31 +053060#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
61#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
62#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
Mingkai Hu0e58b512015-10-26 19:47:50 +080063
Rajesh Bhagat386f2e42016-06-07 18:59:34 +053064#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
65#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
Mingkai Hu0e58b512015-10-26 19:47:50 +080066
67/* TZ Address Space Controller Definitions */
68#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
69#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
70#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
71#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
72#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
73#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
74#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
75#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
76#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
77#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
78#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
79#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
80#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
81
Tang Yuantian57894be2015-12-09 15:32:18 +080082/* SATA */
83#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
84#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
85
Saksham Jain62888be2016-03-23 16:24:32 +053086/* SFP */
87#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
88
Saksham Jain6ae7f582016-03-23 16:24:33 +053089/* SEC */
Alex Porosanu177fca82016-04-29 15:17:58 +030090#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
91#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
92#define CONFIG_SYS_FSL_SEC_ADDR \
93 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
94#define CONFIG_SYS_FSL_JR0_ADDR \
95 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
Saksham Jain6ae7f582016-03-23 16:24:33 +053096
Rajesh Bhagat583da8b2018-11-05 18:01:42 +000097#ifdef CONFIG_TFABOOT
Priyanka Jain88c25662018-10-29 09:11:29 +000098#ifdef CONFIG_NXP_LSCH3_2
Rajesh Bhagat583da8b2018-11-05 18:01:42 +000099/* RCW_SRC field in Power-On Reset Control Register 1 */
100#define RCW_SRC_MASK 0x07800000
101#define RCW_SRC_BIT 23
102
103/* CFG_RCW_SRC[3:0] */
104#define RCW_SRC_TYPE_MASK 0x8
105#define RCW_SRC_ADDR_OFFSET_8MB 0x800000
106
107/* RCW SRC HARDCODED */
108#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */
109
110#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */
111#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */
112#define RCW_SRC_I2C1_VAL 0xa /* 0xa */
113#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */
114#define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */
115#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */
116#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */
117#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */
118#else
119#define RCW_SRC_MASK (0xFF800000)
120#define RCW_SRC_BIT 23
121/* CFG_RCW_SRC[6:0] */
122#define RCW_SRC_TYPE_MASK (0x70)
123
124/* RCW SRC HARDCODED */
125#define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */
126/* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */
127
128/* RCW SRC NOR */
129#define RCW_SRC_NOR_VAL (0x20)
130#define NOR_TYPE_MASK (0x10)
131#define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */
132#define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */
133
134/* RCW SRC Serial Flash
135 * 1. SERIAL NOR (QSPI)
136 * 2. OTHERS (SD/MMC, SPI, I2C1
137 */
138#define RCW_SRC_SERIAL_MASK (0x7F)
139#define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */
140#define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */
141#define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */
142#define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */
143#endif
144#endif
145
Saksham Jain6ae7f582016-03-23 16:24:33 +0530146/* Security Monitor */
147#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
148
Saksham Jain5d8ffe12016-03-23 16:24:40 +0530149/* MMU 500 */
150#define SMMU_SCR0 (SMMU_BASE + 0x0)
151#define SMMU_SCR1 (SMMU_BASE + 0x4)
152#define SMMU_SCR2 (SMMU_BASE + 0x8)
153#define SMMU_SACR (SMMU_BASE + 0x10)
154#define SMMU_IDR0 (SMMU_BASE + 0x20)
155#define SMMU_IDR1 (SMMU_BASE + 0x24)
156
157#define SMMU_NSCR0 (SMMU_BASE + 0x400)
158#define SMMU_NSCR2 (SMMU_BASE + 0x408)
159#define SMMU_NSACR (SMMU_BASE + 0x410)
160
161#define SCR0_CLIENTPD_MASK 0x00000001
162#define SCR0_USFCFG_MASK 0x00000400
163
Saksham Jain6ae7f582016-03-23 16:24:33 +0530164
Mingkai Hu0e58b512015-10-26 19:47:50 +0800165/* PCIe */
166#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
167#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
168#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
169#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
Hou Zhiqiangd08f9702019-04-08 10:15:41 +0000170#ifdef CONFIG_ARCH_LX2160A
171#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
172#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
173#endif
174
175#ifdef CONFIG_ARCH_LX2160A
176#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
177#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
178#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
179#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL
180#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL
181#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL
182#elif CONFIG_ARCH_LS1088A
Hou Zhiqiang19143122017-09-04 10:47:52 +0800183#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
184#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
185#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
Yuantian Tang4aefa162019-04-10 16:43:33 +0800186#elif CONFIG_ARCH_LS1028A
187#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
188#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
Hou Zhiqiang19143122017-09-04 10:47:52 +0800189#else
Mingkai Hu0e58b512015-10-26 19:47:50 +0800190#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
191#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
192#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
193#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
Hou Zhiqiang19143122017-09-04 10:47:52 +0800194#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +0800195
196/* Device Configuration */
197#define DCFG_BASE 0x01e00000
198#define DCFG_PORSR1 0x000
199#define DCFG_PORSR1_RCW_SRC 0xff800000
200#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
201#define DCFG_RCWSR13 0x130
202#define DCFG_RCWSR13_DSPI (0 << 8)
Yuan Yao86f42d72016-06-08 18:24:57 +0800203#define DCFG_RCWSR15 0x138
204#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
Mingkai Hu0e58b512015-10-26 19:47:50 +0800205
206#define DCFG_DCSR_BASE 0X700100000ULL
207#define DCFG_DCSR_PORCR1 0x000
208
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800209/* Interrupt Sampling Control */
210#define ISC_BASE 0x01F70000
211#define IRQCR_OFFSET 0x14
212
Mingkai Hu0e58b512015-10-26 19:47:50 +0800213/* Supplemental Configuration */
214#define SCFG_BASE 0x01fc0000
215#define SCFG_USB3PRM1CR 0x000
Sriram Dash01820952016-06-13 09:58:36 +0530216#define SCFG_USB3PRM1CR_INIT 0x27672b2a
Ran Wangb358b7b2017-09-04 18:46:48 +0800217#define SCFG_USB_TXVREFTUNE 0x9
Ran Wang9e8fabc2017-09-04 18:46:49 +0800218#define SCFG_USB_SQRXTUNE_MASK 0x7
Yuan Yao2ec85842016-06-08 18:24:52 +0800219#define SCFG_QSPICLKCTLR 0x10
Mingkai Hu0e58b512015-10-26 19:47:50 +0800220
Ran Wang3ba69482017-09-04 18:46:51 +0800221#define DCSR_BASE 0x700000000ULL
222#define DCSR_USB_PHY1 0x4600000
223#define DCSR_USB_PHY2 0x4610000
224#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
225#define USB_PHY_RX_EQ_VAL_1 0x0000
226#define USB_PHY_RX_EQ_VAL_2 0x0080
227#define USB_PHY_RX_EQ_VAL_3 0x0380
228#define USB_PHY_RX_EQ_VAL_4 0x0b80
229
Mingkai Hu0e58b512015-10-26 19:47:50 +0800230#define TP_ITYP_AV 0x00000001 /* Initiator available */
231#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
232#define TP_ITYP_TYPE_ARM 0x0
233#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
234#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
235#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
236#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
237#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
238#define TY_ITYP_VER_A7 0x1
239#define TY_ITYP_VER_A53 0x2
240#define TY_ITYP_VER_A57 0x3
Alison Wang79808392016-07-05 16:01:52 +0800241#define TY_ITYP_VER_A72 0x4
Mingkai Hu0e58b512015-10-26 19:47:50 +0800242
243#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
244#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
245#define TP_INIT_PER_CLUSTER 4
246/* This is chassis generation 3 */
Priyanka Jain96b001f2016-11-17 12:29:51 +0530247#ifndef __ASSEMBLY__
Mingkai Hu0e58b512015-10-26 19:47:50 +0800248struct sys_info {
249 unsigned long freq_processor[CONFIG_MAX_CPUS];
Hou Zhiqiang3a76dd52017-01-10 16:44:16 +0800250 /* frequency of platform PLL */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800251 unsigned long freq_systembus;
252 unsigned long freq_ddrbus;
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530253#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
Mingkai Hu0e58b512015-10-26 19:47:50 +0800254 unsigned long freq_ddrbus2;
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530255#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +0800256 unsigned long freq_localbus;
257 unsigned long freq_qe;
258#ifdef CONFIG_SYS_DPAA_FMAN
259 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
260#endif
261#ifdef CONFIG_SYS_DPAA_QBMAN
262 unsigned long freq_qman;
263#endif
264#ifdef CONFIG_SYS_DPAA_PME
265 unsigned long freq_pme;
266#endif
267};
268
269/* Global Utilities Block */
270struct ccsr_gur {
271 u32 porsr1; /* POR status 1 */
272 u32 porsr2; /* POR status 2 */
273 u8 res_008[0x20-0x8];
274 u32 gpporcr1; /* General-purpose POR configuration */
275 u32 gpporcr2; /* General-purpose POR configuration 2 */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530276 u32 gpporcr3;
277 u32 gpporcr4;
278 u8 res_030[0x60-0x30];
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530279#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530280#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
Rajesh Bhagat170eecf2018-01-17 16:13:05 +0530281#if defined(CONFIG_ARCH_LS1088A)
282#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
283#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
284#else
285#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
286#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
287#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +0800288 u32 dcfg_fusesr; /* Fuse status register */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530289 u8 res_064[0x70-0x64];
290 u32 devdisr; /* Device disable control 1 */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800291 u32 devdisr2; /* Device disable control 2 */
292 u32 devdisr3; /* Device disable control 3 */
293 u32 devdisr4; /* Device disable control 4 */
294 u32 devdisr5; /* Device disable control 5 */
295 u32 devdisr6; /* Device disable control 6 */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530296 u8 res_088[0x94-0x88];
297 u32 coredisr; /* Device disable control 7 */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800298#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
299#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
300#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
301#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
302#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
303#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
304#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
305#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
306#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
307#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
308#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
309#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
310#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
311#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
312#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
313#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
314#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
315#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
316#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
317#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
318#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
319#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
320#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
321#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
Mingkai Hu0e58b512015-10-26 19:47:50 +0800322 u8 res_098[0xa0-0x98];
323 u32 pvr; /* Processor version */
324 u32 svr; /* System version */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530325 u8 res_0a8[0x100-0xa8];
326 u32 rcwsr[30]; /* Reset control word status */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800327
328#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
329#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
330#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
331#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
332#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
333#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
Prabhakar Kushwaha57f7f2ed2017-02-15 20:40:35 +0530334
335#if defined(CONFIG_ARCH_LS2080A)
Mingkai Hu0e58b512015-10-26 19:47:50 +0800336#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
337#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
338#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
339#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
Prabhakar Kushwaha57f7f2ed2017-02-15 20:40:35 +0530340#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
341#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
342#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
343#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000344#define FSL_CHASSIS3_SRDS1_REGSR 29
345#define FSL_CHASSIS3_SRDS2_REGSR 29
346#elif defined(CONFIG_ARCH_LX2160A)
347#define FSL_CHASSIS3_EC1_REGSR 27
348#define FSL_CHASSIS3_EC2_REGSR 27
349#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003
350#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0
351#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007
352#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2
353#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000
354#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
355#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000
356#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21
357#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000
358#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26
359#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
360#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
361#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
362#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
363#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK
364#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT
Prabhakar Kushwaha57f7f2ed2017-02-15 20:40:35 +0530365#define FSL_CHASSIS3_SRDS1_REGSR 29
366#define FSL_CHASSIS3_SRDS2_REGSR 29
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000367#define FSL_CHASSIS3_SRDS3_REGSR 29
Pankaj Bansal338baa32019-02-08 10:29:58 +0000368#define FSL_CHASSIS3_RCWSR12_REGSR 12
369#define FSL_CHASSIS3_RCWSR13_REGSR 13
370#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
371#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
372#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
373#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
374#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
375#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
Ashish Kumarb25faa22017-08-31 16:12:53 +0530376#elif defined(CONFIG_ARCH_LS1088A)
Ashish Kumarec455e22017-08-31 16:37:31 +0530377#define FSL_CHASSIS3_EC1_REGSR 26
378#define FSL_CHASSIS3_EC2_REGSR 26
379#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
380#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
381#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
382#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
Ashish Kumarb25faa22017-08-31 16:12:53 +0530383#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
384#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
385#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
386#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
387#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
388#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
389#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
390#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
391#define FSL_CHASSIS3_SRDS1_REGSR 29
392#define FSL_CHASSIS3_SRDS2_REGSR 30
Yuantian Tang4aefa162019-04-10 16:43:33 +0800393#elif defined(CONFIG_ARCH_LS1028A)
394#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
395#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
396#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
397#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
398#define FSL_CHASSIS3_SRDS1_REGSR 29
Prabhakar Kushwaha57f7f2ed2017-02-15 20:40:35 +0530399#endif
Saksham Jain6ae7f582016-03-23 16:24:33 +0530400#define RCW_SB_EN_REG_INDEX 9
401#define RCW_SB_EN_MASK 0x00000400
Mingkai Hu0e58b512015-10-26 19:47:50 +0800402
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530403 u8 res_178[0x200-0x178];
404 u32 scratchrw[16]; /* Scratch Read/Write */
405 u8 res_240[0x300-0x240];
Mingkai Hu0e58b512015-10-26 19:47:50 +0800406 u32 scratchw1r[4]; /* Scratch Read (Write once) */
407 u8 res_310[0x400-0x310];
408 u32 bootlocptrl; /* Boot location pointer low-order addr */
409 u32 bootlocptrh; /* Boot location pointer high-order addr */
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530410 u8 res_408[0x520-0x408];
411 u32 usb1_amqr;
412 u32 usb2_amqr;
413 u8 res_528[0x530-0x528]; /* add more registers when needed */
414 u32 sdmm1_amqr;
415 u8 res_534[0x550-0x534]; /* add more registers when needed */
416 u32 sata1_amqr;
417 u32 sata2_amqr;
418 u8 res_558[0x570-0x558]; /* add more registers when needed */
419 u32 misc1_amqr;
420 u8 res_574[0x590-0x574]; /* add more registers when needed */
421 u32 spare1_amqr;
422 u32 spare2_amqr;
423 u8 res_598[0x620-0x598]; /* add more registers when needed */
424 u32 gencr[7]; /* General Control Registers */
425 u8 res_63c[0x640-0x63c]; /* add more registers when needed */
426 u32 cgensr1; /* Core General Status Register */
427 u8 res_644[0x660-0x644]; /* add more registers when needed */
428 u32 cgencr1; /* Core General Control Register */
429 u8 res_664[0x740-0x664]; /* add more registers when needed */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800430 u32 tp_ityp[64]; /* Topology Initiator Type Register */
431 struct {
432 u32 upper;
433 u32 lower;
Priyanka Jain1b4b7602017-01-19 11:12:26 +0530434 } tp_cluster[4]; /* Core cluster n Topology Register */
435 u8 res_864[0x920-0x864]; /* add more registers when needed */
436 u32 ioqoscr[8]; /*I/O Quality of Services Register */
437 u32 uccr;
438 u8 res_944[0x960-0x944]; /* add more registers when needed */
439 u32 ftmcr;
440 u8 res_964[0x990-0x964]; /* add more registers when needed */
441 u32 coredisablesr;
442 u8 res_994[0xa00-0x994]; /* add more registers when needed */
443 u32 sdbgcr; /*Secure Debug Confifuration Register */
444 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
445 u32 ipbrr1;
446 u32 ipbrr2;
447 u8 res_858[0x1000-0xc00];
Mingkai Hu0e58b512015-10-26 19:47:50 +0800448};
449
Mingkai Hu0e58b512015-10-26 19:47:50 +0800450struct ccsr_clk_cluster_group {
451 struct {
452 u8 res_00[0x10];
453 u32 csr;
454 u8 res_14[0x20-0x14];
455 } hwncsr[3];
456 u8 res_60[0x80-0x60];
457 struct {
458 u32 gsr;
459 u8 res_84[0xa0-0x84];
460 } pllngsr[3];
461 u8 res_e0[0x100-0xe0];
462};
463
464struct ccsr_clk_ctrl {
465 struct {
466 u32 csr; /* core cluster n clock control status */
467 u8 res_04[0x20-0x04];
468 } clkcncsr[8];
469};
470
471struct ccsr_reset {
472 u32 rstcr; /* 0x000 */
473 u32 rstcrsp; /* 0x004 */
474 u8 res_008[0x10-0x08]; /* 0x008 */
475 u32 rstrqmr1; /* 0x010 */
476 u32 rstrqmr2; /* 0x014 */
477 u32 rstrqsr1; /* 0x018 */
478 u32 rstrqsr2; /* 0x01c */
479 u32 rstrqwdtmrl; /* 0x020 */
480 u32 rstrqwdtmru; /* 0x024 */
481 u8 res_028[0x30-0x28]; /* 0x028 */
482 u32 rstrqwdtsrl; /* 0x030 */
483 u32 rstrqwdtsru; /* 0x034 */
484 u8 res_038[0x60-0x38]; /* 0x038 */
485 u32 brrl; /* 0x060 */
486 u32 brru; /* 0x064 */
487 u8 res_068[0x80-0x68]; /* 0x068 */
488 u32 pirset; /* 0x080 */
489 u32 pirclr; /* 0x084 */
490 u8 res_088[0x90-0x88]; /* 0x088 */
491 u32 brcorenbr; /* 0x090 */
492 u8 res_094[0x100-0x94]; /* 0x094 */
493 u32 rcw_reqr; /* 0x100 */
494 u32 rcw_completion; /* 0x104 */
495 u8 res_108[0x110-0x108]; /* 0x108 */
496 u32 pbi_reqr; /* 0x110 */
497 u32 pbi_completion; /* 0x114 */
498 u8 res_118[0xa00-0x118]; /* 0x118 */
499 u32 qmbm_warmrst; /* 0xa00 */
500 u32 soc_warmrst; /* 0xa04 */
501 u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
502 u32 ip_rev1; /* 0xbf8 */
503 u32 ip_rev2; /* 0xbfc */
504};
Sriram Dash9282d262016-06-13 09:58:32 +0530505
Rajesh Bhagat814e0772018-01-17 16:13:00 +0530506struct ccsr_serdes {
507 struct {
508 u32 rstctl; /* Reset Control Register */
509 u32 pllcr0; /* PLL Control Register 0 */
510 u32 pllcr1; /* PLL Control Register 1 */
511 u32 pllcr2; /* PLL Control Register 2 */
512 u32 pllcr3; /* PLL Control Register 3 */
513 u32 pllcr4; /* PLL Control Register 4 */
514 u32 pllcr5; /* PLL Control Register 5 */
515 u8 res[0x20 - 0x1c];
516 } bank[2];
517 u8 res1[0x90 - 0x40];
518 u32 srdstcalcr; /* TX Calibration Control */
519 u32 srdstcalcr1; /* TX Calibration Control1 */
520 u8 res2[0xa0 - 0x98];
521 u32 srdsrcalcr; /* RX Calibration Control */
522 u32 srdsrcalcr1; /* RX Calibration Control1 */
523 u8 res3[0xb0 - 0xa8];
524 u32 srdsgr0; /* General Register 0 */
525 u8 res4[0x800 - 0xb4];
526 struct serdes_lane {
527 u32 gcr0; /* General Control Register 0 */
528 u32 gcr1; /* General Control Register 1 */
529 u32 gcr2; /* General Control Register 2 */
530 u32 ssc0; /* Speed Switch Control 0 */
531 u32 rec0; /* Receive Equalization Control 0 */
532 u32 rec1; /* Receive Equalization Control 1 */
533 u32 tec0; /* Transmit Equalization Control 0 */
534 u32 ssc1; /* Speed Switch Control 1 */
535 u8 res1[0x840 - 0x820];
536 } lane[8];
537 u8 res5[0x19fc - 0xa00];
538};
539
Priyanka Jain96b001f2016-11-17 12:29:51 +0530540#endif /*__ASSEMBLY__*/
Mingkai Hu0e58b512015-10-26 19:47:50 +0800541#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */