blob: 3216a20027a85ae8619224897c46addf5fa65add [file] [log] [blame]
Wasim Khan54e44ef2020-01-06 12:05:57 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019-2020 NXP
4 *
5 * PCIe DT fixup for NXP Layerscape SoCs
6 * Author: Wasim Khan <wasim.khan@nxp.com>
7 *
8 */
9
10#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Wasim Khan54e44ef2020-01-06 12:05:57 +000012#include <asm/arch/clock.h>
13#include <asm/arch/soc.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <linux/libfdt.h>
Vladimir Oltean06a68052021-09-17 15:11:29 +030015#include <fdt_support.h>
Wasim Khan54e44ef2020-01-06 12:05:57 +000016#include "pcie_layerscape_fixup_common.h"
17
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090018void ft_pci_setup(void *blob, struct bd_info *bd)
Wasim Khan54e44ef2020-01-06 12:05:57 +000019{
20#if defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
21 uint svr;
22
23 svr = SVR_SOC_VER(get_svr());
24
25 if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 1, 0))
26 ft_pci_setup_ls_gen4(blob, bd);
27 else
28#endif /* CONFIG_PCIE_LAYERSCAPE_GEN4 */
29 ft_pci_setup_ls(blob, bd);
30}
Wasim Khan9d3d2302020-01-06 12:05:59 +000031
32#if defined(CONFIG_FSL_LAYERSCAPE)
Vladimir Oltean4d5d5d32021-09-17 15:11:30 +030033static int lx2_board_fix_fdt(void *fdt)
Wasim Khan70bec5c2020-01-06 12:06:00 +000034{
35 char *reg_name, *old_str, *new_str;
36 const char *reg_names;
37 int names_len, old_str_len, new_str_len, remaining_str_len;
38 struct str_map {
39 char *old_str;
40 char *new_str;
41 } reg_names_map[] = {
42 { "csr_axi_slave", "regs" },
43 { "config_axi_slave", "config" }
44 };
45 int off = -1, i;
Hou Zhiqiangfdb1dff2020-09-13 23:12:50 +080046 const fdt32_t *prop;
47 u32 ob_wins, ib_wins;
Wasim Khan70bec5c2020-01-06 12:06:00 +000048
49 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
50 while (off != -FDT_ERR_NOTFOUND) {
51 fdt_setprop(fdt, off, "compatible", "fsl,ls2088a-pcie",
52 strlen("fsl,ls2088a-pcie") + 1);
53
54 reg_names = fdt_getprop(fdt, off, "reg-names", &names_len);
55 if (!reg_names)
56 continue;
57 reg_name = (char *)reg_names;
58 remaining_str_len = names_len - (reg_name - reg_names);
59 i = 0;
60 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_str_len) {
61 old_str = reg_names_map[i].old_str;
62 new_str = reg_names_map[i].new_str;
63 old_str_len = strlen(old_str);
64 new_str_len = strlen(new_str);
65 if (memcmp(reg_name, old_str, old_str_len) == 0) {
66 /* first only leave required bytes for new_str
67 * and copy rest of the string after it
68 */
69 memcpy(reg_name + new_str_len,
70 reg_name + old_str_len,
71 remaining_str_len - old_str_len);
72
73 /* Now copy new_str */
74 memcpy(reg_name, new_str, new_str_len);
75 names_len -= old_str_len;
76 names_len += new_str_len;
77 i++;
78 }
79
80 reg_name = memchr(reg_name, '\0', remaining_str_len);
81 if (!reg_name)
82 break;
83 reg_name += 1;
84
85 remaining_str_len = names_len - (reg_name - reg_names);
86 }
87 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
88 fdt_delprop(fdt, off, "apio-wins");
89 fdt_delprop(fdt, off, "ppio-wins");
90 off = fdt_node_offset_by_compatible(fdt, off,
91 "fsl,lx2160a-pcie");
92 }
Hou Zhiqiangfdb1dff2020-09-13 23:12:50 +080093
94 /* Fixup PCIe EP nodes */
95 off = -1;
96 off = fdt_node_offset_by_compatible(fdt, off, "fsl,lx2160a-pcie-ep");
97 while (off != -FDT_ERR_NOTFOUND) {
98 fdt_setprop_string(fdt, off, "compatible",
99 "fsl,lx2160ar2-pcie-ep");
100 prop = fdt_getprop(fdt, off, "apio-wins", NULL);
101 if (!prop) {
102 printf("%s: Failed to fixup PCIe EP node @0x%x\n",
103 __func__, off);
Hou Zhiqiange1a84432020-10-26 11:57:42 +0800104 off = fdt_node_offset_by_compatible(fdt, off,
105 "fsl,lx2160a-pcie-ep");
Hou Zhiqiangfdb1dff2020-09-13 23:12:50 +0800106 continue;
107 }
108
109 ob_wins = fdt32_to_cpu(*prop);
110 ib_wins = (ob_wins == 256) ? 24 : 8;
111 fdt_setprop_u32(fdt, off, "num-ib-windows", ib_wins);
112 fdt_setprop_u32(fdt, off, "num-ob-windows", ob_wins);
113 fdt_delprop(fdt, off, "apio-wins");
114
115 off = fdt_node_offset_by_compatible(fdt, off,
116 "fsl,lx2160a-pcie-ep");
117 }
118
Wasim Khan70bec5c2020-01-06 12:06:00 +0000119 return 0;
120}
121
122int pcie_board_fix_fdt(void *fdt)
123{
124 uint svr;
125
126 svr = SVR_SOC_VER(get_svr());
127
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530128 if ((svr == SVR_LX2160A || svr == SVR_LX2162A ||
129 svr == SVR_LX2120A || svr == SVR_LX2080A ||
130 svr == SVR_LX2122A || svr == SVR_LX2082A) &&
131 IS_SVR_REV(get_svr(), 2, 0))
Wasim Khan70bec5c2020-01-06 12:06:00 +0000132 return lx2_board_fix_fdt(fdt);
133
134 return 0;
135}
136
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530137#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
Wasim Khan9d3d2302020-01-06 12:05:59 +0000138/* returns the next available streamid for pcie, -errno if failed */
139int pcie_next_streamid(int currentid, int idx)
140{
141 if (currentid > FSL_PEX_STREAM_ID_END)
142 return -EINVAL;
143
144 return currentid | ((idx + 1) << 11);
145}
146#else
147/* returns the next available streamid for pcie, -errno if failed */
148int pcie_next_streamid(int currentid, int idx)
149{
150 static int next_stream_id = FSL_PEX_STREAM_ID_START;
151
152 if (next_stream_id > FSL_PEX_STREAM_ID_END)
153 return -EINVAL;
154
155 return next_stream_id++;
156}
157#endif
158#endif /* CONFIG_FSL_LAYERSCAPE */