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git01.mediatek.com / filogic / uboot / 826819fc2b32b7dbe99753dd9393f3ff284b020d / . / arch / arm / mach-davinci / Kconfig
blob: 6eca8db6d5ff5c65a61c64f8b56b9dde290ad6e9 [file] [log] [blame]
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]1if ARCH_DAVINCI
2
3choice
4 prompt "DaVinci board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]5 optional
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]6
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]7config TARGET_DA850EVM
8 bool "DA850 EVM board"
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]9 select MACH_DAVINCI_DA850_EVM
10 select SOC_DA850
Masahiro Yamada6e0971b2014-10-20 17:45:56 +0900[diff] [blame]11 select SUPPORT_SPL
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]12
Simon Glassa6664e92015-08-30 19:18:59 -0600[diff] [blame]13config TARGET_OMAPL138_LCDK
14 bool "OMAPL138 LCDK"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]15 select SOC_DA8XX
Simon Glassa6664e92015-08-30 19:18:59 -0600[diff] [blame]16 select SUPPORT_SPL
Bartosz Golaszewskif1412ef2019-11-14 16:10:30 +0100[diff] [blame]17 select SPL_BOARD_INIT
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]18
David Lechnera67f16f2016-02-26 00:46:07 -0600[diff] [blame]19config TARGET_LEGOEV3
20 bool "LEGO MINDSTORMS EV3"
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]21 select MACH_DAVINCI_DA850_EVM
22 select SOC_DA850
David Lechnera67f16f2016-02-26 00:46:07 -0600[diff] [blame]23
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]24endchoice
25
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]26config SYS_SOC
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]27 default "davinci"
28
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]29config DA850_LOWLEVEL
30 bool "Enable Lowlevel DA850 initialization"
31 depends on SOC_DA850
32
Fabien Parentb1bd48b2016-11-29 14:23:36 +0100[diff] [blame]33config SYS_DA850_PLL_INIT
34 bool
35
Fabien Parent06372b62016-11-29 14:23:37 +0100[diff] [blame]36config SYS_DA850_DDR_INIT
37 bool
38
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]39config SOC_DA850
40 bool
41 select SOC_DA8XX
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]42
43config SOC_DA8XX
44 bool
Lokesh Vutlabcb8d282018-03-16 14:22:12 +0530[diff] [blame]45 select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]46 select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]47
48config MACH_DAVINCI_DA850_EVM
49 bool
50
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]51if SYS_DA850_PLL_INIT
52comment "DA850 PLL Initialization Parameters"
53
54config SYS_DV_CLKMODE
55 int "PLLCTL Clock Mode"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]56 default 0
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]57 help
58 Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
59
60config SYS_DA850_PLL0_POSTDIV
61 int "PLLC0 PLL Post-Divider"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]62 default 1
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]63 help
64 Value written to PLLC0 PLL Post-Divider Control Register
65
66config SYS_DA850_PLL0_PLLDIV1
67 hex "PLLC0 Divider 1"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]68 default 0x8000
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]69 help
70 Value written to PLLC0 Divider 1 register
71
72config SYS_DA850_PLL0_PLLDIV2
73 hex "PLLC0 Divider 2"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]74 default 0x8001
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]75 help
76 Value written to PLLC0 Divider 2 register
77
78config SYS_DA850_PLL0_PLLDIV3
79 hex "PLLC0 Divider 3"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]80 default 0x8002
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]81 help
82 Value written to PLLC0 Divider 3 register
83
84config SYS_DA850_PLL0_PLLDIV4
85 hex "PLLC0 Divider 4"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]86 default 0x8003
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]87 help
88 Value written to PLLC0 Divider 4 register
89
90config SYS_DA850_PLL0_PLLDIV5
91 hex "PLLC0 Divider 5"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]92 default 0x8002
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]93 help
94 Value written to PLLC0 Divider 5 register
95
96config SYS_DA850_PLL0_PLLDIV6
97 hex "PLLC0 Divider 6"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]98 default 0x8000
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]99 help
100 Value written to PLLC0 Divider 6 register
101
102config SYS_DA850_PLL0_PLLDIV7
103 hex "PLLC0 Divider 7"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]104 default 0x8005
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]105 help
106 Value written to PLLC0 Divider 7 register
107
108config SYS_DA850_PLL1_POSTDIV
109 hex "PLLC1 PLL Post-Divider"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]110 default 1
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]111 help
112 Value written to PLLC1 PLL Post-Divider Control Register
113
114config SYS_DA850_PLL1_PLLDIV1
115 hex "PLLC1 Divider 2"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]116 default 0x8000
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]117 help
118 Value written to PLLC1 Divider 1 register
119
120config SYS_DA850_PLL1_PLLDIV2
121 hex "PLLC1 Divider 2"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]122 default 0x8001
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]123 help
124 Value written to PLLC1 Divider 2 register
125
126config SYS_DA850_PLL1_PLLDIV3
127 hex "PLLC1 Divider 3"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]128 default 0x8002
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]129 help
130 Value written to PLLC1 Divider 3 register
131
132endif
133
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]134source "board/davinci/da8xxevm/Kconfig"
David Lechnera67f16f2016-02-26 00:46:07 -0600[diff] [blame]135source "board/lego/ev3/Kconfig"
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]136
Philipp Tomsich2d6a0cc2017-08-03 23:23:55 +0200[diff] [blame]137config SPL_LDSCRIPT
Tom Rini826819f2020-03-11 18:11:14 -0400[diff] [blame^]138 default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds"
Philipp Tomsich2d6a0cc2017-08-03 23:23:55 +0200[diff] [blame]139
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]140endif