blob: 8a2f4048ecb469ca8ad389f5890d50135f4bc2ba [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mingkai Hu0e58b512015-10-26 19:47:50 +08002/*
Pankaj Bansal6c772772019-10-31 05:41:09 +00003 * Copyright 2017-2019 NXP
Mingkai Hu0e58b512015-10-26 19:47:50 +08004 * Copyright 2014-2015 Freescale Semiconductor, Inc.
Mingkai Hu0e58b512015-10-26 19:47:50 +08005 */
6
7#include <common.h>
Simon Glass33d1e702019-11-14 12:57:32 -07008#include <cpu_func.h>
Simon Glassdb229612019-08-01 09:46:42 -06009#include <env.h>
Simon Glass0e0ac202017-04-06 12:47:04 -060010#include <fsl_ddr_sdram.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070011#include <init.h>
Simon Glassf11478f2019-12-28 10:45:07 -070012#include <hang.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -060014#include <net.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070015#include <vsprintf.h>
Simon Glass274e0b02020-05-10 11:39:56 -060016#include <asm/cache.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080017#include <asm/io.h>
Simon Glass6b9f0102020-05-10 11:40:06 -060018#include <asm/ptrace.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090019#include <linux/errno.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080020#include <asm/system.h>
Joe Hershberger8f454d92018-07-16 15:33:51 -050021#include <fm_eth.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080022#include <asm/armv8/mmu.h>
23#include <asm/io.h>
24#include <asm/arch/fsl_serdes.h>
25#include <asm/arch/soc.h>
26#include <asm/arch/cpu.h>
27#include <asm/arch/speed.h>
Ashish Kumar11234062017-08-11 11:09:14 +053028#include <fsl_immap.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080029#include <asm/arch/mp.h>
Alexander Graf12be31c2016-11-17 01:03:01 +010030#include <efi_loader.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080031#include <fsl-mc/fsl_mc.h>
32#ifdef CONFIG_FSL_ESDHC
33#include <fsl_esdhc.h>
34#endif
Hou Zhiqiang21c4d552016-06-28 20:18:15 +080035#include <asm/armv8/sec_firmware.h>
Shengzhou Liu15875a52016-11-21 11:36:48 +080036#ifdef CONFIG_SYS_FSL_DDR
37#include <fsl_ddr.h>
38#endif
Simon Glass243182c2017-05-17 08:23:06 -060039#include <asm/arch/clock.h>
Prabhakar Kushwaha0acce842017-11-10 11:32:52 +053040#include <hwconfig.h>
Ahmed Mansouraa270b42017-12-15 16:01:00 -050041#include <fsl_qbman.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080042
Rajesh Bhagat583da8b2018-11-05 18:01:42 +000043#ifdef CONFIG_TFABOOT
Simon Glass9d1f6192019-08-02 09:44:25 -060044#include <env_internal.h>
Pankit Gargbdbf84f2018-11-05 18:01:52 +000045#ifdef CONFIG_CHAIN_OF_TRUST
46#include <fsl_validate.h>
47#endif
Rajesh Bhagat583da8b2018-11-05 18:01:42 +000048#endif
Simon Glasscaefa322019-11-14 12:57:31 -070049#include <linux/mii.h>
Rajesh Bhagat583da8b2018-11-05 18:01:42 +000050
Mingkai Hu0e58b512015-10-26 19:47:50 +080051DECLARE_GLOBAL_DATA_PTR;
52
York Sunef4cef92018-11-05 18:01:06 +000053static struct cpu_type cpu_type_list[] = {
54 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
55 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
56 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
57 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
58 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
59 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
60 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
61 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
62 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
63 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
Hou Zhiqiangb9aedf92018-12-20 06:31:17 +000064 CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
York Sunef4cef92018-11-05 18:01:06 +000065 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
Hou Zhiqiangb9aedf92018-12-20 06:31:17 +000066 CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
York Sunef4cef92018-11-05 18:01:06 +000067 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
68 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
69 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
70 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
Yuantian Tangf463d752019-09-18 16:50:52 +080071 CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
72 CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
73 CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
Yuantian Tang4aefa162019-04-10 16:43:33 +080074 CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
York Sunef4cef92018-11-05 18:01:06 +000075 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
76 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
77 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
78 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
Priyanka Jainef76b2e2018-10-29 09:17:09 +000079 CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
80 CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
81 CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
York Sunef4cef92018-11-05 18:01:06 +000082};
83
84#define EARLY_PGTABLE_SIZE 0x5000
85static struct mm_region early_map[] = {
86#ifdef CONFIG_FSL_LSCH3
87 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
88 CONFIG_SYS_FSL_CCSR_SIZE,
89 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
90 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
91 },
92 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
93 SYS_FSL_OCRAM_SPACE_SIZE,
94 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
95 },
96 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
97 CONFIG_SYS_FSL_QSPI_SIZE1,
98 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
99#ifdef CONFIG_FSL_IFC
100 /* For IFC Region #1, only the first 4MB is cache-enabled */
101 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
102 CONFIG_SYS_FSL_IFC_SIZE1_1,
103 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
104 },
105 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
106 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
107 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
108 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
109 },
110 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
111 CONFIG_SYS_FSL_IFC_SIZE1,
112 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
113 },
114#endif
115 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
116 CONFIG_SYS_FSL_DRAM_SIZE1,
Rajesh Bhagat5efbecf2018-11-05 18:01:37 +0000117#if defined(CONFIG_TFABOOT) || \
118 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
York Sunef4cef92018-11-05 18:01:06 +0000119 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
120#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
121 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
122#endif
123 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
124 },
125#ifdef CONFIG_FSL_IFC
126 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
127 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
128 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
129 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
130 },
131#endif
132 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
133 CONFIG_SYS_FSL_DCSR_SIZE,
134 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
135 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
136 },
137 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
138 CONFIG_SYS_FSL_DRAM_SIZE2,
139 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
140 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
141 },
Priyanka Jain88c25662018-10-29 09:11:29 +0000142#ifdef CONFIG_SYS_FSL_DRAM_BASE3
143 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
144 CONFIG_SYS_FSL_DRAM_SIZE3,
145 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
146 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
147 },
148#endif
York Sunef4cef92018-11-05 18:01:06 +0000149#elif defined(CONFIG_FSL_LSCH2)
150 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
151 CONFIG_SYS_FSL_CCSR_SIZE,
152 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
153 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
154 },
155 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
156 SYS_FSL_OCRAM_SPACE_SIZE,
157 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
158 },
159 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
160 CONFIG_SYS_FSL_DCSR_SIZE,
161 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
162 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
163 },
164 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
165 CONFIG_SYS_FSL_QSPI_SIZE,
166 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
167 },
168#ifdef CONFIG_FSL_IFC
169 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
170 CONFIG_SYS_FSL_IFC_SIZE,
171 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
172 },
173#endif
174 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
175 CONFIG_SYS_FSL_DRAM_SIZE1,
Rajesh Bhagat5efbecf2018-11-05 18:01:37 +0000176#if defined(CONFIG_TFABOOT) || \
177 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
York Sunef4cef92018-11-05 18:01:06 +0000178 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
179#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
180 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
181#endif
182 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
183 },
184 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
185 CONFIG_SYS_FSL_DRAM_SIZE2,
186 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
187 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
188 },
189#endif
190 {}, /* list terminator */
191};
192
193static struct mm_region final_map[] = {
194#ifdef CONFIG_FSL_LSCH3
195 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
196 CONFIG_SYS_FSL_CCSR_SIZE,
197 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
198 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
199 },
200 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
201 SYS_FSL_OCRAM_SPACE_SIZE,
202 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
203 },
204 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
205 CONFIG_SYS_FSL_DRAM_SIZE1,
206 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
207 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
208 },
209 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
210 CONFIG_SYS_FSL_QSPI_SIZE1,
211 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
212 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
213 },
214 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
215 CONFIG_SYS_FSL_QSPI_SIZE2,
216 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
217 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
218 },
219#ifdef CONFIG_FSL_IFC
220 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
221 CONFIG_SYS_FSL_IFC_SIZE2,
222 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
223 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
224 },
225#endif
226 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
227 CONFIG_SYS_FSL_DCSR_SIZE,
228 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
229 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
230 },
231 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
232 CONFIG_SYS_FSL_MC_SIZE,
233 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
234 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
235 },
236 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
237 CONFIG_SYS_FSL_NI_SIZE,
238 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
239 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
240 },
241 /* For QBMAN portal, only the first 64MB is cache-enabled */
242 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
243 CONFIG_SYS_FSL_QBMAN_SIZE_1,
244 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
245 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
246 },
247 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
248 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
249 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
250 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
251 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
252 },
253 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
254 CONFIG_SYS_PCIE1_PHYS_SIZE,
255 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
256 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
257 },
258 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
259 CONFIG_SYS_PCIE2_PHYS_SIZE,
260 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
261 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
262 },
Yuantian Tang4aefa162019-04-10 16:43:33 +0800263#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
York Sunef4cef92018-11-05 18:01:06 +0000264 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
265 CONFIG_SYS_PCIE3_PHYS_SIZE,
266 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
267 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
268 },
Yuantian Tang4aefa162019-04-10 16:43:33 +0800269#endif
Hou Zhiqiangd5d1ce32019-04-08 10:15:32 +0000270#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
York Sunef4cef92018-11-05 18:01:06 +0000271 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
272 CONFIG_SYS_PCIE4_PHYS_SIZE,
273 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
274 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
275 },
276#endif
Hou Zhiqiangd08f9702019-04-08 10:15:41 +0000277#ifdef SYS_PCIE5_PHYS_ADDR
278 { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
279 SYS_PCIE5_PHYS_SIZE,
280 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
281 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
282 },
283#endif
284#ifdef SYS_PCIE6_PHYS_ADDR
285 { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
286 SYS_PCIE6_PHYS_SIZE,
287 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
288 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
289 },
290#endif
York Sunef4cef92018-11-05 18:01:06 +0000291 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
292 CONFIG_SYS_FSL_WRIOP1_SIZE,
293 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
294 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
295 },
296 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
297 CONFIG_SYS_FSL_AIOP1_SIZE,
298 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
299 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
300 },
301 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
302 CONFIG_SYS_FSL_PEBUF_SIZE,
303 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
304 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
305 },
306 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
307 CONFIG_SYS_FSL_DRAM_SIZE2,
308 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
309 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
310 },
Priyanka Jain88c25662018-10-29 09:11:29 +0000311#ifdef CONFIG_SYS_FSL_DRAM_BASE3
312 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
313 CONFIG_SYS_FSL_DRAM_SIZE3,
314 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
315 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
316 },
317#endif
York Sunef4cef92018-11-05 18:01:06 +0000318#elif defined(CONFIG_FSL_LSCH2)
319 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
320 CONFIG_SYS_FSL_BOOTROM_SIZE,
321 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
322 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
323 },
324 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
325 CONFIG_SYS_FSL_CCSR_SIZE,
326 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
327 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
328 },
329 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
330 SYS_FSL_OCRAM_SPACE_SIZE,
331 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
332 },
333 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
334 CONFIG_SYS_FSL_DCSR_SIZE,
335 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
336 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
337 },
338 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
339 CONFIG_SYS_FSL_QSPI_SIZE,
340 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
341 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
342 },
343#ifdef CONFIG_FSL_IFC
344 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
345 CONFIG_SYS_FSL_IFC_SIZE,
346 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
347 },
348#endif
349 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
350 CONFIG_SYS_FSL_DRAM_SIZE1,
351 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
352 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
353 },
354 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
355 CONFIG_SYS_FSL_QBMAN_SIZE,
356 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
357 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
358 },
359 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
360 CONFIG_SYS_FSL_DRAM_SIZE2,
361 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
362 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
363 },
364 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
365 CONFIG_SYS_PCIE1_PHYS_SIZE,
366 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
367 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
368 },
369 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
370 CONFIG_SYS_PCIE2_PHYS_SIZE,
371 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
372 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
373 },
Yuantian Tang4aefa162019-04-10 16:43:33 +0800374#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
York Sunef4cef92018-11-05 18:01:06 +0000375 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
376 CONFIG_SYS_PCIE3_PHYS_SIZE,
377 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
378 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
379 },
Yuantian Tang4aefa162019-04-10 16:43:33 +0800380#endif
York Sunef4cef92018-11-05 18:01:06 +0000381 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
382 CONFIG_SYS_FSL_DRAM_SIZE3,
383 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
384 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
385 },
386#endif
387#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
388 {}, /* space holder for secure mem */
389#endif
390 {},
391};
392
York Sun9da8f502016-06-24 16:46:23 -0700393struct mm_region *mem_map = early_map;
Alexander Grafce0a64e2016-03-04 01:09:54 +0100394
Mingkai Hu0e58b512015-10-26 19:47:50 +0800395void cpu_name(char *name)
396{
397 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
398 unsigned int i, svr, ver;
399
400 svr = gur_in32(&gur->svr);
401 ver = SVR_SOC_VER(svr);
402
403 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
404 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
405 strcpy(name, cpu_type_list[i].name);
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000406#ifdef CONFIG_ARCH_LX2160A
407 if (IS_C_PROCESSOR(svr))
408 strcat(name, "C");
409#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +0800410
411 if (IS_E_PROCESSOR(svr))
412 strcat(name, "E");
Wenbin Song863a33a2016-09-13 16:13:54 +0800413
414 sprintf(name + strlen(name), " Rev%d.%d",
415 SVR_MAJ(svr), SVR_MIN(svr));
Mingkai Hu0e58b512015-10-26 19:47:50 +0800416 break;
417 }
418
419 if (i == ARRAY_SIZE(cpu_type_list))
420 strcpy(name, "unknown");
421}
422
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400423#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
Mingkai Hu0e58b512015-10-26 19:47:50 +0800424/*
425 * To start MMU before DDR is available, we create MMU table in SRAM.
426 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
427 * levels of translation tables here to cover 40-bit address space.
428 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
York Sun9da8f502016-06-24 16:46:23 -0700429 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
430 * Note, the debug print in cache_v8.c is not usable for debugging
431 * these early MMU tables because UART is not yet available.
Mingkai Hu0e58b512015-10-26 19:47:50 +0800432 */
433static inline void early_mmu_setup(void)
434{
York Sun9da8f502016-06-24 16:46:23 -0700435 unsigned int el = current_el();
Mingkai Hu0e58b512015-10-26 19:47:50 +0800436
York Sun9da8f502016-06-24 16:46:23 -0700437 /* global data is already setup, no allocation yet */
Pankit Gargc4d39eb2018-11-05 18:01:28 +0000438 if (el == 3)
439 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
440 else
441 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
York Sun9da8f502016-06-24 16:46:23 -0700442 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
443 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
Mingkai Hu0e58b512015-10-26 19:47:50 +0800444
York Sun9da8f502016-06-24 16:46:23 -0700445 /* Create early page tables */
446 setup_pgtables();
Mingkai Hu0e58b512015-10-26 19:47:50 +0800447
York Sun9da8f502016-06-24 16:46:23 -0700448 /* point TTBR to the new table */
449 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
450 get_tcr(el, NULL, NULL) &
451 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
Mingkai Hu0e58b512015-10-26 19:47:50 +0800452 MEMORY_ATTRIBUTES);
York Sun9da8f502016-06-24 16:46:23 -0700453
Mingkai Hu0e58b512015-10-26 19:47:50 +0800454 set_sctlr(get_sctlr() | CR_M);
455}
456
Hou Zhiqiang92fecb52017-03-03 12:35:09 +0800457static void fix_pcie_mmu_map(void)
458{
York Sun4ce6fbf2017-03-27 11:41:01 -0700459#ifdef CONFIG_ARCH_LS2080A
Hou Zhiqiang92fecb52017-03-03 12:35:09 +0800460 unsigned int i;
461 u32 svr, ver;
462 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
463
464 svr = gur_in32(&gur->svr);
465 ver = SVR_SOC_VER(svr);
466
467 /* Fix PCIE base and size for LS2088A */
468 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
Priyanka Jain2b361782017-04-27 15:08:06 +0530469 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
470 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
Hou Zhiqiang92fecb52017-03-03 12:35:09 +0800471 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
472 switch (final_map[i].phys) {
473 case CONFIG_SYS_PCIE1_PHYS_ADDR:
474 final_map[i].phys = 0x2000000000ULL;
475 final_map[i].virt = 0x2000000000ULL;
476 final_map[i].size = 0x800000000ULL;
477 break;
478 case CONFIG_SYS_PCIE2_PHYS_ADDR:
479 final_map[i].phys = 0x2800000000ULL;
480 final_map[i].virt = 0x2800000000ULL;
481 final_map[i].size = 0x800000000ULL;
482 break;
Yuantian Tang4aefa162019-04-10 16:43:33 +0800483#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
Hou Zhiqiang92fecb52017-03-03 12:35:09 +0800484 case CONFIG_SYS_PCIE3_PHYS_ADDR:
485 final_map[i].phys = 0x3000000000ULL;
486 final_map[i].virt = 0x3000000000ULL;
487 final_map[i].size = 0x800000000ULL;
488 break;
Yuantian Tang4aefa162019-04-10 16:43:33 +0800489#endif
Hou Zhiqiangd5d1ce32019-04-08 10:15:32 +0000490#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
Hou Zhiqiang92fecb52017-03-03 12:35:09 +0800491 case CONFIG_SYS_PCIE4_PHYS_ADDR:
492 final_map[i].phys = 0x3800000000ULL;
493 final_map[i].virt = 0x3800000000ULL;
494 final_map[i].size = 0x800000000ULL;
495 break;
Hou Zhiqiangd5d1ce32019-04-08 10:15:32 +0000496#endif
Hou Zhiqiang92fecb52017-03-03 12:35:09 +0800497 default:
498 break;
499 }
500 }
501 }
502#endif
503}
504
Mingkai Hu0e58b512015-10-26 19:47:50 +0800505/*
506 * The final tables look similar to early tables, but different in detail.
507 * These tables are in DRAM. Sub tables are added to enable cache for
508 * QBMan and OCRAM.
509 *
York Sun1ef95cc2016-06-24 16:46:18 -0700510 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
511 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
Mingkai Hu0e58b512015-10-26 19:47:50 +0800512 */
513static inline void final_mmu_setup(void)
514{
York Sun9da8f502016-06-24 16:46:23 -0700515 u64 tlb_addr_save = gd->arch.tlb_addr;
York Sun0804d562015-12-04 11:57:08 -0800516 unsigned int el = current_el();
York Sun9da8f502016-06-24 16:46:23 -0700517 int index;
Mingkai Hu0e58b512015-10-26 19:47:50 +0800518
Hou Zhiqiang92fecb52017-03-03 12:35:09 +0800519 /* fix the final_map before filling in the block entries */
520 fix_pcie_mmu_map();
521
York Sun9da8f502016-06-24 16:46:23 -0700522 mem_map = final_map;
Mingkai Hu0e58b512015-10-26 19:47:50 +0800523
York Sun75488ed2017-03-06 09:02:30 -0800524 /* Update mapping for DDR to actual size */
525 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
526 /*
527 * Find the entry for DDR mapping and update the address and
528 * size. Zero-sized mapping will be skipped when creating MMU
529 * table.
530 */
531 switch (final_map[index].virt) {
532 case CONFIG_SYS_FSL_DRAM_BASE1:
533 final_map[index].virt = gd->bd->bi_dram[0].start;
534 final_map[index].phys = gd->bd->bi_dram[0].start;
535 final_map[index].size = gd->bd->bi_dram[0].size;
536 break;
537#ifdef CONFIG_SYS_FSL_DRAM_BASE2
538 case CONFIG_SYS_FSL_DRAM_BASE2:
539#if (CONFIG_NR_DRAM_BANKS >= 2)
540 final_map[index].virt = gd->bd->bi_dram[1].start;
541 final_map[index].phys = gd->bd->bi_dram[1].start;
542 final_map[index].size = gd->bd->bi_dram[1].size;
543#else
544 final_map[index].size = 0;
545#endif
546 break;
547#endif
548#ifdef CONFIG_SYS_FSL_DRAM_BASE3
549 case CONFIG_SYS_FSL_DRAM_BASE3:
550#if (CONFIG_NR_DRAM_BANKS >= 3)
551 final_map[index].virt = gd->bd->bi_dram[2].start;
552 final_map[index].phys = gd->bd->bi_dram[2].start;
553 final_map[index].size = gd->bd->bi_dram[2].size;
554#else
555 final_map[index].size = 0;
556#endif
557 break;
558#endif
559 default:
560 break;
561 }
562 }
563
York Sun0804d562015-12-04 11:57:08 -0800564#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
York Sun9da8f502016-06-24 16:46:23 -0700565 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
566 if (el == 3) {
567 /*
568 * Only use gd->arch.secure_ram if the address is
569 * recalculated. Align to 4KB for MMU table.
570 */
571 /* put page tables in secure ram */
572 index = ARRAY_SIZE(final_map) - 2;
573 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
574 final_map[index].virt = gd->arch.secure_ram & ~0x3;
575 final_map[index].phys = final_map[index].virt;
576 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
577 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
York Sun1ef95cc2016-06-24 16:46:18 -0700578 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
York Sun9da8f502016-06-24 16:46:23 -0700579 tlb_addr_save = gd->arch.tlb_addr;
York Sun0804d562015-12-04 11:57:08 -0800580 } else {
York Sun9da8f502016-06-24 16:46:23 -0700581 /* Use allocated (board_f.c) memory for TLB */
582 tlb_addr_save = gd->arch.tlb_allocated;
583 gd->arch.tlb_addr = tlb_addr_save;
York Sun0804d562015-12-04 11:57:08 -0800584 }
585 }
586#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +0800587
York Sun9da8f502016-06-24 16:46:23 -0700588 /* Reset the fill ptr */
589 gd->arch.tlb_fillptr = tlb_addr_save;
590
591 /* Create normal system page tables */
592 setup_pgtables();
593
594 /* Create emergency page tables */
595 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
596 gd->arch.tlb_emerg = gd->arch.tlb_addr;
597 setup_pgtables();
598 gd->arch.tlb_addr = tlb_addr_save;
599
York Suncf64ced2017-03-06 09:02:31 -0800600 /* Disable cache and MMU */
601 dcache_disable(); /* TLBs are invalidated */
602 invalidate_icache_all();
Mingkai Hu0e58b512015-10-26 19:47:50 +0800603
604 /* point TTBR to the new table */
York Sun9da8f502016-06-24 16:46:23 -0700605 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
Mingkai Hu0e58b512015-10-26 19:47:50 +0800606 MEMORY_ATTRIBUTES);
York Suncf64ced2017-03-06 09:02:31 -0800607
York Suneb6eac12016-07-22 10:52:23 -0700608 set_sctlr(get_sctlr() | CR_M);
Mingkai Hu0e58b512015-10-26 19:47:50 +0800609}
610
Alexander Grafbc78b922016-03-21 20:26:12 +0100611u64 get_page_table_size(void)
612{
613 return 0x10000;
614}
615
Mingkai Hu0e58b512015-10-26 19:47:50 +0800616int arch_cpu_init(void)
617{
York Sune6b871e2017-05-15 08:51:59 -0700618 /*
619 * This function is called before U-Boot relocates itself to speed up
620 * on system running. It is not necessary to run if performance is not
621 * critical. Skip if MMU is already enabled by SPL or other means.
622 */
623 if (get_sctlr() & CR_M)
624 return 0;
625
Mingkai Hu0e58b512015-10-26 19:47:50 +0800626 icache_enable();
627 __asm_invalidate_dcache_all();
628 __asm_invalidate_tlb_all();
629 early_mmu_setup();
630 set_sctlr(get_sctlr() | CR_C);
631 return 0;
632}
633
Hou Zhiqianga7befa52016-06-28 20:18:12 +0800634void mmu_setup(void)
635{
636 final_mmu_setup();
637}
638
Mingkai Hu0e58b512015-10-26 19:47:50 +0800639/*
Hou Zhiqianga7befa52016-06-28 20:18:12 +0800640 * This function is called from common/board_r.c.
641 * It recreates MMU table in main memory.
Mingkai Hu0e58b512015-10-26 19:47:50 +0800642 */
643void enable_caches(void)
644{
Hou Zhiqianga7befa52016-06-28 20:18:12 +0800645 mmu_setup();
Mingkai Hu0e58b512015-10-26 19:47:50 +0800646 __asm_invalidate_tlb_all();
Hou Zhiqianga7befa52016-06-28 20:18:12 +0800647 icache_enable();
648 dcache_enable();
Mingkai Hu0e58b512015-10-26 19:47:50 +0800649}
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400650#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000651
652#ifdef CONFIG_TFABOOT
653enum boot_src __get_boot_src(u32 porsr1)
654{
655 enum boot_src src = BOOT_SOURCE_RESERVED;
656 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
Priyanka Jain88c25662018-10-29 09:11:29 +0000657#if !defined(CONFIG_NXP_LSCH3_2)
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000658 u32 val;
659#endif
660 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
661
662#if defined(CONFIG_FSL_LSCH3)
Priyanka Jain88c25662018-10-29 09:11:29 +0000663#if defined(CONFIG_NXP_LSCH3_2)
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000664 switch (rcw_src) {
665 case RCW_SRC_SDHC1_VAL:
666 src = BOOT_SOURCE_SD_MMC;
667 break;
668 case RCW_SRC_SDHC2_VAL:
669 src = BOOT_SOURCE_SD_MMC2;
670 break;
671 case RCW_SRC_I2C1_VAL:
672 src = BOOT_SOURCE_I2C1_EXTENDED;
673 break;
674 case RCW_SRC_FLEXSPI_NAND2K_VAL:
675 src = BOOT_SOURCE_XSPI_NAND;
676 break;
677 case RCW_SRC_FLEXSPI_NAND4K_VAL:
678 src = BOOT_SOURCE_XSPI_NAND;
679 break;
680 case RCW_SRC_RESERVED_1_VAL:
681 src = BOOT_SOURCE_RESERVED;
682 break;
683 case RCW_SRC_FLEXSPI_NOR_24B:
684 src = BOOT_SOURCE_XSPI_NOR;
685 break;
686 default:
687 src = BOOT_SOURCE_RESERVED;
688 }
689#else
690 val = rcw_src & RCW_SRC_TYPE_MASK;
691 if (val == RCW_SRC_NOR_VAL) {
692 val = rcw_src & NOR_TYPE_MASK;
693
694 switch (val) {
695 case NOR_16B_VAL:
696 case NOR_32B_VAL:
697 src = BOOT_SOURCE_IFC_NOR;
698 break;
699 default:
700 src = BOOT_SOURCE_RESERVED;
701 }
702 } else {
703 /* RCW SRC Serial Flash */
704 val = rcw_src & RCW_SRC_SERIAL_MASK;
705 switch (val) {
706 case RCW_SRC_QSPI_VAL:
707 /* RCW SRC Serial NOR (QSPI) */
708 src = BOOT_SOURCE_QSPI_NOR;
709 break;
710 case RCW_SRC_SD_CARD_VAL:
711 /* RCW SRC SD Card */
712 src = BOOT_SOURCE_SD_MMC;
713 break;
714 case RCW_SRC_EMMC_VAL:
715 /* RCW SRC EMMC */
Rajesh Bhagat5b73c902018-12-27 04:37:49 +0000716 src = BOOT_SOURCE_SD_MMC;
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000717 break;
718 case RCW_SRC_I2C1_VAL:
719 /* RCW SRC I2C1 Extended */
720 src = BOOT_SOURCE_I2C1_EXTENDED;
721 break;
722 default:
723 src = BOOT_SOURCE_RESERVED;
724 }
725 }
726#endif
727#elif defined(CONFIG_FSL_LSCH2)
728 /* RCW SRC NAND */
729 val = rcw_src & RCW_SRC_NAND_MASK;
730 if (val == RCW_SRC_NAND_VAL) {
731 val = rcw_src & NAND_RESERVED_MASK;
732 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
733 src = BOOT_SOURCE_IFC_NAND;
734
735 } else {
736 /* RCW SRC NOR */
737 val = rcw_src & RCW_SRC_NOR_MASK;
738 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
739 src = BOOT_SOURCE_IFC_NOR;
740 } else {
741 switch (rcw_src) {
742 case QSPI_VAL1:
743 case QSPI_VAL2:
744 src = BOOT_SOURCE_QSPI_NOR;
745 break;
746 case SD_VAL:
747 src = BOOT_SOURCE_SD_MMC;
748 break;
749 default:
750 src = BOOT_SOURCE_RESERVED;
751 }
752 }
753 }
754#endif
York Sun8f3f4ef2018-11-05 18:02:09 +0000755
756 if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
757 src = BOOT_SOURCE_QSPI_NOR;
758
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000759 debug("%s: src 0x%x\n", __func__, src);
760 return src;
761}
762
763enum boot_src get_boot_src(void)
764{
York Sun8f3f4ef2018-11-05 18:02:09 +0000765 struct pt_regs regs;
766 u32 porsr1 = 0;
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000767
768#if defined(CONFIG_FSL_LSCH3)
769 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000770#elif defined(CONFIG_FSL_LSCH2)
771 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
York Sun8f3f4ef2018-11-05 18:02:09 +0000772#endif
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000773
York Sun8f3f4ef2018-11-05 18:02:09 +0000774 if (current_el() == 2) {
775 regs.regs[0] = SIP_SVC_RCW;
776
777 smc_call(&regs);
778 if (!regs.regs[0])
779 porsr1 = regs.regs[1];
780 }
781
782 if (current_el() == 3 || !porsr1) {
783#ifdef CONFIG_FSL_LSCH3
784 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
785#elif defined(CONFIG_FSL_LSCH2)
786 porsr1 = in_be32(&gur->porsr1);
Mingkai Hu0e58b512015-10-26 19:47:50 +0800787#endif
York Sun8f3f4ef2018-11-05 18:02:09 +0000788 }
789
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000790 debug("%s: porsr1 0x%x\n", __func__, porsr1);
791
792 return __get_boot_src(porsr1);
793}
794
795#ifdef CONFIG_ENV_IS_IN_MMC
796int mmc_get_env_dev(void)
797{
798 enum boot_src src = get_boot_src();
799 int dev = CONFIG_SYS_MMC_ENV_DEV;
800
801 switch (src) {
802 case BOOT_SOURCE_SD_MMC:
803 dev = 0;
804 break;
805 case BOOT_SOURCE_SD_MMC2:
806 dev = 1;
807 break;
808 default:
809 break;
810 }
811
812 return dev;
813}
814#endif
815
816enum env_location env_get_location(enum env_operation op, int prio)
817{
818 enum boot_src src = get_boot_src();
819 enum env_location env_loc = ENVL_NOWHERE;
820
821 if (prio)
822 return ENVL_UNKNOWN;
823
Udit Agarwal5e9720c2019-04-23 06:06:04 +0000824#ifdef CONFIG_ENV_IS_NOWHERE
825 return env_loc;
Pankit Gargbdbf84f2018-11-05 18:01:52 +0000826#endif
827
Rajesh Bhagat583da8b2018-11-05 18:01:42 +0000828 switch (src) {
829 case BOOT_SOURCE_IFC_NOR:
830 env_loc = ENVL_FLASH;
831 break;
832 case BOOT_SOURCE_QSPI_NOR:
833 /* FALLTHROUGH */
834 case BOOT_SOURCE_XSPI_NOR:
835 env_loc = ENVL_SPI_FLASH;
836 break;
837 case BOOT_SOURCE_IFC_NAND:
838 /* FALLTHROUGH */
839 case BOOT_SOURCE_QSPI_NAND:
840 /* FALLTHROUGH */
841 case BOOT_SOURCE_XSPI_NAND:
842 env_loc = ENVL_NAND;
843 break;
844 case BOOT_SOURCE_SD_MMC:
845 /* FALLTHROUGH */
846 case BOOT_SOURCE_SD_MMC2:
847 env_loc = ENVL_MMC;
848 break;
849 case BOOT_SOURCE_I2C1_EXTENDED:
850 /* FALLTHROUGH */
851 default:
852 break;
853 }
854
855 return env_loc;
856}
857#endif /* CONFIG_TFABOOT */
Mingkai Hu0e58b512015-10-26 19:47:50 +0800858
Priyanka Jain9a276702016-11-17 12:29:56 +0530859u32 initiator_type(u32 cluster, int init_id)
Mingkai Hu0e58b512015-10-26 19:47:50 +0800860{
861 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
862 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
863 u32 type = 0;
864
865 type = gur_in32(&gur->tp_ityp[idx]);
866 if (type & TP_ITYP_AV)
867 return type;
868
869 return 0;
870}
871
York Suned7fbe32016-09-13 12:40:30 -0700872u32 cpu_pos_mask(void)
873{
874 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
875 int i = 0;
876 u32 cluster, type, mask = 0;
877
878 do {
879 int j;
880
881 cluster = gur_in32(&gur->tp_cluster[i].lower);
882 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
883 type = initiator_type(cluster, j);
884 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
885 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
886 }
887 i++;
888 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
889
890 return mask;
891}
892
Mingkai Hu0e58b512015-10-26 19:47:50 +0800893u32 cpu_mask(void)
894{
895 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
896 int i = 0, count = 0;
897 u32 cluster, type, mask = 0;
898
899 do {
900 int j;
901
902 cluster = gur_in32(&gur->tp_cluster[i].lower);
903 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
904 type = initiator_type(cluster, j);
905 if (type) {
906 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
907 mask |= 1 << count;
908 count++;
909 }
910 }
911 i++;
912 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
913
914 return mask;
915}
916
917/*
918 * Return the number of cores on this SOC.
919 */
920int cpu_numcores(void)
921{
922 return hweight32(cpu_mask());
923}
924
925int fsl_qoriq_core_to_cluster(unsigned int core)
926{
927 struct ccsr_gur __iomem *gur =
928 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
929 int i = 0, count = 0;
930 u32 cluster;
931
932 do {
933 int j;
934
935 cluster = gur_in32(&gur->tp_cluster[i].lower);
936 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
937 if (initiator_type(cluster, j)) {
938 if (count == core)
939 return i;
940 count++;
941 }
942 }
943 i++;
944 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
945
946 return -1; /* cannot identify the cluster */
947}
948
949u32 fsl_qoriq_core_to_type(unsigned int core)
950{
951 struct ccsr_gur __iomem *gur =
952 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
953 int i = 0, count = 0;
954 u32 cluster, type;
955
956 do {
957 int j;
958
959 cluster = gur_in32(&gur->tp_cluster[i].lower);
960 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
961 type = initiator_type(cluster, j);
962 if (type) {
963 if (count == core)
964 return type;
965 count++;
966 }
967 }
968 i++;
969 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
970
971 return -1; /* cannot identify the cluster */
972}
973
Priyanka Jain96b001f2016-11-17 12:29:51 +0530974#ifndef CONFIG_FSL_LSCH3
Sriram Dash9282d262016-06-13 09:58:32 +0530975uint get_svr(void)
976{
977 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
978
979 return gur_in32(&gur->svr);
980}
Priyanka Jain96b001f2016-11-17 12:29:51 +0530981#endif
Sriram Dash9282d262016-06-13 09:58:32 +0530982
Mingkai Hu0e58b512015-10-26 19:47:50 +0800983#ifdef CONFIG_DISPLAY_CPUINFO
984int print_cpuinfo(void)
985{
986 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
987 struct sys_info sysinfo;
988 char buf[32];
989 unsigned int i, core;
York Suncbe8e1c2016-04-04 11:41:26 -0700990 u32 type, rcw, svr = gur_in32(&gur->svr);
Mingkai Hu0e58b512015-10-26 19:47:50 +0800991
992 puts("SoC: ");
993
994 cpu_name(buf);
York Suncbe8e1c2016-04-04 11:41:26 -0700995 printf(" %s (0x%x)\n", buf, svr);
Mingkai Hu0e58b512015-10-26 19:47:50 +0800996 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
997 get_sys_info(&sysinfo);
998 puts("Clock Configuration:");
999 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
1000 if (!(i % 3))
1001 puts("\n ");
1002 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
1003 printf("CPU%d(%s):%-4s MHz ", core,
1004 type == TY_ITYP_VER_A7 ? "A7 " :
1005 (type == TY_ITYP_VER_A53 ? "A53" :
Alison Wang79808392016-07-05 16:01:52 +08001006 (type == TY_ITYP_VER_A57 ? "A57" :
1007 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
Mingkai Hu0e58b512015-10-26 19:47:50 +08001008 strmhz(buf, sysinfo.freq_processor[core]));
1009 }
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +08001010 /* Display platform clock as Bus frequency. */
Mingkai Hu0e58b512015-10-26 19:47:50 +08001011 printf("\n Bus: %-4s MHz ",
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +08001012 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
Mingkai Hu0e58b512015-10-26 19:47:50 +08001013 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
Shaohui Xie04643262015-10-26 19:47:54 +08001014#ifdef CONFIG_SYS_DPAA_FMAN
1015 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1016#endif
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +05301017#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Suncbe8e1c2016-04-04 11:41:26 -07001018 if (soc_has_dp_ddr()) {
1019 printf(" DP-DDR: %-4s MT/s",
1020 strmhz(buf, sysinfo.freq_ddrbus2));
1021 }
Mingkai Hu0e58b512015-10-26 19:47:50 +08001022#endif
1023 puts("\n");
1024
1025 /*
1026 * Display the RCW, so that no one gets confused as to what RCW
1027 * we're actually using for this boot.
1028 */
1029 puts("Reset Configuration Word (RCW):");
1030 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1031 rcw = gur_in32(&gur->rcwsr[i]);
1032 if ((i % 4) == 0)
1033 printf("\n %08x:", i * 4);
1034 printf(" %08x", rcw);
1035 }
1036 puts("\n");
1037
1038 return 0;
1039}
1040#endif
1041
1042#ifdef CONFIG_FSL_ESDHC
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001043int cpu_mmc_init(struct bd_info *bis)
Mingkai Hu0e58b512015-10-26 19:47:50 +08001044{
1045 return fsl_esdhc_mmc_init(bis);
1046}
1047#endif
1048
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001049int cpu_eth_init(struct bd_info *bis)
Mingkai Hu0e58b512015-10-26 19:47:50 +08001050{
1051 int error = 0;
1052
Santan Kumar1afa9002017-05-05 15:42:29 +05301053#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
Mingkai Hu0e58b512015-10-26 19:47:50 +08001054 error = fsl_mc_ldpaa_init(bis);
1055#endif
Shaohui Xie04643262015-10-26 19:47:54 +08001056#ifdef CONFIG_FMAN_ENET
1057 fm_standard_init(bis);
1058#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +08001059 return error;
1060}
1061
Yuantian Tangaec3b142017-04-19 13:27:39 +08001062static inline int check_psci(void)
Mingkai Hu0e58b512015-10-26 19:47:50 +08001063{
Yuantian Tangaec3b142017-04-19 13:27:39 +08001064 unsigned int psci_ver;
Prabhakar Kushwaha22cfe962015-11-05 12:00:14 +05301065
Yuantian Tangaec3b142017-04-19 13:27:39 +08001066 psci_ver = sec_firmware_support_psci_version();
1067 if (psci_ver == PSCI_INVALID_VER)
1068 return 1;
1069
1070 return 0;
1071}
1072
Prabhakar Kushwaha0acce842017-11-10 11:32:52 +05301073static void config_core_prefetch(void)
1074{
1075 char *buf = NULL;
1076 char buffer[HWCONFIG_BUFFER_SIZE];
1077 const char *prefetch_arg = NULL;
1078 size_t arglen;
1079 unsigned int mask;
1080 struct pt_regs regs;
1081
1082 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1083 buf = buffer;
Pankaj Bansal6c772772019-10-31 05:41:09 +00001084 else
1085 return;
Prabhakar Kushwaha0acce842017-11-10 11:32:52 +05301086
1087 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1088 &arglen, buf);
1089
1090 if (prefetch_arg) {
1091 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1092 if (mask & 0x1) {
1093 printf("Core0 prefetch can't be disabled\n");
1094 return;
1095 }
1096
1097#define SIP_PREFETCH_DISABLE_64 0xC200FF13
1098 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1099 regs.regs[1] = mask;
1100 smc_call(&regs);
1101
1102 if (regs.regs[0])
1103 printf("Prefetch disable config failed for mask ");
1104 else
1105 printf("Prefetch disable config passed for mask ");
1106 printf("0x%x\n", mask);
1107 }
1108}
1109
Alex Marginean762a2682019-11-27 17:19:32 +02001110#ifdef CONFIG_PCIE_ECAM_GENERIC
1111__weak void set_ecam_icids(void)
1112{
1113}
1114#endif
1115
Yuantian Tangaec3b142017-04-19 13:27:39 +08001116int arch_early_init_r(void)
1117{
Prabhakar Kushwaha22cfe962015-11-05 12:00:14 +05301118#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
Priyanka Jain823e0422017-02-14 10:34:31 +05301119 u32 svr_dev_id;
1120 /*
1121 * erratum A009635 is valid only for LS2080A SoC and
1122 * its personalitiesi
1123 */
Wenbin song5d8a61c2017-12-04 12:18:28 +08001124 svr_dev_id = get_svr();
1125 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
Priyanka Jain823e0422017-02-14 10:34:31 +05301126 erratum_a009635();
Prabhakar Kushwaha22cfe962015-11-05 12:00:14 +05301127#endif
Shengzhou Liu15875a52016-11-21 11:36:48 +08001128#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1129 erratum_a009942_check_cpo();
1130#endif
Yuantian Tangaec3b142017-04-19 13:27:39 +08001131 if (check_psci()) {
1132 debug("PSCI: PSCI does not exist.\n");
1133
1134 /* if PSCI does not exist, boot secondary cores here */
1135 if (fsl_layerscape_wake_seconday_cores())
Hou Zhiqiang21c4d552016-06-28 20:18:15 +08001136 printf("Did not wake secondary cores\n");
1137 }
Mingkai Hu0e58b512015-10-26 19:47:50 +08001138
Prabhakar Kushwaha0acce842017-11-10 11:32:52 +05301139 config_core_prefetch();
1140
Mingkai Hu0e58b512015-10-26 19:47:50 +08001141#ifdef CONFIG_SYS_HAS_SERDES
1142 fsl_serdes_init();
1143#endif
Pankaj Bansalcc840622018-10-29 11:28:26 +00001144#ifdef CONFIG_SYS_FSL_HAS_RGMII
1145 /* some dpmacs in armv8a based freescale layerscape SOCs can be
1146 * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1147 * EC*_PMUX(rgmii) bits in RCW.
1148 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1149 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1150 * Now if a dpmac is enabled by serdes bits then it takes precedence
1151 * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1152 * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1153 * then the dpmac is SGMII and not RGMII.
1154 *
1155 * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1156 * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1157 * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1158 * then don't enable it.
1159 */
1160 fsl_rgmii_init();
1161#endif
Shaohui Xie04643262015-10-26 19:47:54 +08001162#ifdef CONFIG_FMAN_ENET
Madalin Bucurb76b0a62020-04-23 16:25:19 +03001163#ifndef CONFIG_DM_ETH
Shaohui Xie04643262015-10-26 19:47:54 +08001164 fman_enet_init();
1165#endif
Madalin Bucurb76b0a62020-04-23 16:25:19 +03001166#endif
Ahmed Mansouraa270b42017-12-15 16:01:00 -05001167#ifdef CONFIG_SYS_DPAA_QBMAN
1168 setup_qbman_portals();
1169#endif
Alex Marginean762a2682019-11-27 17:19:32 +02001170#ifdef CONFIG_PCIE_ECAM_GENERIC
1171 set_ecam_icids();
1172#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +08001173 return 0;
1174}
1175
1176int timer_init(void)
1177{
1178 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1179#ifdef CONFIG_FSL_LSCH3
1180 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1181#endif
Thomas Schaefercbec2b82019-08-08 16:00:30 +08001182#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1183 defined(CONFIG_ARCH_LS1028A)
Yunhui Cui3dfb82a2016-06-08 10:31:42 +08001184 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
Priyanka Jain3d31ec72016-11-17 12:29:52 +05301185 u32 svr_dev_id;
Yunhui Cui3dfb82a2016-06-08 10:31:42 +08001186#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +08001187#ifdef COUNTER_FREQUENCY_REAL
1188 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1189
1190 /* Update with accurate clock frequency */
York Sune6b871e2017-05-15 08:51:59 -07001191 if (current_el() == 3)
1192 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
Mingkai Hu0e58b512015-10-26 19:47:50 +08001193#endif
1194
1195#ifdef CONFIG_FSL_LSCH3
1196 /* Enable timebase for all clusters.
1197 * It is safe to do so even some clusters are not enabled.
1198 */
1199 out_le32(cltbenr, 0xf);
1200#endif
1201
Thomas Schaefercbec2b82019-08-08 16:00:30 +08001202#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1203 defined(CONFIG_ARCH_LS1028A)
Yunhui Cui3dfb82a2016-06-08 10:31:42 +08001204 /*
1205 * In certain Layerscape SoCs, the clock for each core's
1206 * has an enable bit in the PMU Physical Core Time Base Enable
1207 * Register (PCTBENR), which allows the watchdog to operate.
1208 */
1209 setbits_le32(pctbenr, 0xff);
Priyanka Jain3d31ec72016-11-17 12:29:52 +05301210 /*
1211 * For LS2080A SoC and its personalities, timer controller
1212 * offset is different
1213 */
Wenbin song5d8a61c2017-12-04 12:18:28 +08001214 svr_dev_id = get_svr();
1215 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
Priyanka Jain3d31ec72016-11-17 12:29:52 +05301216 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1217
Yunhui Cui3dfb82a2016-06-08 10:31:42 +08001218#endif
1219
Mingkai Hu0e58b512015-10-26 19:47:50 +08001220 /* Enable clock for timer
1221 * This is a global setting.
1222 */
1223 out_le32(cntcr, 0x1);
1224
1225 return 0;
1226}
1227
Alexander Graf12be31c2016-11-17 01:03:01 +01001228__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1229
1230void __efi_runtime reset_cpu(ulong addr)
Mingkai Hu0e58b512015-10-26 19:47:50 +08001231{
Mingkai Hu0e58b512015-10-26 19:47:50 +08001232 u32 val;
1233
Priyanka Jainef76b2e2018-10-29 09:17:09 +00001234#ifdef CONFIG_ARCH_LX2160A
1235 val = in_le32(rstcr);
1236 val |= 0x01;
1237 out_le32(rstcr, val);
1238#else
Mingkai Hu0e58b512015-10-26 19:47:50 +08001239 /* Raise RESET_REQ_B */
1240 val = scfg_in32(rstcr);
1241 val |= 0x02;
1242 scfg_out32(rstcr, val);
Priyanka Jainef76b2e2018-10-29 09:17:09 +00001243#endif
Mingkai Hu0e58b512015-10-26 19:47:50 +08001244}
York Sun928b6812015-12-07 11:08:58 -08001245
Mathew McBride8f137732019-10-18 14:27:54 +11001246#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
Alexander Graf12be31c2016-11-17 01:03:01 +01001247
1248void __efi_runtime EFIAPI efi_reset_system(
1249 enum efi_reset_type reset_type,
1250 efi_status_t reset_status,
1251 unsigned long data_size, void *reset_data)
1252{
1253 switch (reset_type) {
1254 case EFI_RESET_COLD:
1255 case EFI_RESET_WARM:
Heinrich Schuchardt450d4c82018-02-06 22:00:22 +01001256 case EFI_RESET_PLATFORM_SPECIFIC:
Alexander Graf12be31c2016-11-17 01:03:01 +01001257 reset_cpu(0);
1258 break;
1259 case EFI_RESET_SHUTDOWN:
1260 /* Nothing we can do */
1261 break;
1262 }
1263
1264 while (1) { }
1265}
1266
Heinrich Schuchardt099b3b72018-03-03 15:28:59 +01001267efi_status_t efi_reset_system_init(void)
Alexander Graf12be31c2016-11-17 01:03:01 +01001268{
Heinrich Schuchardt099b3b72018-03-03 15:28:59 +01001269 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
Alexander Graf12be31c2016-11-17 01:03:01 +01001270}
1271
1272#endif
1273
York Sun2db54082017-09-07 10:12:32 -07001274/*
1275 * Calculate reserved memory with given memory bank
1276 * Return aligned memory size on success
1277 * Return (ram_size + needed size) for failure
1278 */
York Sun928b6812015-12-07 11:08:58 -08001279phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1280{
1281 phys_size_t ram_top = ram_size;
1282
Santan Kumar1afa9002017-05-05 15:42:29 +05301283#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
York Sun2db54082017-09-07 10:12:32 -07001284 ram_top = mc_get_dram_block_size();
1285 if (ram_top > ram_size)
1286 return ram_size + ram_top;
1287
1288 ram_top = ram_size - ram_top;
York Sun4de24ef2017-03-06 09:02:28 -08001289 /* The start address of MC reserved memory needs to be aligned. */
York Sun928b6812015-12-07 11:08:58 -08001290 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1291#endif
York Sun4de24ef2017-03-06 09:02:28 -08001292
1293 return ram_size - ram_top;
1294}
1295
1296phys_size_t get_effective_memsize(void)
1297{
1298 phys_size_t ea_size, rem = 0;
1299
1300 /*
1301 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
Sumit Garged0deea2017-10-04 03:20:49 +05301302 * first region is 2GB space at 0x8000_0000. Secure memory needs to
1303 * allocated from first region. If the memory extends to the second
1304 * region (or the third region if applicable), Management Complex (MC)
1305 * memory should be put into the highest region, i.e. the end of DDR
1306 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1307 * U-Boot doesn't relocate itself into higher address. Should DDR be
1308 * configured to skip the first region, this function needs to be
1309 * adjusted.
York Sun4de24ef2017-03-06 09:02:28 -08001310 */
1311 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1312 ea_size = CONFIG_MAX_MEM_MAPPED;
1313 rem = gd->ram_size - ea_size;
1314 } else {
1315 ea_size = gd->ram_size;
1316 }
1317
1318#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1319 /* Check if we have enough space for secure memory */
Sumit Garged0deea2017-10-04 03:20:49 +05301320 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1321 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1322 else
1323 printf("Error: No enough space for secure memory.\n");
York Sun4de24ef2017-03-06 09:02:28 -08001324#endif
1325 /* Check if we have enough memory for MC */
1326 if (rem < board_reserve_ram_top(rem)) {
1327 /* Not enough memory in high region to reserve */
York Sun2db54082017-09-07 10:12:32 -07001328 if (ea_size > board_reserve_ram_top(ea_size))
1329 ea_size -= board_reserve_ram_top(ea_size);
York Sun4de24ef2017-03-06 09:02:28 -08001330 else
1331 printf("Error: No enough space for reserved memory.\n");
1332 }
1333
1334 return ea_size;
1335}
1336
Rajesh Bhagat1dde2d22018-11-05 18:01:58 +00001337#ifdef CONFIG_TFABOOT
1338phys_size_t tfa_get_dram_size(void)
1339{
1340 struct pt_regs regs;
1341 phys_size_t dram_size = 0;
1342
1343 regs.regs[0] = SMC_DRAM_BANK_INFO;
1344 regs.regs[1] = -1;
1345
1346 smc_call(&regs);
1347 if (regs.regs[0])
1348 return 0;
1349
1350 dram_size = regs.regs[1];
1351 return dram_size;
1352}
1353
1354static int tfa_dram_init_banksize(void)
1355{
1356 int i = 0, ret = 0;
1357 struct pt_regs regs;
1358 phys_size_t dram_size = tfa_get_dram_size();
1359
1360 debug("dram_size %llx\n", dram_size);
1361
1362 if (!dram_size)
1363 return -EINVAL;
1364
1365 do {
1366 regs.regs[0] = SMC_DRAM_BANK_INFO;
1367 regs.regs[1] = i;
1368
1369 smc_call(&regs);
1370 if (regs.regs[0]) {
1371 ret = -EINVAL;
1372 break;
1373 }
1374
1375 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1376 regs.regs[2]);
1377 gd->bd->bi_dram[i].start = regs.regs[1];
1378 gd->bd->bi_dram[i].size = regs.regs[2];
1379
1380 dram_size -= gd->bd->bi_dram[i].size;
1381
1382 i++;
1383 } while (dram_size);
1384
1385 if (i > 0)
1386 ret = 0;
1387
Hou Zhiqiang80de3732020-04-28 10:19:28 +08001388#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
Rajesh Bhagat1dde2d22018-11-05 18:01:58 +00001389 /* Assign memory for MC */
1390#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1391 if (gd->bd->bi_dram[2].size >=
1392 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1393 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1394 gd->bd->bi_dram[2].size -
1395 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1396 } else
1397#endif
1398 {
1399 if (gd->bd->bi_dram[1].size >=
1400 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1401 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1402 gd->bd->bi_dram[1].size -
1403 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1404 } else if (gd->bd->bi_dram[0].size >
1405 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1406 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1407 gd->bd->bi_dram[0].size -
1408 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1409 }
1410 }
Hou Zhiqiang80de3732020-04-28 10:19:28 +08001411#endif /* CONFIG_RESV_RAM */
Rajesh Bhagat1dde2d22018-11-05 18:01:58 +00001412
1413 return ret;
1414}
1415#endif
1416
Simon Glass2f949c32017-03-31 08:40:32 -06001417int dram_init_banksize(void)
York Sun4de24ef2017-03-06 09:02:28 -08001418{
1419#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1420 phys_size_t dp_ddr_size;
1421#endif
1422
Rajesh Bhagat1dde2d22018-11-05 18:01:58 +00001423#ifdef CONFIG_TFABOOT
1424 if (!tfa_dram_init_banksize())
1425 return 0;
1426#endif
York Sun4de24ef2017-03-06 09:02:28 -08001427 /*
1428 * gd->ram_size has the total size of DDR memory, less reserved secure
1429 * memory. The DDR extends from low region to high region(s) presuming
1430 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1431 * the location of secure memory. gd->arch.resv_ram tracks the location
York Sunc9e3e042017-09-28 08:42:12 -07001432 * of reserved memory for Management Complex (MC). Because gd->ram_size
1433 * is reduced by this function if secure memory is reserved, checking
1434 * gd->arch.secure_ram should be done to avoid running it repeatedly.
York Sun4de24ef2017-03-06 09:02:28 -08001435 */
York Sunc9e3e042017-09-28 08:42:12 -07001436
1437#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1438 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1439 debug("No need to run again, skip %s\n", __func__);
1440
1441 return 0;
1442 }
1443#endif
1444
York Sun4de24ef2017-03-06 09:02:28 -08001445 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1446 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1447 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1448 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1449 gd->bd->bi_dram[1].size = gd->ram_size -
1450 CONFIG_SYS_DDR_BLOCK1_SIZE;
1451#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1452 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1453 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1454 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1455 CONFIG_SYS_DDR_BLOCK2_SIZE;
1456 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1457 }
1458#endif
1459 } else {
1460 gd->bd->bi_dram[0].size = gd->ram_size;
1461 }
1462#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
Sumit Garged0deea2017-10-04 03:20:49 +05301463 if (gd->bd->bi_dram[0].size >
1464 CONFIG_SYS_MEM_RESERVE_SECURE) {
1465 gd->bd->bi_dram[0].size -=
1466 CONFIG_SYS_MEM_RESERVE_SECURE;
1467 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1468 gd->bd->bi_dram[0].size;
York Sun4de24ef2017-03-06 09:02:28 -08001469 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1470 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
York Sun4de24ef2017-03-06 09:02:28 -08001471 }
1472#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
1473
Hou Zhiqiang80de3732020-04-28 10:19:28 +08001474#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
York Sun4de24ef2017-03-06 09:02:28 -08001475 /* Assign memory for MC */
1476#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1477 if (gd->bd->bi_dram[2].size >=
1478 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1479 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1480 gd->bd->bi_dram[2].size -
1481 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1482 } else
1483#endif
1484 {
1485 if (gd->bd->bi_dram[1].size >=
1486 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1487 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1488 gd->bd->bi_dram[1].size -
1489 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1490 } else if (gd->bd->bi_dram[0].size >
1491 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1492 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1493 gd->bd->bi_dram[0].size -
1494 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1495 }
1496 }
Hou Zhiqiang80de3732020-04-28 10:19:28 +08001497#endif /* CONFIG_RESV_RAM */
York Sun4de24ef2017-03-06 09:02:28 -08001498
1499#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1500#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1501#error "This SoC shouldn't have DP DDR"
1502#endif
1503 if (soc_has_dp_ddr()) {
1504 /* initialize DP-DDR here */
1505 puts("DP-DDR: ");
1506 /*
1507 * DDR controller use 0 as the base address for binding.
1508 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1509 */
1510 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1511 CONFIG_DP_DDR_CTRL,
1512 CONFIG_DP_DDR_NUM_CTRLS,
1513 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1514 NULL, NULL, NULL);
1515 if (dp_ddr_size) {
1516 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1517 gd->bd->bi_dram[2].size = dp_ddr_size;
1518 } else {
1519 puts("Not detected");
1520 }
1521 }
1522#endif
Simon Glass2f949c32017-03-31 08:40:32 -06001523
York Sunc9e3e042017-09-28 08:42:12 -07001524#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1525 debug("%s is called. gd->ram_size is reduced to %lu\n",
1526 __func__, (ulong)gd->ram_size);
1527#endif
1528
Simon Glass2f949c32017-03-31 08:40:32 -06001529 return 0;
York Sun4de24ef2017-03-06 09:02:28 -08001530}
1531
Stephen Warrend0de8062018-08-30 15:43:43 -06001532#if CONFIG_IS_ENABLED(EFI_LOADER)
York Sun4de24ef2017-03-06 09:02:28 -08001533void efi_add_known_memory(void)
1534{
1535 int i;
Michael Walle282d3862020-05-17 12:29:19 +02001536 phys_addr_t ram_start;
York Sun4de24ef2017-03-06 09:02:28 -08001537 phys_size_t ram_size;
York Sun928b6812015-12-07 11:08:58 -08001538
York Sun4de24ef2017-03-06 09:02:28 -08001539 /* Add RAM */
1540 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1541#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1542#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1543#error "This SoC shouldn't have DP DDR"
1544#endif
1545 if (i == 2)
1546 continue; /* skip DP-DDR */
1547#endif
1548 ram_start = gd->bd->bi_dram[i].start;
1549 ram_size = gd->bd->bi_dram[i].size;
1550#ifdef CONFIG_RESV_RAM
1551 if (gd->arch.resv_ram >= ram_start &&
1552 gd->arch.resv_ram < ram_start + ram_size)
1553 ram_size = gd->arch.resv_ram - ram_start;
1554#endif
Michael Walle282d3862020-05-17 12:29:19 +02001555 efi_add_memory_map(ram_start, ram_size,
1556 EFI_CONVENTIONAL_MEMORY);
York Sun4de24ef2017-03-06 09:02:28 -08001557 }
York Sun928b6812015-12-07 11:08:58 -08001558}
York Sun4de24ef2017-03-06 09:02:28 -08001559#endif
York Sun729f2d12017-03-06 09:02:34 -08001560
1561/*
1562 * Before DDR size is known, early MMU table have DDR mapped as device memory
1563 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1564 * needs to be set for these mappings.
1565 * If a special case configures DDR with holes in the mapping, the holes need
1566 * to be marked as invalid. This is not implemented in this function.
1567 */
1568void update_early_mmu_table(void)
1569{
1570 if (!gd->arch.tlb_addr)
1571 return;
1572
1573 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1574 mmu_change_region_attr(
1575 CONFIG_SYS_SDRAM_BASE,
1576 gd->ram_size,
1577 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1578 PTE_BLOCK_OUTER_SHARE |
1579 PTE_BLOCK_NS |
1580 PTE_TYPE_VALID);
1581 } else {
1582 mmu_change_region_attr(
1583 CONFIG_SYS_SDRAM_BASE,
1584 CONFIG_SYS_DDR_BLOCK1_SIZE,
1585 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1586 PTE_BLOCK_OUTER_SHARE |
1587 PTE_BLOCK_NS |
1588 PTE_TYPE_VALID);
1589#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1590#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1591#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1592#endif
1593 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1594 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1595 mmu_change_region_attr(
1596 CONFIG_SYS_DDR_BLOCK2_BASE,
1597 CONFIG_SYS_DDR_BLOCK2_SIZE,
1598 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1599 PTE_BLOCK_OUTER_SHARE |
1600 PTE_BLOCK_NS |
1601 PTE_TYPE_VALID);
1602 mmu_change_region_attr(
1603 CONFIG_SYS_DDR_BLOCK3_BASE,
1604 gd->ram_size -
1605 CONFIG_SYS_DDR_BLOCK1_SIZE -
1606 CONFIG_SYS_DDR_BLOCK2_SIZE,
1607 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1608 PTE_BLOCK_OUTER_SHARE |
1609 PTE_BLOCK_NS |
1610 PTE_TYPE_VALID);
1611 } else
1612#endif
1613 {
1614 mmu_change_region_attr(
1615 CONFIG_SYS_DDR_BLOCK2_BASE,
1616 gd->ram_size -
1617 CONFIG_SYS_DDR_BLOCK1_SIZE,
1618 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1619 PTE_BLOCK_OUTER_SHARE |
1620 PTE_BLOCK_NS |
1621 PTE_TYPE_VALID);
1622 }
1623 }
1624}
1625
1626__weak int dram_init(void)
1627{
Simon Glass0e0ac202017-04-06 12:47:04 -06001628 fsl_initdram();
Rajesh Bhagat5efbecf2018-11-05 18:01:37 +00001629#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1630 defined(CONFIG_SPL_BUILD)
York Sun729f2d12017-03-06 09:02:34 -08001631 /* This will break-before-make MMU for DDR */
1632 update_early_mmu_table();
1633#endif
1634
1635 return 0;
1636}
Alex Marginean47568ce2020-01-11 01:05:40 +02001637
1638#ifdef CONFIG_ARCH_MISC_INIT
1639__weak int serdes_misc_init(void)
1640{
1641 return 0;
1642}
1643
1644int arch_misc_init(void)
1645{
1646 serdes_misc_init();
1647
1648 return 0;
1649}
1650#endif