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Tom Rini8b0c8a12018-05-06 18:27:01 -04001/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
Patrick Delaunay85b53972018-03-12 10:46:10 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay85b53972018-03-12 10:46:10 +01004 */
5
6#ifndef _MACH_STM32_H_
7#define _MACH_STM32_H_
8
Simon Glass4dcacfc2020-05-10 11:40:13 -06009#ifndef __ASSEMBLY__
10#include <linux/bitops.h>
11#endif
12
Patrick Delaunay85b53972018-03-12 10:46:10 +010013/*
14 * Peripheral memory map
15 * only address used before device tree parsing
16 */
17#define STM32_RCC_BASE 0x50000000
18#define STM32_PWR_BASE 0x50001000
Marek Vasut83ec9582022-02-25 02:15:59 +010019#define STM32_SYSCFG_BASE 0x50020000
Patrick Delaunay123687c2022-05-20 18:24:46 +020020#ifdef CONFIG_STM32MP15x
Patrick Delaunay85b53972018-03-12 10:46:10 +010021#define STM32_DBGMCU_BASE 0x50081000
Patrick Delaunay123687c2022-05-20 18:24:46 +020022#endif
Marek Vasut93865c62020-03-26 16:57:26 +010023#define STM32_FMC2_BASE 0x58002000
Marek Vasut83ec9582022-02-25 02:15:59 +010024#define STM32_DDRCTRL_BASE 0x5A003000
25#define STM32_DDRPHYC_BASE 0x5A004000
Patrick Delaunay85b53972018-03-12 10:46:10 +010026#define STM32_TZC_BASE 0x5C006000
27#define STM32_ETZPC_BASE 0x5C007000
Patrick Delaunay82b88ef2019-07-05 17:20:11 +020028#define STM32_STGEN_BASE 0x5C008000
Patrick Delaunay85b53972018-03-12 10:46:10 +010029#define STM32_TAMP_BASE 0x5C00A000
30
Patrick Delaunay123687c2022-05-20 18:24:46 +020031#ifdef CONFIG_STM32MP15x
Patrick Delaunay82168e82018-05-17 14:50:46 +020032#define STM32_USART1_BASE 0x5C000000
33#define STM32_USART2_BASE 0x4000E000
Patrick Delaunay123687c2022-05-20 18:24:46 +020034#endif
35#ifdef CONFIG_STM32MP13x
36#define STM32_USART1_BASE 0x4c000000
37#define STM32_USART2_BASE 0x4c001000
38#endif
Patrick Delaunay82168e82018-05-17 14:50:46 +020039#define STM32_USART3_BASE 0x4000F000
40#define STM32_UART4_BASE 0x40010000
41#define STM32_UART5_BASE 0x40011000
42#define STM32_USART6_BASE 0x44003000
43#define STM32_UART7_BASE 0x40018000
44#define STM32_UART8_BASE 0x40019000
Patrick Delaunay82168e82018-05-17 14:50:46 +020045
Patrick Delaunay5c2f6d72021-07-06 17:19:45 +020046#define STM32_SDMMC1_BASE 0x58005000
47#define STM32_SDMMC2_BASE 0x58007000
48#define STM32_SDMMC3_BASE 0x48004000
49
Patrick Delaunay123687c2022-05-20 18:24:46 +020050#ifdef CONFIG_STM32MP15x
Patrick Delaunay85b53972018-03-12 10:46:10 +010051#define STM32_SYSRAM_BASE 0x2FFC0000
52#define STM32_SYSRAM_SIZE SZ_256K
Patrick Delaunay123687c2022-05-20 18:24:46 +020053#endif
Patrick Delaunay85b53972018-03-12 10:46:10 +010054
55#define STM32_DDR_BASE 0xC0000000
56#define STM32_DDR_SIZE SZ_1G
57
Patrick Delaunayc5d15652018-03-20 10:54:53 +010058#ifndef __ASSEMBLY__
Patrick Delaunay089d4352018-03-20 11:45:14 +010059/* enumerated used to identify the SYSCON driver instance */
60enum {
61 STM32MP_SYSCON_UNKNOWN,
Patrick Delaunay63ae49e2019-02-27 17:01:23 +010062 STM32MP_SYSCON_SYSCFG,
Patrick Delaunay089d4352018-03-20 11:45:14 +010063};
Patrick Delaunayc5d15652018-03-20 10:54:53 +010064
65/*
66 * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
67 * - boot device = bit 8:4
68 * - boot instance = bit 3:0
69 */
70#define BOOT_TYPE_MASK 0xF0
71#define BOOT_TYPE_SHIFT 4
72#define BOOT_INSTANCE_MASK 0x0F
73#define BOOT_INSTANCE_SHIFT 0
74
75enum boot_device {
76 BOOT_FLASH_SD = 0x10,
77 BOOT_FLASH_SD_1 = 0x11,
78 BOOT_FLASH_SD_2 = 0x12,
79 BOOT_FLASH_SD_3 = 0x13,
80
81 BOOT_FLASH_EMMC = 0x20,
82 BOOT_FLASH_EMMC_1 = 0x21,
83 BOOT_FLASH_EMMC_2 = 0x22,
84 BOOT_FLASH_EMMC_3 = 0x23,
85
86 BOOT_FLASH_NAND = 0x30,
87 BOOT_FLASH_NAND_FMC = 0x31,
88
89 BOOT_FLASH_NOR = 0x40,
90 BOOT_FLASH_NOR_QSPI = 0x41,
91
92 BOOT_SERIAL_UART = 0x50,
93 BOOT_SERIAL_UART_1 = 0x51,
94 BOOT_SERIAL_UART_2 = 0x52,
95 BOOT_SERIAL_UART_3 = 0x53,
96 BOOT_SERIAL_UART_4 = 0x54,
97 BOOT_SERIAL_UART_5 = 0x55,
98 BOOT_SERIAL_UART_6 = 0x56,
99 BOOT_SERIAL_UART_7 = 0x57,
100 BOOT_SERIAL_UART_8 = 0x58,
101
102 BOOT_SERIAL_USB = 0x60,
103 BOOT_SERIAL_USB_OTG = 0x62,
Patrick Delaunayb5a7ca22020-03-18 09:22:52 +0100104
105 BOOT_FLASH_SPINAND = 0x70,
106 BOOT_FLASH_SPINAND_1 = 0x71,
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100107};
108
109/* TAMP registers */
110#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
Patrick Delaunay123687c2022-05-20 18:24:46 +0200111
112#ifdef CONFIG_STM32MP15x
Patrick Delaunaye0207372018-04-16 10:13:24 +0200113#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
114#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
Fabien Dessenned7700d12019-10-30 14:38:29 +0100115#define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17)
116#define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18)
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100117#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
Patrick Delaunay9c07f4a2019-04-18 17:32:45 +0200118#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21)
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100119
Fabien Dessenned7700d12019-10-30 14:38:29 +0100120#define TAMP_COPRO_STATE_OFF 0
121#define TAMP_COPRO_STATE_INIT 1
122#define TAMP_COPRO_STATE_CRUN 2
123#define TAMP_COPRO_STATE_CSTOP 3
124#define TAMP_COPRO_STATE_STANDBY 4
125#define TAMP_COPRO_STATE_CRASH 5
Patrick Delaunay123687c2022-05-20 18:24:46 +0200126#endif
127
128#ifdef CONFIG_STM32MP13x
129#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31)
130#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
131#endif
Fabien Dessenned7700d12019-10-30 14:38:29 +0100132
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100133#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
134#define TAMP_BOOT_MODE_SHIFT 8
135#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
136#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
Patrick Delaunay008d3c32019-02-27 17:01:20 +0100137#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
138
139enum forced_boot_mode {
140 BOOT_NORMAL = 0x00,
141 BOOT_FASTBOOT = 0x01,
142 BOOT_RECOVERY = 0x02,
143 BOOT_STM32PROG = 0x03,
144 BOOT_UMS_MMC0 = 0x10,
145 BOOT_UMS_MMC1 = 0x11,
146 BOOT_UMS_MMC2 = 0x12,
147};
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100148
Patrick Delaunay14d6a242018-05-17 15:24:05 +0200149/* offset used for BSEC driver: misc_read and misc_write */
150#define STM32_BSEC_SHADOW_OFFSET 0x0
Patrick Delaunay92dc1022019-02-12 11:44:41 +0100151#define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4)
Patrick Delaunay14d6a242018-05-17 15:24:05 +0200152#define STM32_BSEC_OTP_OFFSET 0x80000000
Patrick Delaunay92dc1022019-02-12 11:44:41 +0100153#define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4)
Patrick Delaunayb10cddf2020-02-12 19:37:38 +0100154#define STM32_BSEC_LOCK_OFFSET 0xC0000000
155#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4)
Patrick Delaunay92dc1022019-02-12 11:44:41 +0100156
Patrick Delaunayb10cddf2020-02-12 19:37:38 +0100157/* BSEC OTP index */
Patrick Delaunay123687c2022-05-20 18:24:46 +0200158#ifdef CONFIG_STM32MP15x
Patrick Delaunayb10cddf2020-02-12 19:37:38 +0100159#define BSEC_OTP_RPN 1
160#define BSEC_OTP_SERIAL 13
161#define BSEC_OTP_PKG 16
162#define BSEC_OTP_MAC 57
Patrick Delaunay92dc1022019-02-12 11:44:41 +0100163#define BSEC_OTP_BOARD 59
Patrick Delaunay123687c2022-05-20 18:24:46 +0200164#endif
165#ifdef CONFIG_STM32MP13x
166#define BSEC_OTP_RPN 1
167#define BSEC_OTP_SERIAL 13
168#define BSEC_OTP_MAC 57
169#define BSEC_OTP_BOARD 60
170#endif
Patrick Delaunay14d6a242018-05-17 15:24:05 +0200171
Simon Glass559f1a82020-05-10 11:40:12 -0600172#endif /* __ASSEMBLY__ */
Patrick Delaunay85b53972018-03-12 10:46:10 +0100173#endif /* _MACH_STM32_H_ */