Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2005 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 3bbe70c | 2019-12-28 10:44:54 -0700 | [diff] [blame] | 8 | #include <fdt_support.h> |
Simon Glass | 8e16b1e | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 9 | #include <init.h> |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 10 | #include <ioports.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 12 | #include <mpc83xx.h> |
| 13 | #include <asm/mpc8349_pci.h> |
| 14 | #include <i2c.h> |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 15 | #include <miiphy.h> |
Peter Tyser | 133c0fe | 2010-04-12 22:28:07 -0500 | [diff] [blame] | 16 | #include <asm/mmu.h> |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 17 | #include <pci.h> |
Stefan Roese | fb9a730 | 2010-08-31 10:00:10 +0200 | [diff] [blame] | 18 | #include <flash.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 19 | #include <linux/delay.h> |
Stefan Roese | fb9a730 | 2010-08-31 10:00:10 +0200 | [diff] [blame] | 20 | #include <mtd/cfi_flash.h> |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 21 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 24 | #define IOSYNC asm("eieio") |
| 25 | #define ISYNC asm("isync") |
| 26 | #define SYNC asm("sync") |
| 27 | #define FPW FLASH_PORT_WIDTH |
| 28 | #define FPWV FLASH_PORT_WIDTHV |
| 29 | |
| 30 | #define DDR_MAX_SIZE_PER_CS 0x20000000 |
| 31 | |
| 32 | #if defined(DDR_CASLAT_20) |
| 33 | #define TIMING_CASLAT TIMING_CFG1_CASLAT_20 |
| 34 | #define MODE_CASLAT DDR_MODE_CASLAT_20 |
| 35 | #else |
| 36 | #define TIMING_CASLAT TIMING_CFG1_CASLAT_25 |
| 37 | #define MODE_CASLAT DDR_MODE_CASLAT_25 |
| 38 | #endif |
| 39 | |
| 40 | #define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \ |
| 41 | CSCONFIG_COL_BIT_9) |
| 42 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 43 | /* External definitions */ |
| 44 | ulong flash_get_size (ulong base, int banknum); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 45 | |
| 46 | /* Local functions */ |
| 47 | static int detect_num_flash_banks(void); |
Wolfgang Denk | 3da2e9f | 2011-07-30 23:50:50 +0200 | [diff] [blame] | 48 | static long int get_ddr_bank_size(short cs, long *base); |
Bin Meng | b597324 | 2016-01-25 00:29:55 -0800 | [diff] [blame] | 49 | static void set_cs_bounds(short cs, ulong base, ulong size); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 50 | static void set_cs_config(short cs, long config); |
| 51 | static void set_ddr_config(void); |
| 52 | |
| 53 | /* Local variable */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 54 | static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 55 | |
| 56 | /************************************************************************** |
| 57 | * Board initialzation after relocation to RAM. Used to detect the number |
| 58 | * of Flash banks on TQM834x. |
| 59 | */ |
| 60 | int board_early_init_r (void) { |
| 61 | /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */ |
| 62 | if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
| 63 | return 0; |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 64 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 65 | /* detect the number of Flash banks */ |
| 66 | return detect_num_flash_banks(); |
| 67 | } |
| 68 | |
| 69 | /************************************************************************** |
| 70 | * DRAM initalization and size detection |
| 71 | */ |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 72 | int dram_init(void) |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 73 | { |
| 74 | long bank_size; |
| 75 | long size; |
| 76 | int cs; |
| 77 | |
| 78 | /* during size detection, set up the max DDRLAW size */ |
Mario Six | c9f9277 | 2019-01-21 09:18:15 +0100 | [diff] [blame] | 79 | im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE; |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 80 | im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); |
| 81 | |
| 82 | /* set CS bounds to maximum size */ |
| 83 | for(cs = 0; cs < 4; ++cs) { |
| 84 | set_cs_bounds(cs, |
Mario Six | c9f9277 | 2019-01-21 09:18:15 +0100 | [diff] [blame] | 85 | CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS), |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 86 | DDR_MAX_SIZE_PER_CS); |
| 87 | |
| 88 | set_cs_config(cs, INITIAL_CS_CONFIG); |
| 89 | } |
| 90 | |
| 91 | /* configure ddr controller */ |
| 92 | set_ddr_config(); |
| 93 | |
| 94 | udelay(200); |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 95 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 96 | /* enable DDR controller */ |
| 97 | im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | |
| 98 | SDRAM_CFG_SREN | |
Kim Phillips | 3b9c20f | 2007-08-16 22:52:48 -0500 | [diff] [blame] | 99 | SDRAM_CFG_SDRAM_TYPE_DDR1); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 100 | SYNC; |
| 101 | |
| 102 | /* size detection */ |
| 103 | debug("\n"); |
| 104 | size = 0; |
| 105 | for(cs = 0; cs < 4; ++cs) { |
| 106 | debug("\nDetecting Bank%d\n", cs); |
| 107 | |
| 108 | bank_size = get_ddr_bank_size(cs, |
Mario Six | c9f9277 | 2019-01-21 09:18:15 +0100 | [diff] [blame] | 109 | (long *)(CONFIG_SYS_SDRAM_BASE + size)); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 110 | size += bank_size; |
| 111 | |
Marek Vasut | 71a14a6 | 2011-10-21 14:17:10 +0000 | [diff] [blame] | 112 | debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 113 | |
| 114 | /* exit if less than one bank */ |
| 115 | if(size < DDR_MAX_SIZE_PER_CS) break; |
| 116 | } |
| 117 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 118 | gd->ram_size = size; |
| 119 | |
| 120 | return 0; |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | /************************************************************************** |
| 124 | * checkboard() |
| 125 | */ |
| 126 | int checkboard (void) |
| 127 | { |
| 128 | puts("Board: TQM834x\n"); |
| 129 | |
| 130 | #ifdef CONFIG_PCI |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 131 | volatile immap_t * immr; |
| 132 | u32 w, f; |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 133 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | immr = (immap_t *)CONFIG_SYS_IMMR; |
Dave Liu | 0b6bc77 | 2006-12-07 21:11:58 +0800 | [diff] [blame] | 135 | if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) { |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 136 | printf("PCI: NOT in host mode..?!\n"); |
| 137 | return 0; |
| 138 | } |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 139 | |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 140 | /* get bus width */ |
| 141 | w = 32; |
Dave Liu | 0b6bc77 | 2006-12-07 21:11:58 +0800 | [diff] [blame] | 142 | if (immr->reset.rcwh & HRCWH_64_BIT_PCI) |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 143 | w = 64; |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 144 | |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 145 | /* get clock */ |
| 146 | f = gd->pci_clk; |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 147 | |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 148 | printf("PCI1: %d bit, %d MHz\n", w, f / 1000000); |
| 149 | #else |
| 150 | printf("PCI: disabled\n"); |
| 151 | #endif |
| 152 | return 0; |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 153 | } |
| 154 | |
Rafal Jaworowski | 384da5e | 2005-10-17 02:39:53 +0200 | [diff] [blame] | 155 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 156 | /************************************************************************** |
| 157 | * |
| 158 | * Local functions |
| 159 | * |
| 160 | *************************************************************************/ |
| 161 | |
| 162 | /************************************************************************** |
| 163 | * Detect the number of flash banks (1 or 2). Store it in |
| 164 | * a global variable tqm834x_num_flash_banks. |
| 165 | * Bank detection code based on the Monitor code. |
| 166 | */ |
| 167 | static int detect_num_flash_banks(void) |
| 168 | { |
| 169 | typedef unsigned long FLASH_PORT_WIDTH; |
| 170 | typedef volatile unsigned long FLASH_PORT_WIDTHV; |
| 171 | FPWV *bank1_base; |
| 172 | FPWV *bank2_base; |
| 173 | FPW bank1_read; |
| 174 | FPW bank2_read; |
| 175 | ulong bank1_size; |
| 176 | ulong bank2_size; |
| 177 | ulong total_size; |
| 178 | |
Stefan Roese | fb9a730 | 2010-08-31 10:00:10 +0200 | [diff] [blame] | 179 | cfi_flash_num_flash_banks = 2; /* assume two banks */ |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 180 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 181 | /* Get bank 1 and 2 information */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 183 | debug("Bank1 size: %lu\n", bank1_size); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 185 | debug("Bank2 size: %lu\n", bank2_size); |
| 186 | total_size = bank1_size + bank2_size; |
| 187 | |
| 188 | if (bank2_size > 0) { |
| 189 | /* Seems like we've got bank 2, but maybe it's mirrored 1 */ |
| 190 | |
| 191 | /* Set the base addresses */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE); |
| 193 | bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 194 | |
| 195 | /* Put bank 2 into CFI command mode and read */ |
| 196 | bank2_base[0x55] = 0x00980098; |
| 197 | IOSYNC; |
| 198 | ISYNC; |
| 199 | bank2_read = bank2_base[0x10]; |
| 200 | |
| 201 | /* Read from bank 1 (it's in read mode) */ |
| 202 | bank1_read = bank1_base[0x10]; |
| 203 | |
| 204 | /* Reset Flash */ |
| 205 | bank1_base[0] = 0x00F000F0; |
| 206 | bank2_base[0] = 0x00F000F0; |
| 207 | |
| 208 | if (bank2_read == bank1_read) { |
| 209 | /* |
| 210 | * Looks like just one bank, but not sure yet. Let's |
| 211 | * read from bank 2 in autosoelect mode. |
| 212 | */ |
| 213 | bank2_base[0x0555] = 0x00AA00AA; |
| 214 | bank2_base[0x02AA] = 0x00550055; |
| 215 | bank2_base[0x0555] = 0x00900090; |
| 216 | IOSYNC; |
| 217 | ISYNC; |
| 218 | bank2_read = bank2_base[0x10]; |
| 219 | |
| 220 | /* Read from bank 1 (it's in read mode) */ |
| 221 | bank1_read = bank1_base[0x10]; |
| 222 | |
| 223 | /* Reset Flash */ |
| 224 | bank1_base[0] = 0x00F000F0; |
| 225 | bank2_base[0] = 0x00F000F0; |
| 226 | |
| 227 | if (bank2_read == bank1_read) { |
| 228 | /* |
| 229 | * In both CFI command and autoselect modes, |
| 230 | * we got the some data reading from Flash. |
| 231 | * There is only one mirrored bank. |
| 232 | */ |
Stefan Roese | fb9a730 | 2010-08-31 10:00:10 +0200 | [diff] [blame] | 233 | cfi_flash_num_flash_banks = 1; |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 234 | total_size = bank1_size; |
| 235 | } |
| 236 | } |
| 237 | } |
| 238 | |
Stefan Roese | fb9a730 | 2010-08-31 10:00:10 +0200 | [diff] [blame] | 239 | debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 240 | |
| 241 | /* set OR0 and BR0 */ |
Mario Six | 560f2e9 | 2019-01-21 09:18:00 +0100 | [diff] [blame] | 242 | set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | |
| 243 | OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM)); |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 244 | set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) | |
| 245 | (BR_MS_GPCM | BR_PS_32 | BR_V)); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 246 | |
| 247 | return (0); |
| 248 | } |
| 249 | |
| 250 | /************************************************************************* |
| 251 | * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly. |
| 252 | */ |
Wolfgang Denk | 3da2e9f | 2011-07-30 23:50:50 +0200 | [diff] [blame] | 253 | static long int get_ddr_bank_size(short cs, long *base) |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 254 | { |
| 255 | /* This array lists all valid DDR SDRAM configurations, with |
| 256 | * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM). |
| 257 | * The last entry has to to have size equal 0 and is igonred during |
| 258 | * autodection. Bank sizes must be in increasing order of size |
| 259 | */ |
| 260 | struct { |
| 261 | long row; |
| 262 | long col; |
| 263 | long size; |
| 264 | } conf[] = { |
| 265 | {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20}, |
| 266 | {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20}, |
| 267 | {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20}, |
| 268 | {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20}, |
| 269 | {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20}, |
| 270 | {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20}, |
| 271 | {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20}, |
| 272 | {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20}, |
| 273 | {0, 0, 0} |
| 274 | }; |
| 275 | |
| 276 | int i; |
| 277 | int detected; |
| 278 | long size; |
| 279 | |
| 280 | detected = -1; |
| 281 | for(i = 0; conf[i].size != 0; ++i) { |
| 282 | |
| 283 | /* set sdram bank configuration */ |
| 284 | set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row); |
| 285 | |
| 286 | debug("Getting RAM size...\n"); |
| 287 | size = get_ram_size(base, DDR_MAX_SIZE_PER_CS); |
| 288 | |
| 289 | if((size == conf[i].size) && (i == detected + 1)) |
| 290 | detected = i; |
| 291 | |
| 292 | debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n", |
| 293 | conf[i].row, |
| 294 | conf[i].col, |
| 295 | conf[i].size >> 20, |
| 296 | base, |
| 297 | size >> 20); |
| 298 | } |
| 299 | |
| 300 | if(detected == -1){ |
| 301 | /* disable empty cs */ |
| 302 | debug("\nNo valid configurations for CS%d, disabling...\n", cs); |
| 303 | set_cs_config(cs, 0); |
| 304 | return 0; |
| 305 | } |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 306 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 307 | debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n", |
| 308 | conf[detected].row, conf[detected].col, conf[detected].size >> 20, base); |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 309 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 310 | /* configure cs ro detected params */ |
| 311 | set_cs_config(cs, CSCONFIG_EN | conf[detected].row | |
| 312 | conf[detected].col); |
| 313 | |
| 314 | set_cs_bounds(cs, (long)base, conf[detected].size); |
| 315 | |
| 316 | return(conf[detected].size); |
| 317 | } |
| 318 | |
| 319 | /************************************************************************** |
| 320 | * Sets DDR bank CS bounds. |
| 321 | */ |
Bin Meng | b597324 | 2016-01-25 00:29:55 -0800 | [diff] [blame] | 322 | static void set_cs_bounds(short cs, ulong base, ulong size) |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 323 | { |
Marek Vasut | 71a14a6 | 2011-10-21 14:17:10 +0000 | [diff] [blame] | 324 | debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 325 | if(size == 0){ |
| 326 | im->ddr.csbnds[cs].csbnds = 0x00000000; |
| 327 | } else { |
| 328 | im->ddr.csbnds[cs].csbnds = |
| 329 | ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | |
| 330 | (((base + size - 1) >> CSBNDS_EA_SHIFT) & |
| 331 | CSBNDS_EA); |
| 332 | } |
| 333 | SYNC; |
| 334 | } |
| 335 | |
| 336 | /************************************************************************** |
| 337 | * Sets DDR banks CS configuration. |
| 338 | * config == 0x00000000 disables the CS. |
| 339 | */ |
| 340 | static void set_cs_config(short cs, long config) |
| 341 | { |
Marek Vasut | 71a14a6 | 2011-10-21 14:17:10 +0000 | [diff] [blame] | 342 | debug("Setting config %08lx for cs %d\n", config, cs); |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 343 | im->ddr.cs_config[cs] = config; |
| 344 | SYNC; |
| 345 | } |
| 346 | |
| 347 | /************************************************************************** |
| 348 | * Sets DDR clocks, timings and configuration. |
| 349 | */ |
| 350 | static void set_ddr_config(void) { |
| 351 | /* clock control */ |
| 352 | im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN | |
| 353 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; |
| 354 | SYNC; |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 355 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 356 | /* timing configuration */ |
| 357 | im->ddr.timing_cfg_1 = |
| 358 | (4 << TIMING_CFG1_PRETOACT_SHIFT) | |
| 359 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | |
| 360 | (4 << TIMING_CFG1_ACTTORW_SHIFT) | |
| 361 | (5 << TIMING_CFG1_REFREC_SHIFT) | |
| 362 | (3 << TIMING_CFG1_WRREC_SHIFT) | |
| 363 | (3 << TIMING_CFG1_ACTTOACT_SHIFT) | |
| 364 | (1 << TIMING_CFG1_WRTORD_SHIFT) | |
| 365 | (TIMING_CFG1_CASLAT & TIMING_CASLAT); |
| 366 | |
| 367 | im->ddr.timing_cfg_2 = |
| 368 | TIMING_CFG2_CPO_DEF | |
| 369 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT); |
| 370 | SYNC; |
| 371 | |
| 372 | /* don't enable DDR controller yet */ |
| 373 | im->ddr.sdram_cfg = |
| 374 | SDRAM_CFG_SREN | |
Kim Phillips | 3b9c20f | 2007-08-16 22:52:48 -0500 | [diff] [blame] | 375 | SDRAM_CFG_SDRAM_TYPE_DDR1; |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 376 | SYNC; |
Wolfgang Denk | f6a692b | 2005-12-04 00:40:34 +0100 | [diff] [blame] | 377 | |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 378 | /* Set SDRAM mode */ |
| 379 | im->ddr.sdram_mode = |
| 380 | ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) << |
| 381 | SDRAM_MODE_ESD_SHIFT) | |
| 382 | ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) << |
| 383 | SDRAM_MODE_SD_SHIFT) | |
| 384 | ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) & |
| 385 | MODE_CASLAT); |
| 386 | SYNC; |
| 387 | |
| 388 | /* Set fast SDRAM refresh rate */ |
| 389 | im->ddr.sdram_interval = |
| 390 | (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | |
| 391 | (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); |
| 392 | SYNC; |
Wolfgang Denk | 1305bd4 | 2006-06-16 16:53:06 +0200 | [diff] [blame] | 393 | |
| 394 | /* Workaround for DDR6 Erratum |
| 395 | * see MPC8349E Device Errata Rev.8, 2/2006 |
| 396 | * This workaround influences the MPC internal "input enables" |
| 397 | * dependent on CAS latency and MPC revision. According to errata |
| 398 | * sheet the internal reserved registers for this workaround are |
| 399 | * not available from revision 2.0 and up. |
| 400 | */ |
| 401 | |
| 402 | /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0 |
| 403 | * (0x200) |
| 404 | */ |
| 405 | if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) { |
| 406 | |
| 407 | /* There is a internal reserved register at IMMRBAR+0x2F00 |
| 408 | * which has to be written with a certain value defined by |
| 409 | * errata sheet. |
| 410 | */ |
Wolfgang Denk | 31560d1 | 2006-07-21 15:24:56 +0200 | [diff] [blame] | 411 | u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00); |
| 412 | |
Wolfgang Denk | 1305bd4 | 2006-06-16 16:53:06 +0200 | [diff] [blame] | 413 | #if defined(DDR_CASLAT_20) |
Wolfgang Denk | 31560d1 | 2006-07-21 15:24:56 +0200 | [diff] [blame] | 414 | *reserved_p = 0x201c0000; |
Wolfgang Denk | 1305bd4 | 2006-06-16 16:53:06 +0200 | [diff] [blame] | 415 | #else |
Wolfgang Denk | 31560d1 | 2006-07-21 15:24:56 +0200 | [diff] [blame] | 416 | *reserved_p = 0x202c0000; |
Wolfgang Denk | 1305bd4 | 2006-06-16 16:53:06 +0200 | [diff] [blame] | 417 | #endif |
| 418 | } |
Marian Balakowicz | 513b4a1 | 2005-10-11 19:09:42 +0200 | [diff] [blame] | 419 | } |
Wolfgang Denk | 9559357 | 2009-05-14 23:18:34 +0200 | [diff] [blame] | 420 | |
| 421 | #ifdef CONFIG_OF_BOARD_SETUP |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 422 | int ft_board_setup(void *blob, struct bd_info *bd) |
Wolfgang Denk | 9559357 | 2009-05-14 23:18:34 +0200 | [diff] [blame] | 423 | { |
| 424 | ft_cpu_setup(blob, bd); |
| 425 | |
| 426 | #ifdef CONFIG_PCI |
| 427 | ft_pci_setup(blob, bd); |
| 428 | #endif /* CONFIG_PCI */ |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 429 | |
| 430 | return 0; |
Wolfgang Denk | 9559357 | 2009-05-14 23:18:34 +0200 | [diff] [blame] | 431 | } |
| 432 | #endif /* CONFIG_OF_BOARD_SETUP */ |