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git01.mediatek.com / filogic / uboot / 8062b053c8497988c4e145f9045d3465b749117c / . / arch / arm / include / asm / arch-keystone / hardware.h
blob: ffdecbfcd6d1cea690fd7e14af8521dcc093e283 [file] [log] [blame]
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400[diff] [blame]1/*
2 * Keystone2: Common SoC definitions, structures etc.
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include <config.h>
13
14#ifndef __ASSEMBLY__
15
16#include <linux/sizes.h>
17#include <asm/io.h>
18
19#define REG(addr) (*(volatile unsigned int *)(addr))
20#define REG_P(addr) ((volatile unsigned int *)(addr))
21
22typedef volatile unsigned int dv_reg;
23typedef volatile unsigned int *dv_reg_p;
24
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400[diff] [blame]25struct ddr3_phy_config {
26 unsigned int pllcr;
27 unsigned int pgcr1_mask;
28 unsigned int pgcr1_val;
29 unsigned int ptr0;
30 unsigned int ptr1;
31 unsigned int ptr2;
32 unsigned int ptr3;
33 unsigned int ptr4;
34 unsigned int dcr_mask;
35 unsigned int dcr_val;
36 unsigned int dtpr0;
37 unsigned int dtpr1;
38 unsigned int dtpr2;
39 unsigned int mr0;
40 unsigned int mr1;
41 unsigned int mr2;
42 unsigned int dtcr;
43 unsigned int pgcr2;
44 unsigned int zq0cr1;
45 unsigned int zq1cr1;
46 unsigned int zq2cr1;
47 unsigned int pir_v1;
48 unsigned int pir_v2;
49};
50
51struct ddr3_emif_config {
52 unsigned int sdcfg;
53 unsigned int sdtim1;
54 unsigned int sdtim2;
55 unsigned int sdtim3;
56 unsigned int sdtim4;
57 unsigned int zqcfg;
58 unsigned int sdrfc;
59};
60
61#endif
62
63#define BIT(x) (1 << (x))
64
65#define KS2_DDRPHY_PIR_OFFSET 0x04
66#define KS2_DDRPHY_PGCR0_OFFSET 0x08
67#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
68#define KS2_DDRPHY_PGSR0_OFFSET 0x10
69#define KS2_DDRPHY_PGSR1_OFFSET 0x14
70#define KS2_DDRPHY_PLLCR_OFFSET 0x18
71#define KS2_DDRPHY_PTR0_OFFSET 0x1C
72#define KS2_DDRPHY_PTR1_OFFSET 0x20
73#define KS2_DDRPHY_PTR2_OFFSET 0x24
74#define KS2_DDRPHY_PTR3_OFFSET 0x28
75#define KS2_DDRPHY_PTR4_OFFSET 0x2C
76#define KS2_DDRPHY_DCR_OFFSET 0x44
77
78#define KS2_DDRPHY_DTPR0_OFFSET 0x48
79#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
80#define KS2_DDRPHY_DTPR2_OFFSET 0x50
81
82#define KS2_DDRPHY_MR0_OFFSET 0x54
83#define KS2_DDRPHY_MR1_OFFSET 0x58
84#define KS2_DDRPHY_MR2_OFFSET 0x5C
85#define KS2_DDRPHY_DTCR_OFFSET 0x68
86#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
87
88#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
89#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
90#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
91#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
92
93#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
94
95#define IODDRM_MASK 0x00000180
96#define ZCKSEL_MASK 0x01800000
97#define CL_MASK 0x00000072
98#define WR_MASK 0x00000E00
99#define BL_MASK 0x00000003
100#define RRMODE_MASK 0x00040000
101#define UDIMM_MASK 0x20000000
102#define BYTEMASK_MASK 0x0003FC00
103#define MPRDQ_MASK 0x00000080
104#define PDQ_MASK 0x00000070
105#define NOSRA_MASK 0x08000000
106#define ECC_MASK 0x00000001
107
108#define KS2_DDR3_MIDR_OFFSET 0x00
109#define KS2_DDR3_STATUS_OFFSET 0x04
110#define KS2_DDR3_SDCFG_OFFSET 0x08
111#define KS2_DDR3_SDRFC_OFFSET 0x10
112#define KS2_DDR3_SDTIM1_OFFSET 0x18
113#define KS2_DDR3_SDTIM2_OFFSET 0x1C
114#define KS2_DDR3_SDTIM3_OFFSET 0x20
115#define KS2_DDR3_SDTIM4_OFFSET 0x28
116#define KS2_DDR3_PMCTL_OFFSET 0x38
117#define KS2_DDR3_ZQCFG_OFFSET 0xC8
118
Murali Karicherif90901c2014-05-29 18:57:12 +0300[diff] [blame]119#define KS2_UART0_BASE 0x02530c00
120#define KS2_UART1_BASE 0x02531000
121
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +0300[diff] [blame^]122/* AEMIF */
123#define KS2_AEMIF_CNTRL_BASE 0x21000a00
124#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
125
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400[diff] [blame]126#ifdef CONFIG_SOC_K2HK
127#include <asm/arch/hardware-k2hk.h>
128#endif
129
130#ifndef __ASSEMBLY__
131static inline int cpu_is_k2hk(void)
132{
133 unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
134 unsigned int part_no = (jtag_id >> 12) & 0xffff;
135
136 return (part_no == 0xb981) ? 1 : 0;
137}
138
139static inline int cpu_revision(void)
140{
141 unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
142 unsigned int rev = (jtag_id >> 28) & 0xf;
143
144 return rev;
145}
146
147void share_all_segments(int priv_id);
148int cpu_to_bus(u32 *ptr, u32 length);
149void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
150void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
151void init_ddr3(void);
152void sdelay(unsigned long);
153
154#endif
155
156#endif /* __ASM_ARCH_HARDWARE_H */