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git01.mediatek.com / filogic / uboot / 7bcf4d664c762f95405aabe682b82ebd12acd787 / . / arch / arm / include / asm / arch-keystone / hardware.h
blob: a305a0cc098b678ded90c61515be4a08b3a93500 [file] [log] [blame]
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400[diff] [blame^]1/*
2 * Keystone2: Common SoC definitions, structures etc.
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include <config.h>
13
14#ifndef __ASSEMBLY__
15
16#include <linux/sizes.h>
17#include <asm/io.h>
18
19#define REG(addr) (*(volatile unsigned int *)(addr))
20#define REG_P(addr) ((volatile unsigned int *)(addr))
21
22typedef volatile unsigned int dv_reg;
23typedef volatile unsigned int *dv_reg_p;
24
25#define ASYNC_EMIF_NUM_CS 4
26#define ASYNC_EMIF_MODE_NOR 0
27#define ASYNC_EMIF_MODE_NAND 1
28#define ASYNC_EMIF_MODE_ONENAND 2
29#define ASYNC_EMIF_PRESERVE -1
30
31struct async_emif_config {
32 unsigned mode;
33 unsigned select_strobe;
34 unsigned extend_wait;
35 unsigned wr_setup;
36 unsigned wr_strobe;
37 unsigned wr_hold;
38 unsigned rd_setup;
39 unsigned rd_strobe;
40 unsigned rd_hold;
41 unsigned turn_around;
42 enum {
43 ASYNC_EMIF_8 = 0,
44 ASYNC_EMIF_16 = 1,
45 ASYNC_EMIF_32 = 2,
46 } width;
47};
48
49void init_async_emif(int num_cs, struct async_emif_config *config);
50
51struct ddr3_phy_config {
52 unsigned int pllcr;
53 unsigned int pgcr1_mask;
54 unsigned int pgcr1_val;
55 unsigned int ptr0;
56 unsigned int ptr1;
57 unsigned int ptr2;
58 unsigned int ptr3;
59 unsigned int ptr4;
60 unsigned int dcr_mask;
61 unsigned int dcr_val;
62 unsigned int dtpr0;
63 unsigned int dtpr1;
64 unsigned int dtpr2;
65 unsigned int mr0;
66 unsigned int mr1;
67 unsigned int mr2;
68 unsigned int dtcr;
69 unsigned int pgcr2;
70 unsigned int zq0cr1;
71 unsigned int zq1cr1;
72 unsigned int zq2cr1;
73 unsigned int pir_v1;
74 unsigned int pir_v2;
75};
76
77struct ddr3_emif_config {
78 unsigned int sdcfg;
79 unsigned int sdtim1;
80 unsigned int sdtim2;
81 unsigned int sdtim3;
82 unsigned int sdtim4;
83 unsigned int zqcfg;
84 unsigned int sdrfc;
85};
86
87#endif
88
89#define BIT(x) (1 << (x))
90
91#define KS2_DDRPHY_PIR_OFFSET 0x04
92#define KS2_DDRPHY_PGCR0_OFFSET 0x08
93#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
94#define KS2_DDRPHY_PGSR0_OFFSET 0x10
95#define KS2_DDRPHY_PGSR1_OFFSET 0x14
96#define KS2_DDRPHY_PLLCR_OFFSET 0x18
97#define KS2_DDRPHY_PTR0_OFFSET 0x1C
98#define KS2_DDRPHY_PTR1_OFFSET 0x20
99#define KS2_DDRPHY_PTR2_OFFSET 0x24
100#define KS2_DDRPHY_PTR3_OFFSET 0x28
101#define KS2_DDRPHY_PTR4_OFFSET 0x2C
102#define KS2_DDRPHY_DCR_OFFSET 0x44
103
104#define KS2_DDRPHY_DTPR0_OFFSET 0x48
105#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
106#define KS2_DDRPHY_DTPR2_OFFSET 0x50
107
108#define KS2_DDRPHY_MR0_OFFSET 0x54
109#define KS2_DDRPHY_MR1_OFFSET 0x58
110#define KS2_DDRPHY_MR2_OFFSET 0x5C
111#define KS2_DDRPHY_DTCR_OFFSET 0x68
112#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
113
114#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
115#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
116#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
117#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
118
119#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
120
121#define IODDRM_MASK 0x00000180
122#define ZCKSEL_MASK 0x01800000
123#define CL_MASK 0x00000072
124#define WR_MASK 0x00000E00
125#define BL_MASK 0x00000003
126#define RRMODE_MASK 0x00040000
127#define UDIMM_MASK 0x20000000
128#define BYTEMASK_MASK 0x0003FC00
129#define MPRDQ_MASK 0x00000080
130#define PDQ_MASK 0x00000070
131#define NOSRA_MASK 0x08000000
132#define ECC_MASK 0x00000001
133
134#define KS2_DDR3_MIDR_OFFSET 0x00
135#define KS2_DDR3_STATUS_OFFSET 0x04
136#define KS2_DDR3_SDCFG_OFFSET 0x08
137#define KS2_DDR3_SDRFC_OFFSET 0x10
138#define KS2_DDR3_SDTIM1_OFFSET 0x18
139#define KS2_DDR3_SDTIM2_OFFSET 0x1C
140#define KS2_DDR3_SDTIM3_OFFSET 0x20
141#define KS2_DDR3_SDTIM4_OFFSET 0x28
142#define KS2_DDR3_PMCTL_OFFSET 0x38
143#define KS2_DDR3_ZQCFG_OFFSET 0xC8
144
145#ifdef CONFIG_SOC_K2HK
146#include <asm/arch/hardware-k2hk.h>
147#endif
148
149#ifndef __ASSEMBLY__
150static inline int cpu_is_k2hk(void)
151{
152 unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
153 unsigned int part_no = (jtag_id >> 12) & 0xffff;
154
155 return (part_no == 0xb981) ? 1 : 0;
156}
157
158static inline int cpu_revision(void)
159{
160 unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
161 unsigned int rev = (jtag_id >> 28) & 0xf;
162
163 return rev;
164}
165
166void share_all_segments(int priv_id);
167int cpu_to_bus(u32 *ptr, u32 length);
168void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
169void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
170void init_ddr3(void);
171void sdelay(unsigned long);
172
173#endif
174
175#endif /* __ASM_ARCH_HARDWARE_H */