Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | /* |
| 3 | * Copyright (C) 2019 Marek Vasut <marex@denx.de> |
| 4 | */ |
| 5 | |
| 6 | #include <dt-bindings/clock/stm32mp1-clksrc.h> |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 7 | #include "stm32mp15-u-boot.dtsi" |
Marek Vasut | 272198e | 2020-04-29 15:08:38 +0200 | [diff] [blame] | 8 | #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi" |
| 9 | #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi" |
| 10 | #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" |
Marek Vasut | 0171144 | 2024-10-05 03:15:50 +0200 | [diff] [blame] | 11 | #include "stm32mp15xx-dhsom-u-boot.dtsi" |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 12 | |
| 13 | / { |
| 14 | aliases { |
Marek Vasut | b83fd66 | 2024-10-21 22:00:21 +0200 | [diff] [blame] | 15 | eeprom0 = &eeprom0; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 16 | i2c1 = &i2c2; |
| 17 | i2c3 = &i2c4; |
| 18 | i2c4 = &i2c5; |
| 19 | mmc0 = &sdmmc1; |
| 20 | mmc1 = &sdmmc2; |
| 21 | spi0 = &qspi; |
| 22 | usb0 = &usbotg_hs; |
| 23 | }; |
| 24 | |
| 25 | config { |
Marek Vasut | 39221b5 | 2020-04-22 13:18:14 +0200 | [diff] [blame] | 26 | dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; |
Marek Vasut | 3551654 | 2024-06-06 15:01:48 +0200 | [diff] [blame] | 27 | dh,mac-coding-gpios = <&gpioc 3 0>; |
Marek Vasut | b83fd66 | 2024-10-21 22:00:21 +0200 | [diff] [blame] | 28 | dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>; |
| 29 | u-boot,boot-led = "heartbeat"; |
| 30 | u-boot,error-led = "error"; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 31 | }; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 32 | }; |
| 33 | |
Marek Vasut | 7d2757f | 2021-12-30 23:46:47 +0100 | [diff] [blame] | 34 | ðernet0 { |
| 35 | phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; |
| 36 | /delete-property/ st,eth-ref-clk-sel; |
| 37 | }; |
| 38 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 39 | &i2c4 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 40 | bootph-all; |
| 41 | bootph-pre-ram; |
Marek Vasut | 7d2757f | 2021-12-30 23:46:47 +0100 | [diff] [blame] | 42 | |
| 43 | eeprom0: eeprom@50 { |
| 44 | }; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 45 | }; |
| 46 | |
| 47 | &i2c4_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 48 | bootph-all; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 49 | pins { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 50 | bootph-all; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 51 | }; |
| 52 | }; |
| 53 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 54 | &flash0 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 55 | bootph-pre-ram; |
Patrick Delaunay | f172bcb | 2023-06-08 17:16:48 +0200 | [diff] [blame] | 56 | |
| 57 | partitions { |
| 58 | compatible = "fixed-partitions"; |
| 59 | #address-cells = <1>; |
| 60 | #size-cells = <1>; |
| 61 | |
| 62 | partition@0 { |
| 63 | label = "fsbl1"; |
| 64 | reg = <0x00000000 0x00040000>; |
| 65 | }; |
| 66 | partition@40000 { |
| 67 | label = "fsbl2"; |
| 68 | reg = <0x00040000 0x00040000>; |
| 69 | }; |
Patrice Chotard | 29c1e7b | 2024-03-08 14:50:09 +0100 | [diff] [blame] | 70 | partition@80000 { |
Patrick Delaunay | f172bcb | 2023-06-08 17:16:48 +0200 | [diff] [blame] | 71 | label = "uboot"; |
| 72 | reg = <0x00080000 0x00160000>; |
| 73 | }; |
Patrice Chotard | 29c1e7b | 2024-03-08 14:50:09 +0100 | [diff] [blame] | 74 | partition@1e0000 { |
Patrick Delaunay | f172bcb | 2023-06-08 17:16:48 +0200 | [diff] [blame] | 75 | label = "env1"; |
| 76 | reg = <0x001E0000 0x00010000>; |
| 77 | }; |
Patrice Chotard | 29c1e7b | 2024-03-08 14:50:09 +0100 | [diff] [blame] | 78 | partition@1f0000 { |
Patrick Delaunay | f172bcb | 2023-06-08 17:16:48 +0200 | [diff] [blame] | 79 | label = "env2"; |
| 80 | reg = <0x001F0000 0x00010000>; |
| 81 | }; |
| 82 | }; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 83 | }; |
| 84 | |
Marek Vasut | b83fd66 | 2024-10-21 22:00:21 +0200 | [diff] [blame] | 85 | &phy0 { |
| 86 | /delete-property/ reset-gpios; |
| 87 | }; |
| 88 | |
| 89 | &pmic { |
| 90 | bootph-all; |
| 91 | bootph-pre-ram; |
| 92 | |
| 93 | regulators { |
| 94 | bootph-pre-ram; |
| 95 | }; |
| 96 | }; |
| 97 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 98 | &qspi { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 99 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | &qspi_clk_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 103 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 104 | pins { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 105 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 106 | }; |
| 107 | }; |
| 108 | |
| 109 | &qspi_bk1_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 110 | bootph-pre-ram; |
Marek Vasut | 3f3375c | 2023-10-10 01:15:51 +0200 | [diff] [blame] | 111 | pins { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 112 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 113 | }; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 114 | }; |
| 115 | |
Marek Vasut | 3f3375c | 2023-10-10 01:15:51 +0200 | [diff] [blame] | 116 | &qspi_cs1_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 117 | bootph-pre-ram; |
Marek Vasut | 3f3375c | 2023-10-10 01:15:51 +0200 | [diff] [blame] | 118 | pins { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 119 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 120 | }; |
| 121 | }; |
| 122 | |
| 123 | &rcc { |
Marek Vasut | b30b159 | 2023-07-27 01:58:07 +0200 | [diff] [blame] | 124 | /* |
| 125 | * Reinstate clock names from stm32mp151.dtsi, the MCO2 trick |
| 126 | * used in stm32mp15xx-dhcom-som.dtsi is not supported by the |
| 127 | * U-Boot clock framework. |
| 128 | */ |
| 129 | clock-names = "hse", "hsi", "csi", "lse", "lsi"; |
| 130 | clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, |
| 131 | <&clk_lse>, <&clk_lsi>; |
| 132 | |
| 133 | /* The MCO2 is already configured correctly, remove those. */ |
| 134 | /delete-property/ assigned-clocks; |
| 135 | /delete-property/ assigned-clock-parents; |
| 136 | /delete-property/ assigned-clock-rates; |
| 137 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 138 | st,clksrc = < |
| 139 | CLK_MPU_PLL1P |
| 140 | CLK_AXI_PLL2P |
| 141 | CLK_MCU_PLL3P |
| 142 | CLK_PLL12_HSE |
| 143 | CLK_PLL3_HSE |
| 144 | CLK_PLL4_HSE |
| 145 | CLK_RTC_LSE |
| 146 | CLK_MCO1_DISABLED |
Marek Vasut | ccfcde3 | 2020-12-01 11:34:48 +0100 | [diff] [blame] | 147 | CLK_MCO2_PLL4P |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 148 | >; |
| 149 | |
| 150 | st,clkdiv = < |
| 151 | 1 /*MPU*/ |
| 152 | 0 /*AXI*/ |
| 153 | 0 /*MCU*/ |
| 154 | 1 /*APB1*/ |
| 155 | 1 /*APB2*/ |
| 156 | 1 /*APB3*/ |
| 157 | 1 /*APB4*/ |
| 158 | 2 /*APB5*/ |
| 159 | 23 /*RTC*/ |
| 160 | 0 /*MCO1*/ |
Marek Vasut | ccfcde3 | 2020-12-01 11:34:48 +0100 | [diff] [blame] | 161 | 1 /*MCO2*/ |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 162 | >; |
| 163 | |
| 164 | st,pkcs = < |
| 165 | CLK_CKPER_HSE |
| 166 | CLK_FMC_ACLK |
| 167 | CLK_QSPI_ACLK |
| 168 | CLK_ETH_PLL4P |
| 169 | CLK_SDMMC12_PLL4P |
| 170 | CLK_DSI_DSIPLL |
| 171 | CLK_STGEN_HSE |
| 172 | CLK_USBPHY_HSE |
| 173 | CLK_SPI2S1_PLL3Q |
| 174 | CLK_SPI2S23_PLL3Q |
| 175 | CLK_SPI45_HSI |
| 176 | CLK_SPI6_HSI |
| 177 | CLK_I2C46_HSI |
| 178 | CLK_SDMMC3_PLL4P |
| 179 | CLK_USBO_USBPHY |
| 180 | CLK_ADC_CKPER |
| 181 | CLK_CEC_LSE |
| 182 | CLK_I2C12_HSI |
| 183 | CLK_I2C35_HSI |
| 184 | CLK_UART1_HSI |
| 185 | CLK_UART24_HSI |
| 186 | CLK_UART35_HSI |
| 187 | CLK_UART6_HSI |
| 188 | CLK_UART78_HSI |
| 189 | CLK_SPDIF_PLL4P |
Antonio Borneo | 84159e8 | 2020-01-28 10:11:01 +0100 | [diff] [blame] | 190 | CLK_FDCAN_PLL4R |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 191 | CLK_SAI1_PLL3Q |
| 192 | CLK_SAI2_PLL3Q |
| 193 | CLK_SAI3_PLL3Q |
| 194 | CLK_SAI4_PLL3Q |
| 195 | CLK_RNG1_LSI |
| 196 | CLK_RNG2_LSI |
| 197 | CLK_LPTIM1_PCLK1 |
| 198 | CLK_LPTIM23_PCLK3 |
| 199 | CLK_LPTIM45_LSE |
| 200 | >; |
| 201 | |
Marek Vasut | 086fa93 | 2022-10-11 22:42:44 +0200 | [diff] [blame] | 202 | /* |
| 203 | * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; |
| 204 | * frac = < f >; |
| 205 | * |
| 206 | * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled |
| 207 | * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN |
| 208 | * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 |
| 209 | * XTAL = 24 MHz |
| 210 | * |
| 211 | * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) |
| 212 | * P = VCO / (P + 1) |
| 213 | * Q = VCO / (Q + 1) |
| 214 | * R = VCO / (R + 1) |
| 215 | */ |
| 216 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 217 | /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ |
| 218 | pll2: st,pll@1 { |
Patrick Delaunay | c22caac | 2020-01-28 10:11:03 +0100 | [diff] [blame] | 219 | compatible = "st,stm32mp1-pll"; |
| 220 | reg = <1>; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 221 | cfg = < 2 65 1 0 0 PQR(1,1,1) >; |
| 222 | frac = < 0x1400 >; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 223 | bootph-all; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 224 | }; |
| 225 | |
| 226 | /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ |
| 227 | pll3: st,pll@2 { |
Patrick Delaunay | c22caac | 2020-01-28 10:11:03 +0100 | [diff] [blame] | 228 | compatible = "st,stm32mp1-pll"; |
| 229 | reg = <2>; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 230 | cfg = < 1 33 1 16 36 PQR(1,1,1) >; |
| 231 | frac = < 0x1a04 >; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 232 | bootph-all; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 233 | }; |
| 234 | |
Marek Vasut | 086fa93 | 2022-10-11 22:42:44 +0200 | [diff] [blame] | 235 | /* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */ |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 236 | pll4: st,pll@3 { |
Patrick Delaunay | c22caac | 2020-01-28 10:11:03 +0100 | [diff] [blame] | 237 | compatible = "st,stm32mp1-pll"; |
| 238 | reg = <3>; |
Marek Vasut | ccfcde3 | 2020-12-01 11:34:48 +0100 | [diff] [blame] | 239 | cfg = < 1 49 5 11 11 PQR(1,1,1) >; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 240 | bootph-all; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 241 | }; |
| 242 | }; |
| 243 | |
Marek Vasut | b83fd66 | 2024-10-21 22:00:21 +0200 | [diff] [blame] | 244 | ®11 { |
| 245 | bootph-pre-ram; |
| 246 | }; |
| 247 | |
| 248 | ®18 { |
| 249 | bootph-pre-ram; |
| 250 | }; |
| 251 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 252 | &sdmmc1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 253 | bootph-pre-ram; |
Marek Vasut | 5f5ce60 | 2021-11-13 03:29:44 +0100 | [diff] [blame] | 254 | st,use-ckin; |
| 255 | st,cmd-gpios = <&gpiod 2 0>; |
| 256 | st,ck-gpios = <&gpioc 12 0>; |
| 257 | st,ckin-gpios = <&gpioe 4 0>; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 258 | }; |
| 259 | |
| 260 | &sdmmc1_b4_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 261 | bootph-pre-ram; |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 262 | pins1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 263 | bootph-pre-ram; |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 264 | }; |
| 265 | pins2 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 266 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 267 | }; |
| 268 | }; |
| 269 | |
| 270 | &sdmmc1_dir_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 271 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 272 | pins1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 273 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 274 | }; |
| 275 | pins2 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 276 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 277 | }; |
| 278 | }; |
| 279 | |
| 280 | &sdmmc2 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 281 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 282 | }; |
| 283 | |
| 284 | &sdmmc2_b4_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 285 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 286 | pins { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 287 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 288 | }; |
| 289 | }; |
| 290 | |
| 291 | &sdmmc2_d47_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 292 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 293 | pins { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 294 | bootph-pre-ram; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 295 | }; |
| 296 | }; |
| 297 | |
| 298 | &uart4 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 299 | bootph-all; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 300 | }; |
| 301 | |
| 302 | &uart4_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 303 | bootph-all; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 304 | pins1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 305 | bootph-all; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 306 | }; |
| 307 | pins2 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 308 | bootph-all; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 309 | /* pull-up on rx to avoid floating level */ |
| 310 | bias-pull-up; |
| 311 | }; |
| 312 | }; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 313 | |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 314 | &usb33 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 315 | bootph-pre-ram; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 316 | }; |
| 317 | |
| 318 | &usbotg_hs_pins_a { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 319 | bootph-pre-ram; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 320 | }; |
| 321 | |
| 322 | &usbotg_hs { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 323 | bootph-pre-ram; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 324 | }; |
| 325 | |
| 326 | &usbphyc { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 327 | bootph-pre-ram; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | &usbphyc_port0 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 331 | bootph-pre-ram; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 332 | }; |
| 333 | |
| 334 | &usbphyc_port1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 335 | bootph-pre-ram; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 336 | }; |
| 337 | |
| 338 | &vdd_usb { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 339 | bootph-pre-ram; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 340 | }; |