commit 7d2757f71e9420b3398a0e9bc3a907b6440e5e65
author Marek Vasut <marex@denx.de> Thu Dec 30 23:46:47 2021 +0100
committer Patrice Chotard <patrice.chotard@foss.st.com> Mon Jan 24 10:57:56 2022 +0100
tree 8713e760cf0312adeb770b69599f5f0fa95f9c8b
parent 8b08dfbe3197d274024dae3853e5f2c035cd4795

ARM: dts: stm32: Synchronize DHCOM DTs with Linux 5.15.12

Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The eeprom0 alias and
PHY reset GPIO are now reinstated in SoM u-boot dtsi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 5b2b09b..f09f429 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -9,6 +9,8 @@
 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
 
+/delete-node/ &ksz8851;
+
 / {
 	aliases {
 		i2c1 = &i2c2;
@@ -18,7 +20,8 @@
 		mmc1 = &sdmmc2;
 		spi0 = &qspi;
 		usb0 = &usbotg_hs;
-		ethernet1 = &ksz8851;
+		eeprom0 = &eeprom0;
+		ethernet1 = &ks8851;
 	};
 
 	config {
@@ -30,28 +33,34 @@
 		dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
 	};
 
-	led {
-		red {
-			label = "error";
-			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-			status = "okay";
-		};
-
-		blue {
-			default-state = "on";
-		};
-	};
-
 	/* This is actually on FMC2, but we do not have bus driver for that */
-	ksz8851: ks8851mll@64000000 {
+	ks8851: ks8851mll@64000000 {
 		compatible = "micrel,ks8851-mll";
 		reg = <0x64000000 0x20000>;
 	};
 };
 
+&ethernet0 {
+	phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+	/delete-property/ st,eth-ref-clk-sel;
+};
+
+&ethernet0_rmii_pins_a {
+	pins1 {
+		pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
+			 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
+			 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
+			 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK */
+			 <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */
+			 <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */
+	};
+};
+
 &i2c4 {
 	u-boot,dm-pre-reloc;
+
+	eeprom0: eeprom@50 {
+	};
 };
 
 &i2c4_pins_a {
@@ -61,6 +70,10 @@
 	};
 };
 
+&phy0 {
+	/delete-property/ reset-gpios;
+};
+
 &pinctrl {
 	/* These should bound to FMC2 bus driver, but we do not have one */
 	pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;