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git01.mediatek.com / filogic / uboot / 7f2cba463fc4488a3c24b422076683b0f6945177 / . / arch / arm / dts / stm32mp13-u-boot.dtsi
blob: 726cd1a7e479fefb29a2f1a78eec7b50d9c24ab4 [file] [log] [blame]
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
4 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 pinctrl0 = &pinctrl;
18 };
19
Patrick Delaunay75785d42022-09-07 13:42:23 +0200[diff] [blame]20 firmware {
21 optee {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-all;
Patrick Delaunay75785d42022-09-07 13:42:23 +0200[diff] [blame]23 };
24 };
25
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]26 /* need PSCI for sysreset during board_f */
27 psci {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-some-ram;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]29 };
30
31 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]33
34 ddr: ddr@5a003000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]36
37 compatible = "st,stm32mp13-ddr";
38
39 reg = <0x5A003000 0x550
40 0x5A004000 0x234>;
41
42 status = "okay";
43 };
44 };
45};
46
47&bsec {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]49};
50
51&gpioa {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]53};
54
55&gpiob {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]57};
58
59&gpioc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]61};
62
63&gpiod {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]65};
66
67&gpioe {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]69};
70
71&gpiof {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]73};
74
75&gpiog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]77};
78
79&gpioh {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]81};
82
83&gpioi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]85};
86
87&iwdg2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]89};
90
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]91&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]93};
94
Gabriel Fernandez80998802022-11-24 11:36:05 +0100[diff] [blame]95&rcc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-all;
Gabriel Fernandez80998802022-11-24 11:36:05 +0100[diff] [blame]97};
98
Patrick Delaunayad09d082022-07-06 18:20:25 +0200[diff] [blame]99&scmi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-all;
Patrick Delaunayad09d082022-07-06 18:20:25 +0200[diff] [blame]101};
102
103&scmi_clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-all;
Patrick Delaunayad09d082022-07-06 18:20:25 +0200[diff] [blame]105};
106
107&scmi_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-all;
Patrick Delaunayad09d082022-07-06 18:20:25 +0200[diff] [blame]109};
110
111&scmi_shm {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-all;
Patrick Delaunayad09d082022-07-06 18:20:25 +0200[diff] [blame]113};
114
115&scmi_sram {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-all;
Patrick Delaunayad09d082022-07-06 18:20:25 +0200[diff] [blame]117};
118
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]119&syscfg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-all;
Patrick Delaunaye063f892022-05-20 18:24:52 +0200[diff] [blame]121};