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git01.mediatek.com / filogic / uboot / 7f19c3bbe9e72bbafc4b2243484145998dc4462a / . / configs / ls1012afrwy_qspi_SECURE_BOOT_defconfig
blob: fe0c894c3c972b2fe8fa981aeec7483c223930bf [file] [log] [blame]
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]1CONFIG_ARM=y
2CONFIG_TARGET_LS1012AFRWY=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x40100000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]4CONFIG_SYS_MALLOC_LEN=0x500000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]5CONFIG_NR_DRAM_BANKS=2
Ashish Kumar17f36a22020-04-29 17:42:03 +0530[diff] [blame]6CONFIG_ENV_SIZE=0x2000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]7CONFIG_NXP_ESBC=y
Tom Rini6bd3b142020-02-06 13:42:52 -0500[diff] [blame]8CONFIG_DM_GPIO=y
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]10CONFIG_FSL_LS_PPA=y
Peng Ma9d75b2d2019-01-30 19:18:43 +0800[diff] [blame]11CONFIG_AHCI=y
Tom Rini76fbc6f2022-04-01 10:33:18 -0400[diff] [blame]12CONFIG_SYS_MEMTEST_START=0x80000000
13CONFIG_SYS_MEMTEST_END=0x9fffffff
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]14CONFIG_DISTRO_DEFAULTS=y
15# CONFIG_SYS_MALLOC_F is not set
16CONFIG_FIT_VERBOSE=y
17CONFIG_OF_BOARD_SETUP=y
18CONFIG_OF_STDOUT_VIA_ALIAS=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]19CONFIG_QSPI_BOOT=y
20CONFIG_BOOTDELAY=10
21CONFIG_USE_BOOTARGS=y
22CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]23CONFIG_BOOTCOMMAND="run distro_bootcmd; run sd_bootcmd; env exists secureboot && esbc_halt;"
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]24# CONFIG_DISPLAY_BOARDINFO is not set
25CONFIG_DISPLAY_BOARDINFO_LATE=y
26CONFIG_CMD_GREPENV=y
Tom Rini32c75d62020-05-26 15:06:18 -0400[diff] [blame]27CONFIG_CMD_MEMINFO=y
Michal Simeka9565e92020-05-04 15:26:20 +0200[diff] [blame]28CONFIG_CMD_MEMTEST=y
Biwen Li52d74352021-02-05 19:02:04 +0800[diff] [blame]29CONFIG_CMD_GPIO=y
Tom Rini3c0d7a22021-02-15 13:34:30 -0500[diff] [blame]30CONFIG_CMD_GPT=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]31CONFIG_CMD_I2C=y
32CONFIG_CMD_MMC=y
33CONFIG_CMD_PCI=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]34CONFIG_CMD_USB=y
35CONFIG_CMD_CACHE=y
36CONFIG_OF_CONTROL=y
Kuldeep Singh248a2932020-07-30 15:38:07 +0530[diff] [blame]37CONFIG_ENV_OVERWRITE=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]38CONFIG_NET_RANDOM_ETHADDR=y
39CONFIG_DM=y
Simon Glass701ef062022-01-31 07:49:33 -0700[diff] [blame]40CONFIG_SATA=y
Peng Ma9d75b2d2019-01-30 19:18:43 +0800[diff] [blame]41CONFIG_SATA_CEVA=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]42CONFIG_MPC8XXX_GPIO=y
Tom Rini6bd3b142020-02-06 13:42:52 -0500[diff] [blame]43CONFIG_DM_I2C=y
Tom Rinib1b13072021-08-18 23:12:37 -0400[diff] [blame]44CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
Yangbo Luadb19e12019-06-21 11:42:26 +0800[diff] [blame]45CONFIG_FSL_ESDHC=y
Miquel Raynal803baa22019-10-03 19:50:08 +0200[diff] [blame]46CONFIG_MTD=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]47CONFIG_DM_SPI_FLASH=y
Ashish Kumar820fa952019-05-31 16:03:28 +0530[diff] [blame]48# CONFIG_SPI_FLASH_BAR is not set
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]49CONFIG_SPI_FLASH_WINBOND=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]50CONFIG_FSL_PFE=y
Tom Riniecbc80e2018-07-09 15:13:08 -0400[diff] [blame]51CONFIG_DM_ETH=y
52CONFIG_E1000=y
Mark Kettenisf8463d62022-01-22 20:38:11 +0100[diff] [blame]53CONFIG_NVME_PCI=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]54CONFIG_PCI=y
Hou Zhiqiang02f1f062020-07-09 23:31:42 +0800[diff] [blame]55CONFIG_PCIE_LAYERSCAPE_RC=y
Tom Rini6bd3b142020-02-06 13:42:52 -0500[diff] [blame]56CONFIG_DM_RTC=y
Peng Ma9d75b2d2019-01-30 19:18:43 +0800[diff] [blame]57CONFIG_DM_SCSI=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]58CONFIG_SYS_NS16550=y
Tom Riniac3de902018-10-02 13:02:22 -0400[diff] [blame]59CONFIG_SPI=y
60CONFIG_DM_SPI=y
Ashish Kumar820fa952019-05-31 16:03:28 +0530[diff] [blame]61CONFIG_FSL_QSPI=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]62CONFIG_USB=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]63CONFIG_USB_XHCI_HCD=y
64CONFIG_USB_XHCI_DWC3=y
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530[diff] [blame]65CONFIG_RSA=y
66CONFIG_RSA_SOFTWARE_EXP=y