arch/arm/dts/am335x-phycore-som.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Phytec Messtechnik GmbH
 * Author: Teresa Remmet <t.remmet@phytec.de>
 */

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "Phytec AM335x phyCORE";
	compatible = "phytec,am335x-phycore-som", "ti,am33xx";

	aliases {
		rtc0 = &i2c_rtc;
		rtc1 = &rtc;
	};

	cpus {
		cpu@0 {
			cpu0-supply = <&vdd1_reg>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256 MB */
	};

	regulators {
		compatible = "simple-bus";

		vcc5v: fixedregulator0 {
			compatible = "regulator-fixed";
			regulator-name = "vcc5v";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			regulator-boot-on;
			regulator-always-on;
		};
	};
};

/* Crypto Module */
&aes {
	status = "okay";
};

&sham {
	status = "okay";
};

/* Ethernet */
&am33xx_pinmux {
	ethernet0_pins: pinmux_ethernet0 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
		>;
	};

	mdio_pins: pinmux_mdio {
		pinctrl-single,pins = <
			/* MDIO */
			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
		>;
	};
};

&cpsw_emac0 {
	phy-handle = <&phy0>;
	phy-mode = "rmii";
	dual_emac_res_vlan = <1>;
};

&davinci_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&mac {
	slaves = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&ethernet0_pins>;
	status = "okay";
};

/* I2C Busses */
&am33xx_pinmux {
	i2c0_pins: pinmux_i2c0 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
		>;
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	clock-frequency = <400000>;
	status = "okay";

	tps: pmic@2d {
		reg = <0x2d>;
	};

	i2c_tmp102: temp@4b {
		compatible = "ti,tmp102";
		reg = <0x4b>;
		status = "disabled";
	};

	i2c_eeprom: eeprom@52 {
		compatible = "atmel,24c32";
		pagesize = <32>;
		reg = <0x52>;
		status = "disabled";
	};

	i2c_rtc: rtc@68 {
		compatible = "microcrystal,rv4162";
		reg = <0x68>;
		status = "disabled";
	};
};

/* NAND memory */
&am33xx_pinmux {
		nandflash_pins: pinmux_nandflash {
			pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
		>;
	};
};

&elm {
	status = "okay";
};

&gpmc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nandflash_pins>;
	ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
	nandflash: nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
		nand-bus-width = <8>;
		ti,nand-ecc-opt = "bch8";
		gpmc,device-nand = "true";
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <30>;
		gpmc,cs-wr-off-ns = <30>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <30>;
		gpmc,adv-wr-off-ns = <30>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <20>;
		gpmc,oe-on-ns = <10>;
		gpmc,oe-off-ns = <30>;
		gpmc,access-ns = <30>;
		gpmc,rd-cycle-ns = <30>;
		gpmc,wr-cycle-ns = <30>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <50>;
		gpmc,cycle2cycle-diffcsen;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-access-ns = <30>;
		gpmc,wr-data-mux-bus-ns = <0>;

		ti,elm-id = <&elm>;

		#address-cells = <1>;
		#size-cells = <1>;
	};
};

/* Power */
#include "tps65910.dtsi"

&tps {
	vcc1-supply = <&vcc5v>;
	vcc2-supply = <&vcc5v>;
	vcc3-supply = <&vcc5v>;
	vcc4-supply = <&vcc5v>;
	vcc5-supply = <&vcc5v>;
	vcc6-supply = <&vcc5v>;
	vcc7-supply = <&vcc5v>;
	vccio-supply = <&vcc5v>;

	regulators {
		vrtc_reg: regulator@0 {
			regulator-always-on;
		};

		vio_reg: regulator@1 {
			regulator-always-on;
		};

		vdd1_reg: regulator@2 {
			/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1378000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd2_reg: regulator@3 {
			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1150000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd3_reg: regulator@4 {
			regulator-always-on;
		};

		vdig1_reg: regulator@5 {
			regulator-name = "vdig1_1p8v";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		vdig2_reg: regulator@6 {
			regulator-always-on;
		};

		vpll_reg: regulator@7 {
			regulator-always-on;
		};

		vdac_reg: regulator@8 {
			regulator-always-on;
		};

		vaux1_reg: regulator@9 {
			regulator-always-on;
		};

		vaux2_reg: regulator@10 {
			regulator-always-on;
		};

		vaux33_reg: regulator@11 {
			regulator-always-on;
		};

		vmmc_reg: regulator@12 {
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

/* SPI Busses */
&am33xx_pinmux {
	spi0_pins: pinmux_spi0 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
		>;
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;
	status = "okay";

	serial_flash: m25p80@0 {
		compatible = "jedec,spi-nor";
		spi-max-frequency = <48000000>;
		reg = <0x0>;
		m25p,fast-read;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <1>;
	};
};