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git01.mediatek.com / filogic / uboot / ebc98d96985b479c3104e4c59ee2faae04c8c6b9 / . / arch / arm / dts / am335x-phycore-som.dtsi
blob: 3b4b97a941e3bcf62f0e8f7bcd746f0e4de8c9da [file] [log] [blame]
Andrew Davisebc98d92023-04-11 13:24:54 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
Niel Fouried3951852019-06-03 15:31:17 +0200[diff] [blame]2/*
3 * Copyright (C) 2015 Phytec Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
Niel Fouried3951852019-06-03 15:31:17 +0200[diff] [blame]5 */
6
7#include "am33xx.dtsi"
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 model = "Phytec AM335x phyCORE";
12 compatible = "phytec,am335x-phycore-som", "ti,am33xx";
13
14 aliases {
15 rtc0 = &i2c_rtc;
16 rtc1 = &rtc;
17 };
18
19 cpus {
20 cpu@0 {
21 cpu0-supply = <&vdd1_reg>;
22 };
23 };
24
25 memory@80000000 {
26 device_type = "memory";
27 reg = <0x80000000 0x10000000>; /* 256 MB */
28 };
29
30 regulators {
31 compatible = "simple-bus";
32
33 vcc5v: fixedregulator0 {
34 compatible = "regulator-fixed";
35 regulator-name = "vcc5v";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 regulator-boot-on;
39 regulator-always-on;
40 };
41 };
42};
43
44/* Crypto Module */
45&aes {
46 status = "okay";
47};
48
49&sham {
50 status = "okay";
51};
52
53/* Ethernet */
54&am33xx_pinmux {
55 ethernet0_pins: pinmux_ethernet0 {
56 pinctrl-single,pins = <
57 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
58 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
59 AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
60 AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
61 AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
62 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
63 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
64 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
65 >;
66 };
67
68 mdio_pins: pinmux_mdio {
69 pinctrl-single,pins = <
70 /* MDIO */
71 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
72 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
73 >;
74 };
75};
76
77&cpsw_emac0 {
78 phy-handle = <&phy0>;
79 phy-mode = "rmii";
80 dual_emac_res_vlan = <1>;
81};
82
83&davinci_mdio {
84 pinctrl-names = "default";
85 pinctrl-0 = <&mdio_pins>;
86 status = "okay";
87
88 phy0: ethernet-phy@0 {
89 reg = <0>;
90 };
91};
92
93&mac {
94 slaves = <1>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&ethernet0_pins>;
97 status = "okay";
98};
99
100/* I2C Busses */
101&am33xx_pinmux {
102 i2c0_pins: pinmux_i2c0 {
103 pinctrl-single,pins = <
104 AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
105 AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
106 >;
107 };
108};
109
110&i2c0 {
111 pinctrl-names = "default";
112 pinctrl-0 = <&i2c0_pins>;
113 clock-frequency = <400000>;
114 status = "okay";
115
116 tps: pmic@2d {
117 reg = <0x2d>;
118 };
119
120 i2c_tmp102: temp@4b {
121 compatible = "ti,tmp102";
122 reg = <0x4b>;
123 status = "disabled";
124 };
125
126 i2c_eeprom: eeprom@52 {
127 compatible = "atmel,24c32";
128 pagesize = <32>;
129 reg = <0x52>;
130 status = "disabled";
131 };
132
133 i2c_rtc: rtc@68 {
134 compatible = "microcrystal,rv4162";
135 reg = <0x68>;
136 status = "disabled";
137 };
138};
139
140/* NAND memory */
141&am33xx_pinmux {
142 nandflash_pins: pinmux_nandflash {
143 pinctrl-single,pins = <
144 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
145 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
146 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
147 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
148 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
149 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
150 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
151 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
152 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
153 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
154 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
155 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
156 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
157 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
158 >;
159 };
160};
161
162&elm {
163 status = "okay";
164};
165
166&gpmc {
167 status = "okay";
168 pinctrl-names = "default";
169 pinctrl-0 = <&nandflash_pins>;
170 ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
171 nandflash: nand@0,0 {
172 compatible = "ti,omap2-nand";
173 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
174 interrupt-parent = <&gpmc>;
175 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
176 <1 IRQ_TYPE_NONE>; /* termcount */
177 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
178 nand-bus-width = <8>;
179 ti,nand-ecc-opt = "bch8";
180 gpmc,device-nand = "true";
181 gpmc,device-width = <1>;
182 gpmc,sync-clk-ps = <0>;
183 gpmc,cs-on-ns = <0>;
184 gpmc,cs-rd-off-ns = <30>;
185 gpmc,cs-wr-off-ns = <30>;
186 gpmc,adv-on-ns = <0>;
187 gpmc,adv-rd-off-ns = <30>;
188 gpmc,adv-wr-off-ns = <30>;
189 gpmc,we-on-ns = <0>;
190 gpmc,we-off-ns = <20>;
191 gpmc,oe-on-ns = <10>;
192 gpmc,oe-off-ns = <30>;
193 gpmc,access-ns = <30>;
194 gpmc,rd-cycle-ns = <30>;
195 gpmc,wr-cycle-ns = <30>;
196 gpmc,bus-turnaround-ns = <0>;
197 gpmc,cycle2cycle-delay-ns = <50>;
198 gpmc,cycle2cycle-diffcsen;
199 gpmc,clk-activation-ns = <0>;
200 gpmc,wr-access-ns = <30>;
201 gpmc,wr-data-mux-bus-ns = <0>;
202
203 ti,elm-id = <&elm>;
204
205 #address-cells = <1>;
206 #size-cells = <1>;
207 };
208};
209
210/* Power */
211#include "tps65910.dtsi"
212
213&tps {
214 vcc1-supply = <&vcc5v>;
215 vcc2-supply = <&vcc5v>;
216 vcc3-supply = <&vcc5v>;
217 vcc4-supply = <&vcc5v>;
218 vcc5-supply = <&vcc5v>;
219 vcc6-supply = <&vcc5v>;
220 vcc7-supply = <&vcc5v>;
221 vccio-supply = <&vcc5v>;
222
223 regulators {
224 vrtc_reg: regulator@0 {
225 regulator-always-on;
226 };
227
228 vio_reg: regulator@1 {
229 regulator-always-on;
230 };
231
232 vdd1_reg: regulator@2 {
233 /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
234 regulator-name = "vdd_mpu";
235 regulator-min-microvolt = <912500>;
236 regulator-max-microvolt = <1378000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240
241 vdd2_reg: regulator@3 {
242 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
243 regulator-name = "vdd_core";
244 regulator-min-microvolt = <912500>;
245 regulator-max-microvolt = <1150000>;
246 regulator-boot-on;
247 regulator-always-on;
248 };
249
250 vdd3_reg: regulator@4 {
251 regulator-always-on;
252 };
253
254 vdig1_reg: regulator@5 {
255 regulator-name = "vdig1_1p8v";
256 regulator-min-microvolt = <1800000>;
257 regulator-max-microvolt = <1800000>;
258 };
259
260 vdig2_reg: regulator@6 {
261 regulator-always-on;
262 };
263
264 vpll_reg: regulator@7 {
265 regulator-always-on;
266 };
267
268 vdac_reg: regulator@8 {
269 regulator-always-on;
270 };
271
272 vaux1_reg: regulator@9 {
273 regulator-always-on;
274 };
275
276 vaux2_reg: regulator@10 {
277 regulator-always-on;
278 };
279
280 vaux33_reg: regulator@11 {
281 regulator-always-on;
282 };
283
284 vmmc_reg: regulator@12 {
285 regulator-min-microvolt = <3300000>;
286 regulator-max-microvolt = <3300000>;
287 regulator-always-on;
288 };
289 };
290};
291
292/* SPI Busses */
293&am33xx_pinmux {
294 spi0_pins: pinmux_spi0 {
295 pinctrl-single,pins = <
296 AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
297 AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
298 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
299 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
300 >;
301 };
302};
303
304&spi0 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&spi0_pins>;
307 status = "okay";
308
309 serial_flash: m25p80@0 {
310 compatible = "jedec,spi-nor";
311 spi-max-frequency = <48000000>;
312 reg = <0x0>;
313 m25p,fast-read;
314 status = "disabled";
315 #address-cells = <1>;
316 #size-cells = <1>;
317 };
318};