blob: 2de55538fdf1ee9192ce925c8116c5e39943d7ea [file] [log] [blame]
Andy Yanb5e16302019-11-14 11:21:12 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#ifndef __CONFIG_RK3308_COMMON_H
7#define __CONFIG_RK3308_COMMON_H
8
9#include "rockchip-common.h"
10
FUKAUMI Naoki4913ee92024-07-17 13:47:24 +090011#define CFG_IRAM_BASE 0xfff80000
Andy Yanb5e16302019-11-14 11:21:12 +080012
Tom Rinibb4dd962022-11-16 13:10:37 -050013#define CFG_SYS_SDRAM_BASE 0
Andy Yanb5e16302019-11-14 11:21:12 +080014#define SDRAM_MAX_SIZE 0xff000000
Andy Yanb5e16302019-11-14 11:21:12 +080015
FUKAUMI Naoki4913ee92024-07-17 13:47:24 +090016#define ENV_MEM_LAYOUT_SETTINGS \
17 "scriptaddr=0x00500000\0" \
FUKAUMI Naoki8d43a342024-07-17 13:47:25 +090018 "script_offset_f=0xffe000\0" \
19 "script_size_f=0x2000\0" \
FUKAUMI Naoki4913ee92024-07-17 13:47:24 +090020 "pxefile_addr_r=0x00600000\0" \
FUKAUMI Naoki8d43a342024-07-17 13:47:25 +090021 "fdt_addr_r=0x01e00000\0" \
22 "fdtoverlay_addr_r=0x01f00000\0" \
23 "kernel_addr_r=0x02080000\0" \
24 "ramdisk_addr_r=0x06000000\0" \
25 "kernel_comp_addr_r=0x08000000\0" \
26 "kernel_comp_size=0x2000000\0"
Andy Yanb5e16302019-11-14 11:21:12 +080027
FUKAUMI Naoki4913ee92024-07-17 13:47:24 +090028#define CFG_EXTRA_ENV_SETTINGS \
29 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
30 "partitions=" PARTS_DEFAULT \
31 ENV_MEM_LAYOUT_SETTINGS \
32 ROCKCHIP_DEVICE_SETTINGS \
Simon Glassf27e9d52023-04-24 13:49:51 +120033 "boot_targets=" BOOT_TARGETS "\0"
Andy Yanb5e16302019-11-14 11:21:12 +080034
FUKAUMI Naoki4913ee92024-07-17 13:47:24 +090035#endif /* __CONFIG_RK3308_COMMON_H */