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git01.mediatek.com / filogic / uboot / 7ec2413578b3b72531ed60bb45c8a6cd1a142049 / . / drivers / clk / Makefile
blob: f9b90a38b00fdecc7e3df5c1d1b081b1febef664 [file] [log] [blame]
Patrick Delaunayd6e53c72018-10-26 09:02:52 +0200[diff] [blame]1# SPDX-License-Identifier: GPL-2.0+
Simon Glass36ad2342015-06-23 15:39:15 -0600[diff] [blame]2#
3# Copyright (c) 2015 Google, Inc
4# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5#
Simon Glass36ad2342015-06-23 15:39:15 -0600[diff] [blame]6
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]7obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
8obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
9obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
Peng Fan0f085152019-07-31 07:01:34 +0000[diff] [blame]10obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
Lukasz Majewski4de44bb2019-06-24 15:50:45 +0200[diff] [blame]11obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
Peng Fan2d9bd932019-07-31 07:01:54 +0000[diff] [blame]12obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
Marek Vasut59ee41c2023-08-14 01:51:27 +0200[diff] [blame]13obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o
Stephen Warrene8e3f202016-08-08 11:28:24 -0600[diff] [blame]14
Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame]15obj-y += adi/
Anup Patel00a156d2019-06-25 06:31:02 +0000[diff] [blame]16obj-y += analogbits/
Peng Fan5e80d5a2018-10-18 14:28:30 +0200[diff] [blame]17obj-y += imx/
Yanhong Wang5a85d052023-03-29 11:42:13 +0800[diff] [blame]18obj-$(CONFIG_CLK_JH7110) += starfive/
Stephen Warrene8e3f202016-08-08 11:28:24 -0600[diff] [blame]19obj-y += tegra/
Dario Binacchida3b0202020-12-30 00:06:32 +0100[diff] [blame]20obj-y += ti/
Sean Anderson5eafaa62021-12-15 11:36:18 -0500[diff] [blame]21obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
Mario Sixd290e272018-01-15 11:06:54 +0100[diff] [blame]22obj-$(CONFIG_ARCH_ASPEED) += aspeed/
developer2186c982018-11-15 10:07:54 +0800[diff] [blame]23obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
Jerome Brunet3da39a82019-02-10 14:54:30 +0100[diff] [blame]24obj-$(CONFIG_ARCH_MESON) += meson/
Sean Anderson5eafaa62021-12-15 11:36:18 -0500[diff] [blame]25obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
Jim Liu25688562022-04-19 13:32:20 +0800[diff] [blame]26obj-$(CONFIG_ARCH_NPCM) += nuvoton/
Mario Sixd290e272018-01-15 11:06:54 +0100[diff] [blame]27obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
Marek Vasut3f9d7352018-07-31 17:58:07 +0200[diff] [blame]28obj-$(CONFIG_ARCH_SOCFPGA) += altera/
Patrick Delaunay12427612022-05-19 17:56:45 +0200[diff] [blame]29obj-$(CONFIG_ARCH_STM32) += stm32/
30obj-$(CONFIG_ARCH_STM32MP) += stm32/
Wenyou Yang8c772bd2016-07-20 17:55:12 +0800[diff] [blame]31obj-$(CONFIG_CLK_AT91) += at91/
Álvaro Fernández Rojasc35611c2017-05-07 20:13:01 +0200[diff] [blame]32obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
Paul Burton0399f442016-09-08 07:47:38 +0100[diff] [blame]33obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
Sean Anderson5eafaa62021-12-15 11:36:18 -0500[diff] [blame]34obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
Mario Sixd290e272018-01-15 11:06:54 +0100[diff] [blame]35obj-$(CONFIG_CLK_EXYNOS) += exynos/
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300[diff] [blame]36obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
Damien Le Moal6e5a8b72022-03-01 10:35:39 +0000[diff] [blame]37obj-$(CONFIG_CLK_K210) += clk_k210.o
Mario Six7cab1472018-08-06 10:23:36 +0200[diff] [blame]38obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
Padmarao Begari0c4ae802021-01-15 08:20:38 +0530[diff] [blame]39obj-$(CONFIG_CLK_MPFS) += microchip/
Sean Anderson5eafaa62021-12-15 11:36:18 -0500[diff] [blame]40obj-$(CONFIG_CLK_MVEBU) += mvebu/
Stefan Roese560b07f2020-07-30 13:56:16 +0200[diff] [blame]41obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
Manivannan Sadhasivam91a85132018-06-14 23:38:35 +0530[diff] [blame]42obj-$(CONFIG_CLK_OWL) += owl/
Caleb Connolly878b26a2023-11-07 12:40:59 +0000[diff] [blame]43obj-$(CONFIG_CLK_QCOM) += qcom/
Mario Sixd290e272018-01-15 11:06:54 +0100[diff] [blame]44obj-$(CONFIG_CLK_RENESAS) += renesas/
Jonas Karlman3cf87082023-04-17 19:07:18 +0000[diff] [blame]45obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
Anup Patel42fdf082019-02-25 08:14:49 +0000[diff] [blame]46obj-$(CONFIG_CLK_SIFIVE) += sifive/
Kongyang Liu80bf1f72024-06-11 17:41:14 +0800[diff] [blame]47obj-$(CONFIG_CLK_SOPHGO) += sophgo/
Samuel Holland687f5e82023-10-30 23:49:22 -0500[diff] [blame]48obj-$(CONFIG_CLK_SUNXI) += sunxi/
Mario Sixd290e272018-01-15 11:06:54 +0100[diff] [blame]49obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
Sean Anderson5eafaa62021-12-15 11:36:18 -0500[diff] [blame]50obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
51obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
Liviu Dudauba024e62018-09-17 17:50:00 +0100[diff] [blame]52obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
Sean Anderson5eafaa62021-12-15 11:36:18 -0500[diff] [blame]53obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
Mario Sixd290e272018-01-15 11:06:54 +0100[diff] [blame]54obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
55obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
Sean Anderson35b37542021-12-15 11:36:20 -0500[diff] [blame]56obj-$(CONFIG_CLK_ICS8N3QV01) += ics8n3qv01.o
Mario Sixd290e272018-01-15 11:06:54 +0100[diff] [blame]57obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
Sean Anderson5eafaa62021-12-15 11:36:18 -0500[diff] [blame]58obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
Mario Sixd290e272018-01-15 11:06:54 +0100[diff] [blame]59obj-$(CONFIG_SANDBOX) += clk_sandbox.o
60obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o