Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 2 | /* |
Marcel Ziswiler | 510c2dd | 2019-03-25 17:25:01 +0100 | [diff] [blame] | 3 | * Copyright 2015-2019 Toradex, Inc. |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 4 | * |
Marcel Ziswiler | d92dee5 | 2016-11-16 17:49:23 +0100 | [diff] [blame] | 5 | * Configuration settings for the Toradex VF50/VF61 modules. |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 6 | * |
| 7 | * Based on vf610twr.h: |
| 8 | * Copyright 2013 Freescale Semiconductor, Inc. |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | #include <asm/arch/imx-regs.h> |
Marcel Ziswiler | 2e3b3d5 | 2019-03-25 17:25:02 +0100 | [diff] [blame] | 15 | #include <linux/sizes.h> |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 16 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 17 | /* NAND support */ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 18 | |
| 19 | #define CONFIG_IPADDR 192.168.10.2 |
| 20 | #define CONFIG_NETMASK 255.255.255.0 |
| 21 | #define CONFIG_SERVERIP 192.168.10.1 |
| 22 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 23 | #define CONFIG_FDTADDR 0x84000000 |
| 24 | |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 25 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 26 | "bootm_size=0x10000000\0" \ |
| 27 | "fdt_addr_r=0x82000000\0" \ |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 28 | "kernel_addr_r=0x81000000\0" \ |
| 29 | "pxefile_addr_r=0x87100000\0" \ |
| 30 | "ramdisk_addr_r=0x82100000\0" \ |
| 31 | "scriptaddr=0x87000000\0" |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 32 | |
Igor Opaniuk | af80e15 | 2019-12-09 12:33:32 +0200 | [diff] [blame] | 33 | #define UBOOT_UPDATE \ |
| 34 | "update_uboot=nand erase.part u-boot && " \ |
| 35 | "nand write ${loadaddr} u-boot ${filesize}\0" \ |
| 36 | |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 37 | #define UBI_BOOTCMD \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 38 | "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ |
| 39 | "ubi.fm_autoconvert=1\0" \ |
| 40 | "ubiboot=run setup; " \ |
| 41 | "setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \ |
Philippe Schenker | 21c3842 | 2022-04-08 10:07:02 +0200 | [diff] [blame] | 42 | "${setupargs} ${vidargs} ${tdxargs}; echo Booting from NAND...; " \ |
Sanchayan Maity | 27e4e10 | 2016-11-25 16:19:17 +0530 | [diff] [blame] | 43 | "ubi part ubi && " \ |
| 44 | "ubi read ${kernel_addr_r} kernel && " \ |
| 45 | "ubi read ${fdt_addr_r} dtb && " \ |
Sanchayan Maity | a48b427 | 2016-12-02 14:28:27 +0530 | [diff] [blame] | 46 | "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 47 | |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 48 | #define BOOT_TARGET_DEVICES(func) \ |
| 49 | func(MMC, mmc, 0) \ |
| 50 | func(USB, usb, 0) \ |
| 51 | func(DHCP, dhcp, na) |
| 52 | #include <config_distro_bootcmd.h> |
| 53 | #undef BOOTENV_RUN_NET_USB_START |
| 54 | #define BOOTENV_RUN_NET_USB_START "" |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 55 | |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 56 | #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" |
| 57 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 58 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 59 | BOOTENV \ |
| 60 | MEM_LAYOUT_ENV_SETTINGS \ |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 61 | UBI_BOOTCMD \ |
Igor Opaniuk | af80e15 | 2019-12-09 12:33:32 +0200 | [diff] [blame] | 62 | UBOOT_UPDATE \ |
Igor Opaniuk | 84c1a2d | 2022-04-13 11:33:27 +0200 | [diff] [blame] | 63 | "boot_script_dhcp=boot.scr\0" \ |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 64 | "console=ttyLP0\0" \ |
Stefan Agner | b093f0f | 2019-03-25 17:25:07 +0100 | [diff] [blame] | 65 | "defargs=user_debug=30\0" \ |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 66 | "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 67 | "fdt_board=eval-v3\0" \ |
Sanchayan Maity | a48b427 | 2016-12-02 14:28:27 +0530 | [diff] [blame] | 68 | "fdt_fixup=;\0" \ |
Max Krummenacher | 115d21f | 2020-06-16 22:20:05 +0300 | [diff] [blame] | 69 | "kernel_image=zImage\0" \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 70 | "setsdupdate=mmc rescan && set interface mmc && " \ |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 71 | "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ |
| 72 | "source ${loadaddr}\0" \ |
| 73 | "setup=setenv setupargs console=tty1 console=${console}" \ |
| 74 | ",${baudrate}n8 ${memargs}\0" \ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 75 | "setupdate=run setsdupdate || run setusbupdate\0" \ |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 76 | "setusbupdate=usb start && set interface usb && " \ |
| 77 | "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ |
| 78 | "source ${loadaddr}\0" \ |
Stefan Agner | 1301175 | 2017-04-11 11:12:14 +0530 | [diff] [blame] | 79 | "splashpos=m,m\0" \ |
Stefan Agner | c059483 | 2019-03-25 17:25:03 +0100 | [diff] [blame] | 80 | "video-mode=dcufb:640x480-16@60,monitor=lcd\0" |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 81 | |
| 82 | /* Miscellaneous configurable options */ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 83 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 84 | /* Physical memory map */ |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 85 | #define PHYS_SDRAM (0x80000000) |
Marcel Ziswiler | 2e3b3d5 | 2019-03-25 17:25:02 +0100 | [diff] [blame] | 86 | #define PHYS_SDRAM_SIZE (256 * SZ_1M) |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 87 | |
| 88 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
| 89 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 90 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
| 91 | |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 92 | /* USB Host Support */ |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 93 | |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 94 | /* USB DFU */ |
Sanchayan Maity | 7755e53 | 2015-04-17 18:56:42 +0530 | [diff] [blame] | 95 | |
Sanchayan Maity | cc4d78f | 2015-04-15 16:24:26 +0530 | [diff] [blame] | 96 | #endif /* __CONFIG_H */ |