Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Vladimir Zapolskiy | 8bf9450 | 2015-12-19 23:29:25 +0200 | [diff] [blame] | 7 | #include <dm.h> |
| 8 | #include <ns16550.h> |
| 9 | #include <dm/platform_data/lpc32xx_hsuart.h> |
| 10 | |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 11 | #include <asm/arch/clk.h> |
| 12 | #include <asm/arch/uart.h> |
Albert ARIBAUD \(3ADEV\) | 24bfa9d | 2015-03-31 11:40:47 +0200 | [diff] [blame] | 13 | #include <asm/arch/mux.h> |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 14 | #include <asm/io.h> |
| 15 | |
| 16 | static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; |
| 17 | static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; |
Albert ARIBAUD \(3ADEV\) | 24bfa9d | 2015-03-31 11:40:47 +0200 | [diff] [blame] | 18 | static struct mux_regs *mux = (struct mux_regs *)MUX_BASE; |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 19 | |
| 20 | void lpc32xx_uart_init(unsigned int uart_id) |
| 21 | { |
| 22 | if (uart_id < 1 || uart_id > 7) |
| 23 | return; |
| 24 | |
| 25 | /* Disable loopback mode, if it is set by S1L bootloader */ |
Trevor Woerner | 0b881ac | 2021-06-10 22:37:02 -0400 | [diff] [blame] | 26 | clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id)); |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 27 | |
| 28 | if (uart_id < 3 || uart_id > 6) |
| 29 | return; |
| 30 | |
| 31 | /* Enable UART system clock */ |
| 32 | setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id)); |
| 33 | |
| 34 | /* Set UART into autoclock mode */ |
| 35 | clrsetbits_le32(&ctrl->clkmode, |
| 36 | UART_CLKMODE_MASK(uart_id), |
| 37 | UART_CLKMODE_AUTO(uart_id)); |
| 38 | |
| 39 | /* Bypass pre-divider of UART clock */ |
| 40 | writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1), |
| 41 | &clk->u3clk + (uart_id - 3)); |
| 42 | } |
Albert ARIBAUD \(3ADEV\) | 391e163 | 2015-03-31 11:40:43 +0200 | [diff] [blame] | 43 | |
Vladimir Zapolskiy | 45e3fd9 | 2015-12-19 23:29:26 +0200 | [diff] [blame] | 44 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 45 | static const struct ns16550_plat lpc32xx_uart[] = { |
Heiko Schocher | 06f108e | 2017-01-18 08:05:49 +0100 | [diff] [blame] | 46 | { .base = UART3_BASE, .reg_shift = 2, |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 47 | .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
Heiko Schocher | 06f108e | 2017-01-18 08:05:49 +0100 | [diff] [blame] | 48 | { .base = UART4_BASE, .reg_shift = 2, |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 49 | .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
Heiko Schocher | 06f108e | 2017-01-18 08:05:49 +0100 | [diff] [blame] | 50 | { .base = UART5_BASE, .reg_shift = 2, |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 51 | .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
Heiko Schocher | 06f108e | 2017-01-18 08:05:49 +0100 | [diff] [blame] | 52 | { .base = UART6_BASE, .reg_shift = 2, |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 53 | .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, |
Vladimir Zapolskiy | 8bf9450 | 2015-12-19 23:29:25 +0200 | [diff] [blame] | 54 | }; |
| 55 | |
| 56 | #if defined(CONFIG_LPC32XX_HSUART) |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 57 | static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = { |
Vladimir Zapolskiy | 8bf9450 | 2015-12-19 23:29:25 +0200 | [diff] [blame] | 58 | { HS_UART1_BASE, }, |
| 59 | { HS_UART2_BASE, }, |
| 60 | { HS_UART7_BASE, }, |
| 61 | }; |
| 62 | #endif |
| 63 | |
Simon Glass | 1d8364a | 2020-12-28 20:34:54 -0700 | [diff] [blame] | 64 | U_BOOT_DRVINFOS(lpc32xx_uarts) = { |
Vladimir Zapolskiy | 8bf9450 | 2015-12-19 23:29:25 +0200 | [diff] [blame] | 65 | #if defined(CONFIG_LPC32XX_HSUART) |
| 66 | { "lpc32xx_hsuart", &lpc32xx_hsuart[0], }, |
| 67 | { "lpc32xx_hsuart", &lpc32xx_hsuart[1], }, |
| 68 | #endif |
| 69 | { "ns16550_serial", &lpc32xx_uart[0], }, |
| 70 | { "ns16550_serial", &lpc32xx_uart[1], }, |
| 71 | { "ns16550_serial", &lpc32xx_uart[2], }, |
| 72 | { "ns16550_serial", &lpc32xx_uart[3], }, |
| 73 | #if defined(CONFIG_LPC32XX_HSUART) |
| 74 | { "lpc32xx_hsuart", &lpc32xx_hsuart[2], }, |
| 75 | #endif |
| 76 | }; |
| 77 | #endif |
| 78 | |
Sylvain Lemieux | 90a837f | 2015-08-10 08:16:31 -0400 | [diff] [blame] | 79 | void lpc32xx_dma_init(void) |
| 80 | { |
| 81 | /* Enable DMA interface */ |
Vladimir Zapolskiy | b7f8ed2 | 2015-08-27 03:16:48 +0300 | [diff] [blame] | 82 | writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl); |
Sylvain Lemieux | 90a837f | 2015-08-10 08:16:31 -0400 | [diff] [blame] | 83 | } |
| 84 | |
Albert ARIBAUD \(3ADEV\) | 391e163 | 2015-03-31 11:40:43 +0200 | [diff] [blame] | 85 | void lpc32xx_mac_init(void) |
| 86 | { |
| 87 | /* Enable MAC interface */ |
| 88 | writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER |
Vladimir Zapolskiy | 8bffd71 | 2015-07-06 07:22:11 +0300 | [diff] [blame] | 89 | #if defined(CONFIG_RMII) |
| 90 | | CLK_MAC_RMII, |
| 91 | #else |
| 92 | | CLK_MAC_MII, |
| 93 | #endif |
| 94 | &clk->macclk_ctrl); |
Albert ARIBAUD \(3ADEV\) | 391e163 | 2015-03-31 11:40:43 +0200 | [diff] [blame] | 95 | } |
Albert ARIBAUD \(3ADEV\) | 7c97f70 | 2015-03-31 11:40:44 +0200 | [diff] [blame] | 96 | |
| 97 | void lpc32xx_mlc_nand_init(void) |
| 98 | { |
| 99 | /* Enable NAND interface */ |
| 100 | writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl); |
| 101 | } |
Albert ARIBAUD \(3ADEV\) | b23324c | 2015-03-31 11:40:45 +0200 | [diff] [blame] | 102 | |
Vladimir Zapolskiy | 78f04f0 | 2015-07-18 03:07:52 +0300 | [diff] [blame] | 103 | void lpc32xx_slc_nand_init(void) |
| 104 | { |
| 105 | /* Enable SLC NAND interface */ |
| 106 | writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl); |
| 107 | } |
| 108 | |
Sylvain Lemieux | 890cc77 | 2015-08-13 15:40:22 -0400 | [diff] [blame] | 109 | void lpc32xx_usb_init(void) |
| 110 | { |
| 111 | /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */ |
| 112 | clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE); |
| 113 | } |
| 114 | |
Albert ARIBAUD \(3ADEV\) | b23324c | 2015-03-31 11:40:45 +0200 | [diff] [blame] | 115 | void lpc32xx_i2c_init(unsigned int devnum) |
| 116 | { |
| 117 | /* Enable I2C interface */ |
| 118 | uint32_t ctrl = readl(&clk->i2cclk_ctrl); |
| 119 | if (devnum == 1) |
| 120 | ctrl |= CLK_I2C1_ENABLE; |
| 121 | if (devnum == 2) |
| 122 | ctrl |= CLK_I2C2_ENABLE; |
| 123 | writel(ctrl, &clk->i2cclk_ctrl); |
| 124 | } |
Albert ARIBAUD \(3ADEV\) | eb135ad | 2015-03-31 11:40:46 +0200 | [diff] [blame] | 125 | |
Simon Glass | 1d8364a | 2020-12-28 20:34:54 -0700 | [diff] [blame] | 126 | U_BOOT_DRVINFO(lpc32xx_gpios) = { |
Albert ARIBAUD \(3ADEV\) | eb135ad | 2015-03-31 11:40:46 +0200 | [diff] [blame] | 127 | .name = "gpio_lpc32xx" |
| 128 | }; |
Albert ARIBAUD \(3ADEV\) | 24bfa9d | 2015-03-31 11:40:47 +0200 | [diff] [blame] | 129 | |
| 130 | /* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */ |
| 131 | |
| 132 | #define P_MUX_SET_SSP0 0x1600 |
| 133 | |
| 134 | void lpc32xx_ssp_init(void) |
| 135 | { |
| 136 | /* Enable SSP0 interface */ |
| 137 | writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl); |
| 138 | /* Mux SSP0 pins */ |
| 139 | writel(P_MUX_SET_SSP0, &mux->p_mux_set); |
| 140 | } |