blob: 8a351b927c056f2cba1fefe44c1284918981cbd9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Eran Liberty9095d4a2005-07-28 10:08:46 -05002/*
3 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
4 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
5 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
Scott Woodb71689b2008-06-30 14:13:28 -05006 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
Eran Liberty9095d4a2005-07-28 10:08:46 -05007 */
8
9/*
10 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
11 */
12
Wolfgang Denk0191e472010-10-26 14:34:52 +020013#include <asm-offsets.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050014#include <config.h>
Jon Loeligerebc72242005-08-01 13:20:47 -050015#include <mpc83xx.h>
Tom Rini4ddbade2022-05-25 12:16:03 -040016#include <system-constants.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050017
Eran Liberty9095d4a2005-07-28 10:08:46 -050018#include <ppc_asm.tmpl>
19#include <ppc_defs.h>
20
21#include <asm/cache.h>
22#include <asm/mmu.h>
Peter Tyser3a1362d2010-10-14 23:33:24 -050023#include <asm/u-boot.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050024
Mario Six94867102019-01-21 09:17:54 +010025#include "hrcw/hrcw.h"
Mario Sixa861ea62019-01-21 09:17:57 +010026#include "bats/bats.h"
Mario Six8b2141c2019-01-21 09:18:09 +010027#include "hid/hid.h"
Mario Six94867102019-01-21 09:17:54 +010028
Eran Liberty9095d4a2005-07-28 10:08:46 -050029/* We don't want the MMU yet.
30 */
31#undef MSR_KERNEL
32
33/*
34 * Floating Point enable, Machine Check and Recoverable Interr.
35 */
36#ifdef DEBUG
37#define MSR_KERNEL (MSR_FP|MSR_RI)
38#else
39#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
40#endif
41
Scott Wood2b36fbb2012-12-06 13:33:17 +000042#if defined(CONFIG_NAND_SPL) || \
Tom Rini6b15c162022-05-13 12:26:35 -040043 (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL))
Scott Wood2b36fbb2012-12-06 13:33:17 +000044#define MINIMAL_SPL
45#endif
46
47#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
48 !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_FLASHBOOT
Scott Woodb71689b2008-06-30 14:13:28 -050050#endif
51
Eran Liberty9095d4a2005-07-28 10:08:46 -050052/*
53 * Set up GOT: Global Offset Table
54 *
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +010055 * Use r12 to access the GOT
Eran Liberty9095d4a2005-07-28 10:08:46 -050056 */
57 START_GOT
58 GOT_ENTRY(_GOT2_TABLE_)
Scott Woodb71689b2008-06-30 14:13:28 -050059 GOT_ENTRY(__bss_start)
Simon Glassed70c8f2013-03-14 06:54:53 +000060 GOT_ENTRY(__bss_end)
Eran Liberty9095d4a2005-07-28 10:08:46 -050061
Scott Wood2b36fbb2012-12-06 13:33:17 +000062#ifndef MINIMAL_SPL
Scott Woodb71689b2008-06-30 14:13:28 -050063 GOT_ENTRY(_FIXUP_TABLE_)
Eran Liberty9095d4a2005-07-28 10:08:46 -050064 GOT_ENTRY(_start)
65 GOT_ENTRY(_start_of_vectors)
66 GOT_ENTRY(_end_of_vectors)
67 GOT_ENTRY(transfer_to_handler)
Scott Woodb71689b2008-06-30 14:13:28 -050068#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -050069 END_GOT
70
71/*
Jerry Van Baren93eb9312006-12-06 21:23:55 -050072 * The Hard Reset Configuration Word (HRCW) table is in the first 64
73 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
74 * times so the processor can fetch it out of flash whether the flash
75 * is 8, 16, 32, or 64 bits wide (hardware trickery).
Eran Liberty9095d4a2005-07-28 10:08:46 -050076 */
Eran Liberty9095d4a2005-07-28 10:08:46 -050077 .text
78#define _HRCW_TABLE_ENTRY(w) \
79 .fill 8,1,(((w)>>24)&0xff); \
80 .fill 8,1,(((w)>>16)&0xff); \
81 .fill 8,1,(((w)>> 8)&0xff); \
82 .fill 8,1,(((w) )&0xff)
83
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
85 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
Eran Liberty9095d4a2005-07-28 10:08:46 -050086
Jerry Van Baren93eb9312006-12-06 21:23:55 -050087/*
88 * Magic number and version string - put it after the HRCW since it
89 * cannot be first in flash like it is in many other processors.
90 */
91 .long 0x27051956 /* U-Boot Magic Number */
92
Ron Madrid787b61d2008-12-12 13:12:45 -080093 .globl enable_addr_trans
94enable_addr_trans:
95 /* enable address translation */
96 mfmsr r5
97 ori r5, r5, (MSR_IR | MSR_DR)
98 mtmsr r5
99 isync
100 blr
101
102 .globl disable_addr_trans
103disable_addr_trans:
104 /* disable address translation */
105 mflr r4
106 mfmsr r3
107 andi. r0, r3, (MSR_IR | MSR_DR)
108 beqlr
109 andc r3, r3, r0
110 mtspr SRR0, r4
111 mtspr SRR1, r3
112 rfi
113
Eran Liberty9095d4a2005-07-28 10:08:46 -0500114#ifndef CONFIG_DEFAULT_IMMR
115#error CONFIG_DEFAULT_IMMR must be defined
Heiko Schocher71cb3e92017-06-07 17:33:10 +0200116#endif /* CONFIG_DEFAULT_IMMR */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500117
118/*
119 * After configuration, a system reset exception is executed using the
120 * vector at offset 0x100 relative to the base set by MSR[IP]. If
121 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
122 * base address is 0xfff00000. In the case of a Power On Reset or Hard
123 * Reset, the value of MSR[IP] is determined by the CIP field in the
124 * HRCW.
125 *
126 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
127 * This determines the location of the boot ROM (flash or EPROM) in the
128 * processor's address space at boot time. As long as the HRCW is set up
129 * so that we eventually end up executing the code below when the
130 * processor executes the reset exception, the actual values used should
131 * not matter.
132 *
133 * Once we have got here, the address mask in OR0 is cleared so that the
134 * bottom 32K of the boot ROM is effectively repeated all throughout the
135 * processor's address space, after which we can jump to the absolute
136 * address at which the boot ROM was linked at compile time, and proceed
137 * to initialise the memory controller without worrying if the rug will
138 * be pulled out from under us, so to speak (it will be fine as long as
139 * we configure BR0 with the same boot ROM link address).
140 */
141 . = EXC_OFF_SYS_RESET
142
143 .globl _start
144_start: /* time t 0 */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500145 lis r4, CONFIG_DEFAULT_IMMR@h
146 nop
Peter Tyser0c44caf2010-09-14 19:13:53 -0500147
Eran Liberty9095d4a2005-07-28 10:08:46 -0500148 mfmsr r5 /* save msr contents */
Scott Wood838450e2009-01-20 11:56:11 -0600149
150 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
151 bl 1f
1521: mflr r7
153
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154 lis r3, CONFIG_SYS_IMMR@h
155 ori r3, r3, CONFIG_SYS_IMMR@l
Scott Wood838450e2009-01-20 11:56:11 -0600156
157 lwz r6, IMMRBAR(r4)
158 isync
159
Eran Liberty9095d4a2005-07-28 10:08:46 -0500160 stw r3, IMMRBAR(r4)
Scott Wood838450e2009-01-20 11:56:11 -0600161 lwz r6, 0(r7) /* Arbitrary external load */
162 isync
163
164 lwz r6, IMMRBAR(r3)
165 isync
Jon Loeligerebc72242005-08-01 13:20:47 -0500166
Eran Liberty9095d4a2005-07-28 10:08:46 -0500167 /* Initialise the E300 processor core */
168 /*------------------------------------------*/
Jon Loeligerebc72242005-08-01 13:20:47 -0500169
Scott Wood2b36fbb2012-12-06 13:33:17 +0000170#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
171 defined(CONFIG_NAND_SPL)
Lepcha Suchit7ed421f2008-10-16 13:38:00 -0500172 /* The FCM begins execution after only the first page
173 * is loaded. Wait for the rest before branching
174 * to another flash page.
175 */
Scott Wood838450e2009-01-20 11:56:11 -06001761: lwz r6, 0x50b0(r3)
Lepcha Suchit7ed421f2008-10-16 13:38:00 -0500177 andi. r6, r6, 1
178 beq 1b
179#endif
180
Eran Liberty9095d4a2005-07-28 10:08:46 -0500181 bl init_e300_core
Jon Loeligerebc72242005-08-01 13:20:47 -0500182
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#ifdef CONFIG_SYS_FLASHBOOT
Eran Liberty9095d4a2005-07-28 10:08:46 -0500184
185 /* Inflate flash location so it appears everywhere, calculate */
186 /* the absolute address in final location of the FLASH, jump */
187 /* there and deflate the flash size back to minimal size */
188 /*------------------------------------------------------------*/
189 bl map_flash_by_law1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
191 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500192 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
193 mtlr r5
194 blr
195in_flash:
196#if 1 /* Remapping flash with LAW0. */
197 bl remap_flash_by_law0
198#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199#endif /* CONFIG_SYS_FLASHBOOT */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500200
Kumar Galad5d94d62006-02-10 15:40:06 -0600201 /* setup the bats */
202 bl setup_bats
203 sync
204
205 /*
206 * Cache must be enabled here for stack-in-cache trick.
207 * This means we need to enable the BATS.
208 * This means:
209 * 1) for the EVB, original gt regs need to be mapped
210 * 2) need to have an IBAT for the 0xf region,
211 * we are running there!
212 * Cache should be turned on after BATs, since by default
213 * everything is write-through.
214 * The init-mem BAT can be reused after reloc. The old
215 * gt-regs BAT can be reused after board_init_f calls
216 * board_early_init_f (EVB only).
217 */
218 /* enable address translation */
219 bl enable_addr_trans
220 sync
221
Nick Spence7c20aef2008-08-28 14:09:25 -0700222 /* enable the data cache */
Kumar Galad5d94d62006-02-10 15:40:06 -0600223 bl dcache_enable
224 sync
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#ifdef CONFIG_SYS_INIT_RAM_LOCK
Kumar Galad5d94d62006-02-10 15:40:06 -0600226 bl lock_ram_in_cache
227 sync
228#endif
229
230 /* set up the stack pointer in our newly created
mario.six@gdsys.ccd4f4a542017-01-17 08:33:47 +0100231 * cache-ram; use r3 to keep the new SP for now to
232 * avoid overiding the SP it uselessly */
Tom Rini4ddbade2022-05-25 12:16:03 -0400233 lis r3, SYS_INIT_SP_ADDR@h
234 ori r3, r3, SYS_INIT_SP_ADDR@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600235
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100236 /* r4 = end of GD area */
237 addi r4, r3, GENERATED_GBL_DATA_SIZE
238
239 /* Zero GD area */
240 li r0, 0
2411:
242 subi r4, r4, 1
243 stb r0, 0(r4)
244 cmplw r3, r4
245 bne 1b
246
Andy Yanad0ac4b2017-07-24 17:47:27 +0800247#if CONFIG_VAL(SYS_MALLOC_F_LEN)
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100248
Andy Yanad0ac4b2017-07-24 17:47:27 +0800249#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
250#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100251#endif
252
253 /* r3 = new stack pointer / pre-reloc malloc area */
Andy Yanad0ac4b2017-07-24 17:47:27 +0800254 subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN)
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100255
256 /* Set pointer to pre-reloc malloc area in GD */
257 stw r3, GD_MALLOC_BASE(r4)
258#endif
Kumar Galad5d94d62006-02-10 15:40:06 -0600259 li r0, 0 /* Make room for stack frame header and */
mario.six@gdsys.ccd4f4a542017-01-17 08:33:47 +0100260 stwu r0, -4(r3) /* clear final stack frame so that */
261 stwu r0, -4(r3) /* stack backtraces terminate cleanly */
Kumar Galad5d94d62006-02-10 15:40:06 -0600262
mario.six@gdsys.ccd4f4a542017-01-17 08:33:47 +0100263 /* Finally, actually set SP */
264 mr r1, r3
Eran Liberty9095d4a2005-07-28 10:08:46 -0500265
266 /* let the C-code set up the rest */
Kumar Galad5d94d62006-02-10 15:40:06 -0600267 /* */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500268 /* Be careful to keep code relocatable & stack humble */
269 /*------------------------------------------------------*/
270
271 GET_GOT /* initialize GOT access */
Joakim Tjernlundf14554d2018-11-28 10:59:55 +0100272 /* Needed for -msingle-pic-base */
273 bl _GLOBAL_OFFSET_TABLE_@local-4
274 mflr r30
Wolfgang Denkb2d36ea2011-04-20 22:11:21 +0200275
Eran Liberty9095d4a2005-07-28 10:08:46 -0500276 /* r3: IMMR */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200277 lis r3, CONFIG_SYS_IMMR@h
Eran Liberty9095d4a2005-07-28 10:08:46 -0500278 /* run low-level CPU init code (in Flash)*/
279 bl cpu_init_f
280
Eran Liberty9095d4a2005-07-28 10:08:46 -0500281 /* run 1st part of board init code (in Flash)*/
Valentin Longchampe91e10a2014-10-03 11:45:23 +0200282 li r3, 0 /* clear boot_flag for calling board_init_f */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500283 bl board_init_f
284
Peter Tyser0c44caf2010-09-14 19:13:53 -0500285 /* NOTREACHED - board_init_f() does not return */
286
Scott Wood2b36fbb2012-12-06 13:33:17 +0000287#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -0500288/*
289 * Vector Table
290 */
291
292 .globl _start_of_vectors
293_start_of_vectors:
294
295/* Machine check */
296 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
297
298/* Data Storage exception. */
299 STD_EXCEPTION(0x300, DataStorage, UnknownException)
300
301/* Instruction Storage exception. */
302 STD_EXCEPTION(0x400, InstStorage, UnknownException)
303
304/* External Interrupt exception. */
305#ifndef FIXME
306 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
Jon Loeligerebc72242005-08-01 13:20:47 -0500307#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500308
309/* Alignment exception. */
310 . = 0x600
311Alignment:
Rafal Jaworowski06244e42007-06-22 14:58:04 +0200312 EXCEPTION_PROLOG(SRR0, SRR1)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500313 mfspr r4,DAR
314 stw r4,_DAR(r21)
315 mfspr r5,DSISR
316 stw r5,_DSISR(r21)
317 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100318 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500319
320/* Program check exception */
321 . = 0x700
322ProgramCheck:
Rafal Jaworowski06244e42007-06-22 14:58:04 +0200323 EXCEPTION_PROLOG(SRR0, SRR1)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500324 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100325 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
326 MSR_KERNEL, COPY_EE)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500327
328 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
329
330 /* I guess we could implement decrementer, and may have
331 * to someday for timekeeping.
332 */
333 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
334
335 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
336 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
337 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
338 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
339
340 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
341 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
342
343 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
344 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
345 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
346#ifdef DEBUG
347 . = 0x1300
348 /*
349 * This exception occurs when the program counter matches the
350 * Instruction Address Breakpoint Register (IABR).
351 *
352 * I want the cpu to halt if this occurs so I can hunt around
353 * with the debugger and look at things.
354 *
355 * When DEBUG is defined, both machine check enable (in the MSR)
356 * and checkstop reset enable (in the reset mode register) are
357 * turned off and so a checkstop condition will result in the cpu
358 * halting.
359 *
360 * I force the cpu into a checkstop condition by putting an illegal
361 * instruction here (at least this is the theory).
362 *
363 * well - that didnt work, so just do an infinite loop!
364 */
3651: b 1b
366#else
367 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
368#endif
369 STD_EXCEPTION(0x1400, SMI, UnknownException)
370
371 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
372 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
373 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
374 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
375 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
376 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
377 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
378 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
379 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
380 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
381 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
382 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
383 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
384 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
385 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
386 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
387 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
388 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
389 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
390 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
391 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
392 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
393 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
394 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
395 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
396 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
397 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
398
399
400 .globl _end_of_vectors
401_end_of_vectors:
402
403 . = 0x3000
404
405/*
406 * This code finishes saving the registers to the exception frame
407 * and jumps to the appropriate handler for the exception.
408 * Register r21 is pointer into trap frame, r1 has new stack pointer.
409 */
410 .globl transfer_to_handler
411transfer_to_handler:
412 stw r22,_NIP(r21)
413 lis r22,MSR_POW@h
414 andc r23,r23,r22
415 stw r23,_MSR(r21)
416 SAVE_GPR(7, r21)
417 SAVE_4GPRS(8, r21)
418 SAVE_8GPRS(12, r21)
419 SAVE_8GPRS(24, r21)
420 mflr r23
421 andi. r24,r23,0x3f00 /* get vector offset */
422 stw r24,TRAP(r21)
423 li r22,0
424 stw r22,RESULT(r21)
425 lwz r24,0(r23) /* virtual address of handler */
426 lwz r23,4(r23) /* where to go when done */
427 mtspr SRR0,r24
428 mtspr SRR1,r20
429 mtlr r23
430 SYNC
431 rfi /* jump to handler, enable MMU */
432
433int_return:
434 mfmsr r28 /* Disable interrupts */
435 li r4,0
436 ori r4,r4,MSR_EE
437 andc r28,r28,r4
438 SYNC /* Some chip revs need this... */
439 mtmsr r28
440 SYNC
441 lwz r2,_CTR(r1)
442 lwz r0,_LINK(r1)
443 mtctr r2
444 mtlr r0
445 lwz r2,_XER(r1)
446 lwz r0,_CCR(r1)
447 mtspr XER,r2
448 mtcrf 0xFF,r0
449 REST_10GPRS(3, r1)
450 REST_10GPRS(13, r1)
451 REST_8GPRS(23, r1)
452 REST_GPR(31, r1)
453 lwz r2,_NIP(r1) /* Restore environment */
454 lwz r0,_MSR(r1)
455 mtspr SRR0,r2
456 mtspr SRR1,r0
457 lwz r0,GPR0(r1)
458 lwz r2,GPR2(r1)
459 lwz r1,GPR1(r1)
460 SYNC
461 rfi
Scott Wood2b36fbb2012-12-06 13:33:17 +0000462#endif /* !MINIMAL_SPL */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500463
464/*
465 * This code initialises the E300 processor core
466 * (conforms to PowerPC 603e spec)
467 * Note: expects original MSR contents to be in r5.
468 */
469 .globl init_e300_core
470init_e300_core: /* time t 10 */
471 /* Initialize machine status; enable machine check interrupt */
472 /*-----------------------------------------------------------*/
473
474 li r3, MSR_KERNEL /* Set ME and RI flags */
475 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
476#ifdef DEBUG
477 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
478#endif
479 SYNC /* Some chip revs need this... */
480 mtmsr r3
481 SYNC
482 mtspr SRR1, r3 /* Make SRR1 match MSR */
483
484
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200485 lis r3, CONFIG_SYS_IMMR@h
Eran Liberty9095d4a2005-07-28 10:08:46 -0500486#if defined(CONFIG_WATCHDOG)
Horst Kronstorfer4565e042010-05-18 10:37:05 +0200487 /* Initialise the Watchdog values and reset it (if req) */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500488 /*------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200489 lis r4, CONFIG_SYS_WATCHDOG_VALUE
Eran Liberty9095d4a2005-07-28 10:08:46 -0500490 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
491 stw r4, SWCRR(r3)
Jon Loeligerebc72242005-08-01 13:20:47 -0500492
Eran Liberty9095d4a2005-07-28 10:08:46 -0500493 /* and reset it */
Jon Loeligerebc72242005-08-01 13:20:47 -0500494
Eran Liberty9095d4a2005-07-28 10:08:46 -0500495 li r4, 0x556C
496 sth r4, SWSRR@l(r3)
Heiko Schocher6dfb2e52008-01-11 15:15:17 +0100497 li r4, -0x55C7
Eran Liberty9095d4a2005-07-28 10:08:46 -0500498 sth r4, SWSRR@l(r3)
499#else
Horst Kronstorfer4565e042010-05-18 10:37:05 +0200500 /* Disable Watchdog */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500501 /*-------------------*/
Kumar Galab42751c2006-01-11 11:23:01 -0600502 lwz r4, SWCRR(r3)
503 /* Check to see if its enabled for disabling
504 once disabled by SW you can't re-enable */
505 andi. r4, r4, 0x4
506 beq 1f
Eran Liberty9095d4a2005-07-28 10:08:46 -0500507 xor r4, r4, r4
508 stw r4, SWCRR(r3)
Kumar Galab42751c2006-01-11 11:23:01 -06005091:
Eran Liberty9095d4a2005-07-28 10:08:46 -0500510#endif /* CONFIG_WATCHDOG */
511
Nick Spence56fd3c22008-08-28 14:09:19 -0700512#if defined(CONFIG_MASK_AER_AO)
513 /* Write the Arbiter Event Enable to mask Address Only traps. */
514 /* This prevents the dcbz instruction from being trapped when */
515 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
516 /* COHERENCY bit is set in the WIMG bits, which is often */
517 /* needed for PCI operation. */
518 lwz r4, 0x0808(r3)
519 rlwinm r0, r4, 0, ~AER_AO
520 stw r0, 0x0808(r3)
521#endif /* CONFIG_MASK_AER_AO */
522
Eran Liberty9095d4a2005-07-28 10:08:46 -0500523 /* Initialize the Hardware Implementation-dependent Registers */
524 /* HID0 also contains cache control */
Nick Spence7c20aef2008-08-28 14:09:25 -0700525 /* - force invalidation of data and instruction caches */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500526 /*------------------------------------------------------*/
527
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200528 lis r3, CONFIG_SYS_HID0_INIT@h
529 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500530 SYNC
531 mtspr HID0, r3
532
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200533 lis r3, CONFIG_SYS_HID0_FINAL@h
534 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500535 SYNC
536 mtspr HID0, r3
537
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200538 lis r3, CONFIG_SYS_HID2@h
539 ori r3, r3, CONFIG_SYS_HID2@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500540 SYNC
541 mtspr HID2, r3
542
Eran Liberty9095d4a2005-07-28 10:08:46 -0500543 /* Done! */
544 /*------------------------------*/
Jon Loeligerebc72242005-08-01 13:20:47 -0500545 blr
Eran Liberty9095d4a2005-07-28 10:08:46 -0500546
Kumar Galad5d94d62006-02-10 15:40:06 -0600547 /* setup_bats - set them up to some initial state */
548 .globl setup_bats
549setup_bats:
550 addis r0, r0, 0x0000
551
552 /* IBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200553 addis r4, r0, CONFIG_SYS_IBAT0L@h
554 ori r4, r4, CONFIG_SYS_IBAT0L@l
555 addis r3, r0, CONFIG_SYS_IBAT0U@h
556 ori r3, r3, CONFIG_SYS_IBAT0U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600557 mtspr IBAT0L, r4
558 mtspr IBAT0U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600559
560 /* DBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200561 addis r4, r0, CONFIG_SYS_DBAT0L@h
562 ori r4, r4, CONFIG_SYS_DBAT0L@l
563 addis r3, r0, CONFIG_SYS_DBAT0U@h
564 ori r3, r3, CONFIG_SYS_DBAT0U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600565 mtspr DBAT0L, r4
566 mtspr DBAT0U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600567
568 /* IBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200569 addis r4, r0, CONFIG_SYS_IBAT1L@h
570 ori r4, r4, CONFIG_SYS_IBAT1L@l
571 addis r3, r0, CONFIG_SYS_IBAT1U@h
572 ori r3, r3, CONFIG_SYS_IBAT1U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600573 mtspr IBAT1L, r4
574 mtspr IBAT1U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600575
576 /* DBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200577 addis r4, r0, CONFIG_SYS_DBAT1L@h
578 ori r4, r4, CONFIG_SYS_DBAT1L@l
579 addis r3, r0, CONFIG_SYS_DBAT1U@h
580 ori r3, r3, CONFIG_SYS_DBAT1U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600581 mtspr DBAT1L, r4
582 mtspr DBAT1U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600583
584 /* IBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200585 addis r4, r0, CONFIG_SYS_IBAT2L@h
586 ori r4, r4, CONFIG_SYS_IBAT2L@l
587 addis r3, r0, CONFIG_SYS_IBAT2U@h
588 ori r3, r3, CONFIG_SYS_IBAT2U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600589 mtspr IBAT2L, r4
590 mtspr IBAT2U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600591
592 /* DBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200593 addis r4, r0, CONFIG_SYS_DBAT2L@h
594 ori r4, r4, CONFIG_SYS_DBAT2L@l
595 addis r3, r0, CONFIG_SYS_DBAT2U@h
596 ori r3, r3, CONFIG_SYS_DBAT2U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600597 mtspr DBAT2L, r4
598 mtspr DBAT2U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600599
600 /* IBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200601 addis r4, r0, CONFIG_SYS_IBAT3L@h
602 ori r4, r4, CONFIG_SYS_IBAT3L@l
603 addis r3, r0, CONFIG_SYS_IBAT3U@h
604 ori r3, r3, CONFIG_SYS_IBAT3U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600605 mtspr IBAT3L, r4
606 mtspr IBAT3U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600607
608 /* DBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200609 addis r4, r0, CONFIG_SYS_DBAT3L@h
610 ori r4, r4, CONFIG_SYS_DBAT3L@l
611 addis r3, r0, CONFIG_SYS_DBAT3U@h
612 ori r3, r3, CONFIG_SYS_DBAT3U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600613 mtspr DBAT3L, r4
614 mtspr DBAT3U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600615
Becky Bruce03ea1be2008-05-08 19:02:12 -0500616#ifdef CONFIG_HIGH_BATS
Kumar Galad5d94d62006-02-10 15:40:06 -0600617 /* IBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200618 addis r4, r0, CONFIG_SYS_IBAT4L@h
619 ori r4, r4, CONFIG_SYS_IBAT4L@l
620 addis r3, r0, CONFIG_SYS_IBAT4U@h
621 ori r3, r3, CONFIG_SYS_IBAT4U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600622 mtspr IBAT4L, r4
623 mtspr IBAT4U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600624
625 /* DBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200626 addis r4, r0, CONFIG_SYS_DBAT4L@h
627 ori r4, r4, CONFIG_SYS_DBAT4L@l
628 addis r3, r0, CONFIG_SYS_DBAT4U@h
629 ori r3, r3, CONFIG_SYS_DBAT4U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600630 mtspr DBAT4L, r4
631 mtspr DBAT4U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600632
633 /* IBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200634 addis r4, r0, CONFIG_SYS_IBAT5L@h
635 ori r4, r4, CONFIG_SYS_IBAT5L@l
636 addis r3, r0, CONFIG_SYS_IBAT5U@h
637 ori r3, r3, CONFIG_SYS_IBAT5U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600638 mtspr IBAT5L, r4
639 mtspr IBAT5U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600640
641 /* DBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200642 addis r4, r0, CONFIG_SYS_DBAT5L@h
643 ori r4, r4, CONFIG_SYS_DBAT5L@l
644 addis r3, r0, CONFIG_SYS_DBAT5U@h
645 ori r3, r3, CONFIG_SYS_DBAT5U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600646 mtspr DBAT5L, r4
647 mtspr DBAT5U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600648
649 /* IBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200650 addis r4, r0, CONFIG_SYS_IBAT6L@h
651 ori r4, r4, CONFIG_SYS_IBAT6L@l
652 addis r3, r0, CONFIG_SYS_IBAT6U@h
653 ori r3, r3, CONFIG_SYS_IBAT6U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600654 mtspr IBAT6L, r4
655 mtspr IBAT6U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600656
657 /* DBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200658 addis r4, r0, CONFIG_SYS_DBAT6L@h
659 ori r4, r4, CONFIG_SYS_DBAT6L@l
660 addis r3, r0, CONFIG_SYS_DBAT6U@h
661 ori r3, r3, CONFIG_SYS_DBAT6U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600662 mtspr DBAT6L, r4
663 mtspr DBAT6U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600664
665 /* IBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200666 addis r4, r0, CONFIG_SYS_IBAT7L@h
667 ori r4, r4, CONFIG_SYS_IBAT7L@l
668 addis r3, r0, CONFIG_SYS_IBAT7U@h
669 ori r3, r3, CONFIG_SYS_IBAT7U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600670 mtspr IBAT7L, r4
671 mtspr IBAT7U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600672
673 /* DBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200674 addis r4, r0, CONFIG_SYS_DBAT7L@h
675 ori r4, r4, CONFIG_SYS_DBAT7L@l
676 addis r3, r0, CONFIG_SYS_DBAT7U@h
677 ori r3, r3, CONFIG_SYS_DBAT7U@l
Kumar Galad5d94d62006-02-10 15:40:06 -0600678 mtspr DBAT7L, r4
679 mtspr DBAT7U, r3
Kumar Galad5d94d62006-02-10 15:40:06 -0600680#endif
681
Scott Woodb71689b2008-06-30 14:13:28 -0500682 isync
683
684 /* invalidate all tlb's
685 *
686 * From the 603e User Manual: "The 603e provides the ability to
687 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
688 * instruction invalidates the TLB entry indexed by the EA, and
689 * operates on both the instruction and data TLBs simultaneously
690 * invalidating four TLB entries (both sets in each TLB). The
691 * index corresponds to bits 15-19 of the EA. To invalidate all
692 * entries within both TLBs, 32 tlbie instructions should be
693 * issued, incrementing this field by one each time."
694 *
695 * "Note that the tlbia instruction is not implemented on the
696 * 603e."
697 *
698 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
699 * incrementing by 0x1000 each time. The code below is sort of
Stefan Roese88fbf932010-04-15 16:07:28 +0200700 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
Scott Woodb71689b2008-06-30 14:13:28 -0500701 *
Kumar Galad5d94d62006-02-10 15:40:06 -0600702 */
703 lis r3, 0
704 lis r5, 2
705
7061:
707 tlbie r3
708 addi r3, r3, 0x1000
709 cmp 0, 0, r3, r5
710 blt 1b
711
712 blr
713
Eran Liberty9095d4a2005-07-28 10:08:46 -0500714/* Cache functions.
715 *
716 * Note: requires that all cache bits in
717 * HID0 are in the low half word.
718 */
Scott Wood2b36fbb2012-12-06 13:33:17 +0000719#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -0500720 .globl icache_enable
721icache_enable:
722 mfspr r3, HID0
723 ori r3, r3, HID0_ICE
Nick Spence7c20aef2008-08-28 14:09:25 -0700724 li r4, HID0_ICFI|HID0_ILOCK
Eran Liberty9095d4a2005-07-28 10:08:46 -0500725 andc r3, r3, r4
726 ori r4, r3, HID0_ICFI
727 isync
728 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
729 isync
730 mtspr HID0, r3 /* clears invalidate */
731 blr
732
733 .globl icache_disable
734icache_disable:
735 mfspr r3, HID0
736 lis r4, 0
Nick Spence7c20aef2008-08-28 14:09:25 -0700737 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
Eran Liberty9095d4a2005-07-28 10:08:46 -0500738 andc r3, r3, r4
Eran Liberty9095d4a2005-07-28 10:08:46 -0500739 isync
Nick Spence7c20aef2008-08-28 14:09:25 -0700740 mtspr HID0, r3 /* clears invalidate, enable and lock */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500741 blr
742
743 .globl icache_status
744icache_status:
745 mfspr r3, HID0
Marian Balakowicz758e5d32006-03-14 16:01:25 +0100746 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
Eran Liberty9095d4a2005-07-28 10:08:46 -0500747 blr
Scott Wood2b36fbb2012-12-06 13:33:17 +0000748#endif /* !MINIMAL_SPL */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500749
750 .globl dcache_enable
751dcache_enable:
752 mfspr r3, HID0
Kumar Galad5d94d62006-02-10 15:40:06 -0600753 li r5, HID0_DCFI|HID0_DLOCK
754 andc r3, r3, r5
Kumar Galad5d94d62006-02-10 15:40:06 -0600755 ori r3, r3, HID0_DCE
Eran Liberty9095d4a2005-07-28 10:08:46 -0500756 sync
Nick Spence7c20aef2008-08-28 14:09:25 -0700757 mtspr HID0, r3 /* enable, no invalidate */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500758 blr
759
760 .globl dcache_disable
761dcache_disable:
Nick Spence7c20aef2008-08-28 14:09:25 -0700762 mflr r4
763 bl flush_dcache /* uses r3 and r5 */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500764 mfspr r3, HID0
Nick Spence7c20aef2008-08-28 14:09:25 -0700765 li r5, HID0_DCE|HID0_DLOCK
766 andc r3, r3, r5
767 ori r5, r3, HID0_DCFI
Eran Liberty9095d4a2005-07-28 10:08:46 -0500768 sync
Nick Spence7c20aef2008-08-28 14:09:25 -0700769 mtspr HID0, r5 /* sets invalidate, clears enable and lock */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500770 sync
771 mtspr HID0, r3 /* clears invalidate */
Nick Spence7c20aef2008-08-28 14:09:25 -0700772 mtlr r4
Eran Liberty9095d4a2005-07-28 10:08:46 -0500773 blr
774
775 .globl dcache_status
776dcache_status:
777 mfspr r3, HID0
Marian Balakowicz758e5d32006-03-14 16:01:25 +0100778 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
Eran Liberty9095d4a2005-07-28 10:08:46 -0500779 blr
780
Nick Spence7c20aef2008-08-28 14:09:25 -0700781 .globl flush_dcache
782flush_dcache:
783 lis r3, 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200784 lis r5, CONFIG_SYS_CACHELINE_SIZE
Nick Spence7c20aef2008-08-28 14:09:25 -07007851: cmp 0, 1, r3, r5
786 bge 2f
787 lwz r5, 0(r3)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200788 lis r5, CONFIG_SYS_CACHELINE_SIZE
Nick Spence7c20aef2008-08-28 14:09:25 -0700789 addi r3, r3, 0x4
790 b 1b
7912: blr
792
Eran Liberty9095d4a2005-07-28 10:08:46 -0500793/*-------------------------------------------------------------------*/
794
795/*
Simon Glass284f71b2019-12-28 10:44:45 -0700796 * void relocate_code(addr_sp, gd, addr_moni)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500797 *
798 * This "function" does not return, instead it continues in RAM
799 * after relocating the monitor code.
800 *
801 * r3 = dest
802 * r4 = src
803 * r5 = length in bytes
804 * r6 = cachelinesize
805 */
806 .globl relocate_code
807relocate_code:
808 mr r1, r3 /* Set new stack pointer */
809 mr r9, r4 /* Save copy of Global Data pointer */
810 mr r10, r5 /* Save copy of Destination Address */
811
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100812 GET_GOT
Eran Liberty9095d4a2005-07-28 10:08:46 -0500813 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200814 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
815 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
Scott Woodb71689b2008-06-30 14:13:28 -0500816 lwz r5, GOT(__bss_start)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500817 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200818 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500819
820 /*
821 * Fix GOT pointer:
822 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200823 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500824 * + Destination Address
825 *
826 * Offset:
827 */
828 sub r15, r10, r4
829
830 /* First our own GOT */
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100831 add r12, r12, r15
Eran Liberty9095d4a2005-07-28 10:08:46 -0500832 /* then the one used by the C code */
833 add r30, r30, r15
834
835 /*
836 * Now relocate code
837 */
838
839 cmplw cr1,r3,r4
840 addi r0,r5,3
841 srwi. r0,r0,2
842 beq cr1,4f /* In place copy is not necessary */
843 beq 7f /* Protect against 0 count */
844 mtctr r0
845 bge cr1,2f
846 la r8,-4(r4)
847 la r7,-4(r3)
848
849 /* copy */
8501: lwzu r0,4(r8)
851 stwu r0,4(r7)
852 bdnz 1b
853
854 addi r0,r5,3
855 srwi. r0,r0,2
856 mtctr r0
857 la r8,-4(r4)
858 la r7,-4(r3)
Jon Loeligerebc72242005-08-01 13:20:47 -0500859
860 /* and compare */
Eran Liberty9095d4a2005-07-28 10:08:46 -050086120: lwzu r20,4(r8)
862 lwzu r21,4(r7)
863 xor. r22, r20, r21
864 bne 30f
865 bdnz 20b
866 b 4f
867
868 /* compare failed */
86930: li r3, 0
870 blr
871
8722: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
873 add r8,r4,r0
874 add r7,r3,r0
8753: lwzu r0,-4(r8)
876 stwu r0,-4(r7)
877 bdnz 3b
Eran Liberty9095d4a2005-07-28 10:08:46 -0500878
879/*
880 * Now flush the cache: note that we must start from a cache aligned
881 * address. Otherwise we might miss one cache line.
882 */
Kumar Galad5d94d62006-02-10 15:40:06 -06008834: cmpwi r6,0
Eran Liberty9095d4a2005-07-28 10:08:46 -0500884 add r5,r3,r5
Kumar Galad5d94d62006-02-10 15:40:06 -0600885 beq 7f /* Always flush prefetch queue in any case */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500886 subi r0,r6,1
887 andc r3,r3,r0
Eran Liberty9095d4a2005-07-28 10:08:46 -0500888 mr r4,r3
8895: dcbst 0,r4
890 add r4,r4,r6
891 cmplw r4,r5
892 blt 5b
Kumar Galad5d94d62006-02-10 15:40:06 -0600893 sync /* Wait for all dcbst to complete on bus */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500894 mr r4,r3
8956: icbi 0,r4
896 add r4,r4,r6
897 cmplw r4,r5
898 blt 6b
Kumar Galad5d94d62006-02-10 15:40:06 -06008997: sync /* Wait for all icbi to complete on bus */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500900 isync
901
902/*
903 * We are done. Do not return, instead branch to second part of board
904 * initialization, now running from RAM.
905 */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500906 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
907 mtlr r0
908 blr
909
910in_ram:
911
912 /*
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100913 * Relocation Function, r12 point to got2+0x8000
Eran Liberty9095d4a2005-07-28 10:08:46 -0500914 *
915 * Adjust got2 pointers, no need to check for 0, this code
916 * already puts a few entries in the table.
917 */
918 li r0,__got2_entries@sectoff@l
919 la r3,GOT(_GOT2_TABLE_)
920 lwz r11,GOT(_GOT2_TABLE_)
921 mtctr r0
922 sub r11,r3,r11
923 addi r3,r3,-4
9241: lwzu r0,4(r3)
Joakim Tjernlund4f2fdac2009-10-08 02:03:51 +0200925 cmpwi r0,0
926 beq- 2f
Eran Liberty9095d4a2005-07-28 10:08:46 -0500927 add r0,r0,r11
928 stw r0,0(r3)
Joakim Tjernlund4f2fdac2009-10-08 02:03:51 +02009292: bdnz 1b
Eran Liberty9095d4a2005-07-28 10:08:46 -0500930
Scott Wood2b36fbb2012-12-06 13:33:17 +0000931#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -0500932 /*
933 * Now adjust the fixups and the pointers to the fixups
934 * in case we need to move ourselves again.
935 */
Joakim Tjernlund4f2fdac2009-10-08 02:03:51 +0200936 li r0,__fixup_entries@sectoff@l
Eran Liberty9095d4a2005-07-28 10:08:46 -0500937 lwz r3,GOT(_FIXUP_TABLE_)
938 cmpwi r0,0
939 mtctr r0
940 addi r3,r3,-4
941 beq 4f
9423: lwzu r4,4(r3)
943 lwzux r0,r4,r11
Joakim Tjernlundc61b25a2010-10-14 11:51:44 +0200944 cmpwi r0,0
Eran Liberty9095d4a2005-07-28 10:08:46 -0500945 add r0,r0,r11
Joakim Tjernlund401b5922010-11-04 19:02:00 +0100946 stw r4,0(r3)
Joakim Tjernlundc61b25a2010-10-14 11:51:44 +0200947 beq- 5f
Eran Liberty9095d4a2005-07-28 10:08:46 -0500948 stw r0,0(r4)
Joakim Tjernlundc61b25a2010-10-14 11:51:44 +02009495: bdnz 3b
Eran Liberty9095d4a2005-07-28 10:08:46 -05009504:
Scott Woodb71689b2008-06-30 14:13:28 -0500951#endif
952
Eran Liberty9095d4a2005-07-28 10:08:46 -0500953clear_bss:
954 /*
955 * Now clear BSS segment
956 */
957 lwz r3,GOT(__bss_start)
Simon Glassed70c8f2013-03-14 06:54:53 +0000958 lwz r4,GOT(__bss_end)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500959
960 cmplw 0, r3, r4
961 beq 6f
962
963 li r0, 0
9645:
965 stw r0, 0(r3)
966 addi r3, r3, 4
967 cmplw 0, r3, r4
968 bne 5b
9696:
970
971 mr r3, r9 /* Global Data pointer */
972 mr r4, r10 /* Destination Address */
973 bl board_init_r
974
Scott Wood2b36fbb2012-12-06 13:33:17 +0000975#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -0500976 /*
977 * Copy exception vector code to low memory
978 *
979 * r3: dest_addr
980 * r7: source address, r8: end address, r9: target address
981 */
982 .globl trap_init
983trap_init:
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100984 mflr r4 /* save link register */
985 GET_GOT
Eran Liberty9095d4a2005-07-28 10:08:46 -0500986 lwz r7, GOT(_start)
987 lwz r8, GOT(_end_of_vectors)
988
989 li r9, 0x100 /* reset vector always at 0x100 */
990
991 cmplw 0, r7, r8
992 bgelr /* return if r7>=r8 - just in case */
Eran Liberty9095d4a2005-07-28 10:08:46 -05009931:
994 lwz r0, 0(r7)
995 stw r0, 0(r9)
996 addi r7, r7, 4
997 addi r9, r9, 4
998 cmplw 0, r7, r8
999 bne 1b
1000
1001 /*
1002 * relocate `hdlr' and `int_return' entries
1003 */
1004 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1005 li r8, Alignment - _start + EXC_OFF_SYS_RESET
10062:
1007 bl trap_reloc
1008 addi r7, r7, 0x100 /* next exception vector */
1009 cmplw 0, r7, r8
1010 blt 2b
1011
1012 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1013 bl trap_reloc
1014
1015 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1016 bl trap_reloc
1017
1018 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1019 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
10203:
1021 bl trap_reloc
1022 addi r7, r7, 0x100 /* next exception vector */
1023 cmplw 0, r7, r8
1024 blt 3b
1025
1026 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1027 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
10284:
1029 bl trap_reloc
1030 addi r7, r7, 0x100 /* next exception vector */
1031 cmplw 0, r7, r8
1032 blt 4b
1033
1034 mfmsr r3 /* now that the vectors have */
1035 lis r7, MSR_IP@h /* relocated into low memory */
1036 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1037 andc r3, r3, r7 /* (if it was on) */
1038 SYNC /* Some chip revs need this... */
1039 mtmsr r3
1040 SYNC
1041
1042 mtlr r4 /* restore link register */
1043 blr
1044
Scott Wood2b36fbb2012-12-06 13:33:17 +00001045#endif /* !MINIMAL_SPL */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001046
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001047#ifdef CONFIG_SYS_INIT_RAM_LOCK
Kumar Galad5d94d62006-02-10 15:40:06 -06001048lock_ram_in_cache:
1049 /* Allocate Initial RAM in data cache.
1050 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001051 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1052 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +02001053 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001054 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spenceb89d6fb2008-08-28 14:09:11 -07001055 mtctr r4
Kumar Galad5d94d62006-02-10 15:40:06 -060010561:
1057 dcbz r0, r3
1058 addi r3, r3, 32
1059 bdnz 1b
1060
1061 /* Lock the data cache */
1062 mfspr r0, HID0
Nick Spence7c20aef2008-08-28 14:09:25 -07001063 ori r0, r0, HID0_DLOCK
Kumar Galad5d94d62006-02-10 15:40:06 -06001064 sync
1065 mtspr HID0, r0
1066 sync
1067 blr
1068
Scott Wood2b36fbb2012-12-06 13:33:17 +00001069#ifndef MINIMAL_SPL
Eran Liberty9095d4a2005-07-28 10:08:46 -05001070.globl unlock_ram_in_cache
1071unlock_ram_in_cache:
1072 /* invalidate the INIT_RAM section */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001073 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1074 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +02001075 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001076 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spenceb89d6fb2008-08-28 14:09:11 -07001077 mtctr r4
Eran Liberty9095d4a2005-07-28 10:08:46 -050010781: icbi r0, r3
1079 dcbi r0, r3
1080 addi r3, r3, 32
1081 bdnz 1b
1082 sync /* Wait for all icbi to complete on bus */
1083 isync
Kumar Galad5d94d62006-02-10 15:40:06 -06001084
1085 /* Unlock the data cache and invalidate it */
1086 mfspr r3, HID0
1087 li r5, HID0_DLOCK|HID0_DCFI
1088 andc r3, r3, r5 /* no invalidate, unlock */
1089 ori r5, r3, HID0_DCFI /* invalidate, unlock */
Nick Spence7c20aef2008-08-28 14:09:25 -07001090 sync
Kumar Galad5d94d62006-02-10 15:40:06 -06001091 mtspr HID0, r5 /* invalidate, unlock */
Kumar Galad5d94d62006-02-10 15:40:06 -06001092 sync
Nick Spence7c20aef2008-08-28 14:09:25 -07001093 mtspr HID0, r3 /* no invalidate, unlock */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001094 blr
Scott Wood2b36fbb2012-12-06 13:33:17 +00001095#endif /* !MINIMAL_SPL */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001096#endif /* CONFIG_SYS_INIT_RAM_LOCK */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001097
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001098#ifdef CONFIG_SYS_FLASHBOOT
Eran Liberty9095d4a2005-07-28 10:08:46 -05001099map_flash_by_law1:
1100 /* When booting from ROM (Flash or EPROM), clear the */
1101 /* Address Mask in OR0 so ROM appears everywhere */
1102 /*----------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001103 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
Jon Loeligerebc72242005-08-01 13:20:47 -05001104 lwz r4, OR0@l(r3)
Eran Liberty9095d4a2005-07-28 10:08:46 -05001105 li r5, 0x7fff /* r5 <= 0x00007FFFF */
Jon Loeligerebc72242005-08-01 13:20:47 -05001106 and r4, r4, r5
Eran Liberty9095d4a2005-07-28 10:08:46 -05001107 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1108
1109 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1110 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1111 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1112 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1113 * 0xFF800. From the hard resetting to here, the processor fetched and
1114 * executed the instructions one by one. There is not absolutely
1115 * jumping happened. Laterly, the u-boot code has to do an absolutely
1116 * jumping to tell the CPU instruction fetching component what the
1117 * u-boot TEXT base address is. Because the TEXT base resides in the
1118 * boot ROM memory space, to garantee the code can run smoothly after
1119 * that jumping, we must map in the entire boot ROM by Local Access
1120 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1121 * address for boot ROM, such as 0xFE000000. In this case, the default
1122 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1123 * need another window to map in it.
1124 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001125 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1126 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1127 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
Timur Tabi53b46172006-08-22 17:07:00 -05001128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001129 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
Timur Tabi53b46172006-08-22 17:07:00 -05001130 lis r4, (0x80000012)@h
1131 ori r4, r4, (0x80000012)@l
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001132 li r5, CONFIG_SYS_FLASH_SIZE
Timur Tabi53b46172006-08-22 17:07:00 -050011331: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1134 addi r4, r4, 1
1135 bne 1b
1136
Eran Liberty9095d4a2005-07-28 10:08:46 -05001137 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
Joakim Tjernlundb168d632010-11-19 14:15:33 +01001138 /* Wait for HW to catch up */
1139 lwz r4, LBLAWAR1(r3)
1140 twi 0,r4,0
1141 isync
Eran Liberty9095d4a2005-07-28 10:08:46 -05001142 blr
1143
1144 /* Though all the LBIU Local Access Windows and LBC Banks will be
1145 * initialized in the C code, we'd better configure boot ROM's
1146 * window 0 and bank 0 correctly at here.
1147 */
1148remap_flash_by_law0:
1149 /* Initialize the BR0 with the boot ROM starting address. */
1150 lwz r4, BR0(r3)
1151 li r5, 0x7FFF
Jon Loeligerebc72242005-08-01 13:20:47 -05001152 and r4, r4, r5
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001153 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1154 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
Eran Liberty9095d4a2005-07-28 10:08:46 -05001155 or r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001156 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001157
1158 lwz r4, OR0(r3)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001159 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
Eran Liberty9095d4a2005-07-28 10:08:46 -05001160 or r4, r4, r5
Timur Tabi53b46172006-08-22 17:07:00 -05001161 stw r4, OR0(r3)
Eran Liberty9095d4a2005-07-28 10:08:46 -05001162
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001163 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1164 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1165 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
Eran Liberty9095d4a2005-07-28 10:08:46 -05001166
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001167 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
Timur Tabi53b46172006-08-22 17:07:00 -05001168 lis r4, (0x80000012)@h
1169 ori r4, r4, (0x80000012)@l
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001170 li r5, CONFIG_SYS_FLASH_SIZE
Timur Tabi53b46172006-08-22 17:07:00 -050011711: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1172 addi r4, r4, 1
1173 bne 1b
1174 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1175
Eran Liberty9095d4a2005-07-28 10:08:46 -05001176
1177 xor r4, r4, r4
1178 stw r4, LBLAWBAR1(r3)
1179 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
Joakim Tjernlundb168d632010-11-19 14:15:33 +01001180 /* Wait for HW to catch up */
1181 lwz r4, LBLAWAR1(r3)
1182 twi 0,r4,0
1183 isync
Eran Liberty9095d4a2005-07-28 10:08:46 -05001184 blr
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02001185#endif /* CONFIG_SYS_FLASHBOOT */