Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | /* |
| 3 | * Copyright (C) 2019 Marek Vasut <marex@denx.de> |
| 4 | */ |
| 5 | |
| 6 | #include <dt-bindings/clock/stm32mp1-clksrc.h> |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 7 | #include "stm32mp15-u-boot.dtsi" |
Marek Vasut | 272198e | 2020-04-29 15:08:38 +0200 | [diff] [blame] | 8 | #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi" |
| 9 | #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi" |
| 10 | #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 11 | |
| 12 | / { |
| 13 | aliases { |
| 14 | i2c1 = &i2c2; |
| 15 | i2c3 = &i2c4; |
| 16 | i2c4 = &i2c5; |
| 17 | mmc0 = &sdmmc1; |
| 18 | mmc1 = &sdmmc2; |
| 19 | spi0 = &qspi; |
| 20 | usb0 = &usbotg_hs; |
Marek Vasut | 7d2757f | 2021-12-30 23:46:47 +0100 | [diff] [blame] | 21 | eeprom0 = &eeprom0; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 22 | }; |
| 23 | |
| 24 | config { |
| 25 | u-boot,boot-led = "heartbeat"; |
| 26 | u-boot,error-led = "error"; |
Marek Vasut | 47b98ba | 2020-04-22 13:18:11 +0200 | [diff] [blame] | 27 | dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>; |
Marek Vasut | 39221b5 | 2020-04-22 13:18:14 +0200 | [diff] [blame] | 28 | dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 29 | }; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 30 | }; |
| 31 | |
Marek Vasut | 7d2757f | 2021-12-30 23:46:47 +0100 | [diff] [blame] | 32 | ðernet0 { |
| 33 | phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; |
| 34 | /delete-property/ st,eth-ref-clk-sel; |
| 35 | }; |
| 36 | |
| 37 | ðernet0_rmii_pins_a { |
| 38 | pins1 { |
| 39 | pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ |
| 40 | <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ |
| 41 | <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ |
| 42 | <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ |
| 43 | <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ |
| 44 | <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ |
| 45 | }; |
| 46 | }; |
| 47 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 48 | &i2c4 { |
| 49 | u-boot,dm-pre-reloc; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 50 | u-boot,dm-spl; |
Marek Vasut | 7d2757f | 2021-12-30 23:46:47 +0100 | [diff] [blame] | 51 | |
| 52 | eeprom0: eeprom@50 { |
| 53 | }; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 54 | }; |
| 55 | |
| 56 | &i2c4_pins_a { |
| 57 | u-boot,dm-pre-reloc; |
| 58 | pins { |
| 59 | u-boot,dm-pre-reloc; |
| 60 | }; |
| 61 | }; |
| 62 | |
Marek Vasut | 7d2757f | 2021-12-30 23:46:47 +0100 | [diff] [blame] | 63 | &phy0 { |
| 64 | /delete-property/ reset-gpios; |
| 65 | }; |
| 66 | |
Marek Vasut | 0839ea9 | 2020-03-28 02:01:58 +0100 | [diff] [blame] | 67 | &pinctrl { |
Marek Vasut | ccfcde3 | 2020-12-01 11:34:48 +0100 | [diff] [blame] | 68 | mco2_pins_a: mco2-0 { |
| 69 | pins { |
| 70 | pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ |
| 71 | bias-disable; |
| 72 | drive-push-pull; |
| 73 | slew-rate = <2>; |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | mco2_sleep_pins_a: mco2-sleep-0 { |
| 78 | pins { |
| 79 | pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ |
| 80 | }; |
| 81 | }; |
Marek Vasut | 0839ea9 | 2020-03-28 02:01:58 +0100 | [diff] [blame] | 82 | }; |
| 83 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 84 | &pmic { |
| 85 | u-boot,dm-pre-reloc; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 86 | u-boot,dm-spl; |
| 87 | |
| 88 | regulators { |
| 89 | u-boot,dm-spl; |
| 90 | }; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 91 | }; |
| 92 | |
| 93 | &flash0 { |
| 94 | u-boot,dm-spl; |
| 95 | }; |
| 96 | |
| 97 | &qspi { |
| 98 | u-boot,dm-spl; |
| 99 | }; |
| 100 | |
| 101 | &qspi_clk_pins_a { |
| 102 | u-boot,dm-spl; |
| 103 | pins { |
| 104 | u-boot,dm-spl; |
| 105 | }; |
| 106 | }; |
| 107 | |
| 108 | &qspi_bk1_pins_a { |
| 109 | u-boot,dm-spl; |
| 110 | pins1 { |
| 111 | u-boot,dm-spl; |
| 112 | }; |
| 113 | pins2 { |
| 114 | u-boot,dm-spl; |
| 115 | }; |
| 116 | }; |
| 117 | |
| 118 | &qspi_bk2_pins_a { |
| 119 | u-boot,dm-spl; |
| 120 | pins1 { |
| 121 | u-boot,dm-spl; |
| 122 | }; |
| 123 | pins2 { |
| 124 | u-boot,dm-spl; |
| 125 | }; |
| 126 | }; |
| 127 | |
| 128 | &rcc { |
| 129 | st,clksrc = < |
| 130 | CLK_MPU_PLL1P |
| 131 | CLK_AXI_PLL2P |
| 132 | CLK_MCU_PLL3P |
| 133 | CLK_PLL12_HSE |
| 134 | CLK_PLL3_HSE |
| 135 | CLK_PLL4_HSE |
| 136 | CLK_RTC_LSE |
| 137 | CLK_MCO1_DISABLED |
Marek Vasut | ccfcde3 | 2020-12-01 11:34:48 +0100 | [diff] [blame] | 138 | CLK_MCO2_PLL4P |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 139 | >; |
| 140 | |
| 141 | st,clkdiv = < |
| 142 | 1 /*MPU*/ |
| 143 | 0 /*AXI*/ |
| 144 | 0 /*MCU*/ |
| 145 | 1 /*APB1*/ |
| 146 | 1 /*APB2*/ |
| 147 | 1 /*APB3*/ |
| 148 | 1 /*APB4*/ |
| 149 | 2 /*APB5*/ |
| 150 | 23 /*RTC*/ |
| 151 | 0 /*MCO1*/ |
Marek Vasut | ccfcde3 | 2020-12-01 11:34:48 +0100 | [diff] [blame] | 152 | 1 /*MCO2*/ |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 153 | >; |
| 154 | |
| 155 | st,pkcs = < |
| 156 | CLK_CKPER_HSE |
| 157 | CLK_FMC_ACLK |
| 158 | CLK_QSPI_ACLK |
| 159 | CLK_ETH_PLL4P |
| 160 | CLK_SDMMC12_PLL4P |
| 161 | CLK_DSI_DSIPLL |
| 162 | CLK_STGEN_HSE |
| 163 | CLK_USBPHY_HSE |
| 164 | CLK_SPI2S1_PLL3Q |
| 165 | CLK_SPI2S23_PLL3Q |
| 166 | CLK_SPI45_HSI |
| 167 | CLK_SPI6_HSI |
| 168 | CLK_I2C46_HSI |
| 169 | CLK_SDMMC3_PLL4P |
| 170 | CLK_USBO_USBPHY |
| 171 | CLK_ADC_CKPER |
| 172 | CLK_CEC_LSE |
| 173 | CLK_I2C12_HSI |
| 174 | CLK_I2C35_HSI |
| 175 | CLK_UART1_HSI |
| 176 | CLK_UART24_HSI |
| 177 | CLK_UART35_HSI |
| 178 | CLK_UART6_HSI |
| 179 | CLK_UART78_HSI |
| 180 | CLK_SPDIF_PLL4P |
Antonio Borneo | 84159e8 | 2020-01-28 10:11:01 +0100 | [diff] [blame] | 181 | CLK_FDCAN_PLL4R |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 182 | CLK_SAI1_PLL3Q |
| 183 | CLK_SAI2_PLL3Q |
| 184 | CLK_SAI3_PLL3Q |
| 185 | CLK_SAI4_PLL3Q |
| 186 | CLK_RNG1_LSI |
| 187 | CLK_RNG2_LSI |
| 188 | CLK_LPTIM1_PCLK1 |
| 189 | CLK_LPTIM23_PCLK3 |
| 190 | CLK_LPTIM45_LSE |
| 191 | >; |
| 192 | |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 193 | /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ |
| 194 | pll2: st,pll@1 { |
Patrick Delaunay | c22caac | 2020-01-28 10:11:03 +0100 | [diff] [blame] | 195 | compatible = "st,stm32mp1-pll"; |
| 196 | reg = <1>; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 197 | cfg = < 2 65 1 0 0 PQR(1,1,1) >; |
| 198 | frac = < 0x1400 >; |
| 199 | u-boot,dm-pre-reloc; |
| 200 | }; |
| 201 | |
| 202 | /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ |
| 203 | pll3: st,pll@2 { |
Patrick Delaunay | c22caac | 2020-01-28 10:11:03 +0100 | [diff] [blame] | 204 | compatible = "st,stm32mp1-pll"; |
| 205 | reg = <2>; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 206 | cfg = < 1 33 1 16 36 PQR(1,1,1) >; |
| 207 | frac = < 0x1a04 >; |
| 208 | u-boot,dm-pre-reloc; |
| 209 | }; |
| 210 | |
| 211 | /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */ |
| 212 | pll4: st,pll@3 { |
Patrick Delaunay | c22caac | 2020-01-28 10:11:03 +0100 | [diff] [blame] | 213 | compatible = "st,stm32mp1-pll"; |
| 214 | reg = <3>; |
Marek Vasut | ccfcde3 | 2020-12-01 11:34:48 +0100 | [diff] [blame] | 215 | cfg = < 1 49 5 11 11 PQR(1,1,1) >; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 216 | u-boot,dm-pre-reloc; |
| 217 | }; |
| 218 | }; |
| 219 | |
| 220 | &sdmmc1 { |
| 221 | u-boot,dm-spl; |
Marek Vasut | 5f5ce60 | 2021-11-13 03:29:44 +0100 | [diff] [blame] | 222 | st,use-ckin; |
| 223 | st,cmd-gpios = <&gpiod 2 0>; |
| 224 | st,ck-gpios = <&gpioc 12 0>; |
| 225 | st,ckin-gpios = <&gpioe 4 0>; |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 226 | }; |
| 227 | |
| 228 | &sdmmc1_b4_pins_a { |
| 229 | u-boot,dm-spl; |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 230 | pins1 { |
| 231 | u-boot,dm-spl; |
| 232 | }; |
| 233 | pins2 { |
Marek Vasut | 5ff0529 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 234 | u-boot,dm-spl; |
| 235 | }; |
| 236 | }; |
| 237 | |
| 238 | &sdmmc1_dir_pins_a { |
| 239 | u-boot,dm-spl; |
| 240 | pins1 { |
| 241 | u-boot,dm-spl; |
| 242 | }; |
| 243 | pins2 { |
| 244 | u-boot,dm-spl; |
| 245 | }; |
| 246 | }; |
| 247 | |
| 248 | &sdmmc2 { |
| 249 | u-boot,dm-spl; |
| 250 | }; |
| 251 | |
| 252 | &sdmmc2_b4_pins_a { |
| 253 | u-boot,dm-spl; |
| 254 | pins { |
| 255 | u-boot,dm-spl; |
| 256 | }; |
| 257 | }; |
| 258 | |
| 259 | &sdmmc2_d47_pins_a { |
| 260 | u-boot,dm-spl; |
| 261 | pins { |
| 262 | u-boot,dm-spl; |
| 263 | }; |
| 264 | }; |
| 265 | |
| 266 | &uart4 { |
| 267 | u-boot,dm-pre-reloc; |
| 268 | }; |
| 269 | |
| 270 | &uart4_pins_a { |
| 271 | u-boot,dm-pre-reloc; |
| 272 | pins1 { |
| 273 | u-boot,dm-pre-reloc; |
| 274 | }; |
| 275 | pins2 { |
| 276 | u-boot,dm-pre-reloc; |
| 277 | /* pull-up on rx to avoid floating level */ |
| 278 | bias-pull-up; |
| 279 | }; |
| 280 | }; |
Marek Vasut | 8b64230 | 2022-03-14 13:35:54 +0100 | [diff] [blame] | 281 | |
| 282 | ®11 { |
| 283 | u-boot,dm-spl; |
| 284 | }; |
| 285 | |
| 286 | ®18 { |
| 287 | u-boot,dm-spl; |
| 288 | }; |
| 289 | |
| 290 | &usb33 { |
| 291 | u-boot,dm-spl; |
| 292 | }; |
| 293 | |
| 294 | &usbotg_hs_pins_a { |
| 295 | u-boot,dm-spl; |
| 296 | }; |
| 297 | |
| 298 | &usbotg_hs { |
| 299 | u-boot,dm-spl; |
| 300 | }; |
| 301 | |
| 302 | &usbphyc { |
| 303 | u-boot,dm-spl; |
| 304 | }; |
| 305 | |
| 306 | &usbphyc_port0 { |
| 307 | u-boot,dm-spl; |
| 308 | }; |
| 309 | |
| 310 | &usbphyc_port1 { |
| 311 | u-boot,dm-spl; |
| 312 | }; |
| 313 | |
| 314 | &vdd_usb { |
| 315 | u-boot,dm-spl; |
| 316 | }; |