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Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +01005#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04006#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05307#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01008
Simon Glassb2c1cac2014-02-26 15:59:21 -07009/ {
10 model = "sandbox";
11 compatible = "sandbox";
12 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060013 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070014
Simon Glassfef72b72014-07-23 06:55:03 -060015 aliases {
16 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010017 ethernet0 = "/eth@10002000";
18 ethernet2 = &swp_0;
19 ethernet3 = &eth_3;
20 ethernet4 = &dsa_eth0;
21 ethernet5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060022 gpio1 = &gpio_a;
23 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010024 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070025 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060026 mmc0 = "/mmc0";
27 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070028 pci0 = &pci0;
29 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070030 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020031 remoteproc0 = &rproc_1;
32 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060033 rtc0 = &rtc_0;
34 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060035 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020036 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070037 testbus3 = "/some-bus";
38 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070039 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070040 testfdt3 = "/b-test";
41 testfdt5 = "/some-bus/c-test@5";
42 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070043 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020044 fdt-dummy0 = "/translation-test@8000/dev@0,0";
45 fdt-dummy1 = "/translation-test@8000/dev@1,100";
46 fdt-dummy2 = "/translation-test@8000/dev@2,200";
47 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060048 usb0 = &usb_0;
49 usb1 = &usb_1;
50 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020051 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020052 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060053 };
54
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020055 config {
56 environment {
57 from_fdt = "yes";
58 fdt_env_path = "";
59 };
60 };
61
Nandor Han6521e5d2021-06-10 16:56:44 +030062 reboot-mode0 {
63 compatible = "reboot-mode-gpio";
64 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
65 u-boot,env-variable = "bootstatus";
66 mode-test = <0x01>;
67 mode-download = <0x03>;
68 };
69
Simon Glassed96cde2018-12-10 10:37:33 -070070 audio: audio-codec {
71 compatible = "sandbox,audio-codec";
72 #sound-dai-cells = <1>;
73 };
74
Philippe Reynes1ee26482020-07-24 18:19:51 +020075 buttons {
76 compatible = "gpio-keys";
77
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020078 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020079 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020080 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020081 };
82
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020083 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020084 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020085 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020086 };
87 };
88
Marek Szyprowskiad398592021-02-18 11:33:18 +010089 buttons2 {
90 compatible = "adc-keys";
91 io-channels = <&adc 3>;
92 keyup-threshold-microvolt = <3000000>;
93
94 button-up {
95 label = "button3";
96 linux,code = <KEY_F3>;
97 press-threshold-microvolt = <1500000>;
98 };
99
100 button-down {
101 label = "button4";
102 linux,code = <KEY_F4>;
103 press-threshold-microvolt = <1000000>;
104 };
105
106 button-enter {
107 label = "button5";
108 linux,code = <KEY_F5>;
109 press-threshold-microvolt = <500000>;
110 };
111 };
112
Simon Glassc953aaf2018-12-10 10:37:34 -0700113 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600114 reg = <0 0>;
115 compatible = "google,cros-ec-sandbox";
116
117 /*
118 * This describes the flash memory within the EC. Note
119 * that the STM32L flash erases to 0, not 0xff.
120 */
121 flash {
122 image-pos = <0x08000000>;
123 size = <0x20000>;
124 erase-value = <0>;
125
126 /* Information for sandbox */
127 ro {
128 image-pos = <0>;
129 size = <0xf000>;
130 };
131 wp-ro {
132 image-pos = <0xf000>;
133 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700134 used = <0x884>;
135 compress = "lz4";
136 uncomp-size = <0xcf8>;
137 hash {
138 algo = "sha256";
139 value = [00 01 02 03 04 05 06 07
140 08 09 0a 0b 0c 0d 0e 0f
141 10 11 12 13 14 15 16 17
142 18 19 1a 1b 1c 1d 1e 1f];
143 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600144 };
145 rw {
146 image-pos = <0x10000>;
147 size = <0x10000>;
148 };
149 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300150
151 cros_ec_pwm: cros-ec-pwm {
152 compatible = "google,cros-ec-pwm";
153 #pwm-cells = <1>;
154 };
155
Simon Glass699c9ca2018-10-01 12:22:08 -0600156 };
157
Yannick Fertré9712c822019-10-07 15:29:05 +0200158 dsi_host: dsi_host {
159 compatible = "sandbox,dsi-host";
160 };
161
Simon Glassb2c1cac2014-02-26 15:59:21 -0700162 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600163 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700164 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600165 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700166 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600167 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100168 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
169 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700170 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100171 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
172 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
173 <&gpio_b 7 GPIO_IN 3 2 1>,
174 <&gpio_b 8 GPIO_OUT 3 2 1>,
175 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100176 test3-gpios =
177 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
178 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
179 <&gpio_c 2 GPIO_OUT>,
180 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
181 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200182 <&gpio_c 5 GPIO_IN>,
183 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
184 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530185 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
186 test5-gpios = <&gpio_a 19>;
187
Simon Glass6df01f92018-12-10 10:37:37 -0700188 int-value = <1234>;
189 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200190 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200191 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600192 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700193 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600194 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200195 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530196
197 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
198 <&muxcontroller0 2>, <&muxcontroller0 3>,
199 <&muxcontroller1>;
200 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
201 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100202 display-timings {
203 timing0: 240x320 {
204 clock-frequency = <6500000>;
205 hactive = <240>;
206 vactive = <320>;
207 hfront-porch = <6>;
208 hback-porch = <7>;
209 hsync-len = <1>;
210 vback-porch = <5>;
211 vfront-porch = <8>;
212 vsync-len = <2>;
213 hsync-active = <1>;
214 vsync-active = <0>;
215 de-active = <1>;
216 pixelclk-active = <1>;
217 interlaced;
218 doublescan;
219 doubleclk;
220 };
221 timing1: 480x800 {
222 clock-frequency = <9000000>;
223 hactive = <480>;
224 vactive = <800>;
225 hfront-porch = <10>;
226 hback-porch = <59>;
227 hsync-len = <12>;
228 vback-porch = <15>;
229 vfront-porch = <17>;
230 vsync-len = <16>;
231 hsync-active = <0>;
232 vsync-active = <1>;
233 de-active = <0>;
234 pixelclk-active = <0>;
235 };
236 timing2: 800x480 {
237 clock-frequency = <33500000>;
238 hactive = <800>;
239 vactive = <480>;
240 hback-porch = <89>;
241 hfront-porch = <164>;
242 vback-porch = <23>;
243 vfront-porch = <10>;
244 hsync-len = <11>;
245 vsync-len = <13>;
246 };
247 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700248 };
249
250 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600251 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700252 compatible = "not,compatible";
253 };
254
255 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600256 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700257 };
258
Simon Glass5620cf82018-10-01 12:22:40 -0600259 backlight: backlight {
260 compatible = "pwm-backlight";
261 enable-gpios = <&gpio_a 1>;
262 power-supply = <&ldo_1>;
263 pwms = <&pwm 0 1000>;
264 default-brightness-level = <5>;
265 brightness-levels = <0 16 32 64 128 170 202 234 255>;
266 };
267
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200268 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200269 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200270 bind-test-child1 {
271 compatible = "sandbox,phy";
272 #phy-cells = <1>;
273 };
274
275 bind-test-child2 {
276 compatible = "simple-bus";
277 };
278 };
279
Simon Glassb2c1cac2014-02-26 15:59:21 -0700280 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600281 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700282 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600283 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700284 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530285
286 mux-controls = <&muxcontroller0 0>;
287 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700288 };
289
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200290 phy_provider0: gen_phy@0 {
291 compatible = "sandbox,phy";
292 #phy-cells = <1>;
293 };
294
295 phy_provider1: gen_phy@1 {
296 compatible = "sandbox,phy";
297 #phy-cells = <0>;
298 broken;
299 };
300
developer71092972020-05-02 11:35:12 +0200301 phy_provider2: gen_phy@2 {
302 compatible = "sandbox,phy";
303 #phy-cells = <0>;
304 };
305
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200306 gen_phy_user: gen_phy_user {
307 compatible = "simple-bus";
308 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
309 phy-names = "phy1", "phy2", "phy3";
310 };
311
developer71092972020-05-02 11:35:12 +0200312 gen_phy_user1: gen_phy_user1 {
313 compatible = "simple-bus";
314 phys = <&phy_provider0 0>, <&phy_provider2>;
315 phy-names = "phy1", "phy2";
316 };
317
Simon Glassb2c1cac2014-02-26 15:59:21 -0700318 some-bus {
319 #address-cells = <1>;
320 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600321 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600322 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600323 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700324 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600325 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700326 compatible = "denx,u-boot-fdt-test";
327 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600328 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700329 ping-add = <5>;
330 };
Simon Glass40717422014-07-23 06:55:18 -0600331 c-test@0 {
332 compatible = "denx,u-boot-fdt-test";
333 reg = <0>;
334 ping-expect = <6>;
335 ping-add = <6>;
336 };
337 c-test@1 {
338 compatible = "denx,u-boot-fdt-test";
339 reg = <1>;
340 ping-expect = <7>;
341 ping-add = <7>;
342 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700343 };
344
345 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600346 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600347 ping-expect = <6>;
348 ping-add = <6>;
349 compatible = "google,another-fdt-test";
350 };
351
352 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600353 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600354 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700355 ping-add = <6>;
356 compatible = "google,another-fdt-test";
357 };
358
Simon Glass0ccb0972015-01-25 08:27:05 -0700359 f-test {
360 compatible = "denx,u-boot-fdt-test";
361 };
362
363 g-test {
364 compatible = "denx,u-boot-fdt-test";
365 };
366
Bin Mengd9d24782018-10-10 22:07:01 -0700367 h-test {
368 compatible = "denx,u-boot-fdt-test1";
369 };
370
developercf8bc132020-05-02 11:35:10 +0200371 i-test {
372 compatible = "mediatek,u-boot-fdt-test";
373 #address-cells = <1>;
374 #size-cells = <0>;
375
376 subnode@0 {
377 reg = <0>;
378 };
379
380 subnode@1 {
381 reg = <1>;
382 };
383
384 subnode@2 {
385 reg = <2>;
386 };
387 };
388
Simon Glass204675c2019-12-29 21:19:25 -0700389 devres-test {
390 compatible = "denx,u-boot-devres-test";
391 };
392
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530393 another-test {
394 reg = <0 2>;
395 compatible = "denx,u-boot-fdt-test";
396 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
397 test5-gpios = <&gpio_a 19>;
398 };
399
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100400 mmio-bus@0 {
401 #address-cells = <1>;
402 #size-cells = <1>;
403 compatible = "denx,u-boot-test-bus";
404 dma-ranges = <0x10000000 0x00000000 0x00040000>;
405
406 subnode@0 {
407 compatible = "denx,u-boot-fdt-test";
408 };
409 };
410
411 mmio-bus@1 {
412 #address-cells = <1>;
413 #size-cells = <1>;
414 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100415
416 subnode@0 {
417 compatible = "denx,u-boot-fdt-test";
418 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100419 };
420
Simon Glass3c601b12020-07-07 13:12:06 -0600421 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600422 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600423 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600424 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600425 child {
426 compatible = "denx,u-boot-acpi-test";
427 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600428 };
429
Simon Glass3c601b12020-07-07 13:12:06 -0600430 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600431 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600432 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600433 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600434 };
435
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200436 clocks {
437 clk_fixed: clk-fixed {
438 compatible = "fixed-clock";
439 #clock-cells = <0>;
440 clock-frequency = <1234>;
441 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000442
443 clk_fixed_factor: clk-fixed-factor {
444 compatible = "fixed-factor-clock";
445 #clock-cells = <0>;
446 clock-div = <3>;
447 clock-mult = <2>;
448 clocks = <&clk_fixed>;
449 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200450
451 osc {
452 compatible = "fixed-clock";
453 #clock-cells = <0>;
454 clock-frequency = <20000000>;
455 };
Stephen Warrena9622432016-06-17 09:44:00 -0600456 };
457
458 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600459 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600460 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200461 assigned-clocks = <&clk_sandbox 3>;
462 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600463 };
464
465 clk-test {
466 compatible = "sandbox,clk-test";
467 clocks = <&clk_fixed>,
468 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200469 <&clk_sandbox 0>,
470 <&clk_sandbox 3>,
471 <&clk_sandbox 2>;
472 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600473 };
474
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200475 ccf: clk-ccf {
476 compatible = "sandbox,clk-ccf";
477 };
478
Simon Glass5b968632015-05-22 15:42:15 -0600479 eth@10002000 {
480 compatible = "sandbox,eth";
481 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500482 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600483 };
484
485 eth_5: eth@10003000 {
486 compatible = "sandbox,eth";
487 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500488 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600489 };
490
Bin Meng04a11cb2015-08-27 22:25:53 -0700491 eth_3: sbe5 {
492 compatible = "sandbox,eth";
493 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500494 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700495 };
496
Simon Glass5b968632015-05-22 15:42:15 -0600497 eth@10004000 {
498 compatible = "sandbox,eth";
499 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500500 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600501 };
502
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800503 dsa_eth0: dsa-test-eth {
504 compatible = "sandbox,eth";
505 reg = <0x10006000 0x1000>;
506 fake-host-hwaddr = [00 00 66 44 22 66];
507 };
508
509 dsa-test {
510 compatible = "sandbox,dsa";
511
512 ports {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 swp_0: port@0 {
516 reg = <0>;
517 label = "lan0";
518 phy-mode = "rgmii-rxid";
519
520 fixed-link {
521 speed = <100>;
522 full-duplex;
523 };
524 };
525
526 swp_1: port@1 {
527 reg = <1>;
528 label = "lan1";
529 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800530 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800531 };
532
533 port@2 {
534 reg = <2>;
535 ethernet = <&dsa_eth0>;
536
537 fixed-link {
538 speed = <1000>;
539 full-duplex;
540 };
541 };
542 };
543 };
544
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700545 firmware {
546 sandbox_firmware: sandbox-firmware {
547 compatible = "sandbox,firmware";
548 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200549
550 sandbox-scmi-agent@0 {
551 compatible = "sandbox,scmi-agent";
552 #address-cells = <1>;
553 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200554
555 clk_scmi0: protocol@14 {
556 reg = <0x14>;
557 #clock-cells = <1>;
558 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200559
560 reset_scmi0: protocol@16 {
561 reg = <0x16>;
562 #reset-cells = <1>;
563 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100564
565 protocol@17 {
566 reg = <0x17>;
567
568 regulators {
569 #address-cells = <1>;
570 #size-cells = <0>;
571
572 regul0_scmi0: reg@0 {
573 reg = <0>;
574 regulator-name = "sandbox-voltd0";
575 regulator-min-microvolt = <1100000>;
576 regulator-max-microvolt = <3300000>;
577 };
578 regul1_scmi0: reg@1 {
579 reg = <0x1>;
580 regulator-name = "sandbox-voltd1";
581 regulator-min-microvolt = <1800000>;
582 };
583 };
584 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200585 };
586
587 sandbox-scmi-agent@1 {
588 compatible = "sandbox,scmi-agent";
589 #address-cells = <1>;
590 #size-cells = <0>;
591
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200592 clk_scmi1: protocol@14 {
593 reg = <0x14>;
594 #clock-cells = <1>;
595 };
596
Etienne Carriere02fd1262020-09-09 18:44:00 +0200597 protocol@10 {
598 reg = <0x10>;
599 };
600 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700601 };
602
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100603 pinctrl-gpio {
604 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700605
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100606 gpio_a: base-gpios {
607 compatible = "sandbox,gpio";
608 gpio-controller;
609 #gpio-cells = <1>;
610 gpio-bank-name = "a";
611 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200612 hog_input_active_low {
613 gpio-hog;
614 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200615 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200616 };
617 hog_input_active_high {
618 gpio-hog;
619 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200620 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200621 };
622 hog_output_low {
623 gpio-hog;
624 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200625 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200626 };
627 hog_output_high {
628 gpio-hog;
629 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200630 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200631 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100632 };
633
634 gpio_b: extra-gpios {
635 compatible = "sandbox,gpio";
636 gpio-controller;
637 #gpio-cells = <5>;
638 gpio-bank-name = "b";
639 sandbox,gpio-count = <10>;
640 };
Simon Glass25348a42014-10-13 23:42:11 -0600641
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100642 gpio_c: pinmux-gpios {
643 compatible = "sandbox,gpio";
644 gpio-controller;
645 #gpio-cells = <2>;
646 gpio-bank-name = "c";
647 sandbox,gpio-count = <10>;
648 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100649 };
650
Simon Glass7df766e2014-12-10 08:55:55 -0700651 i2c@0 {
652 #address-cells = <1>;
653 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600654 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700655 compatible = "sandbox,i2c";
656 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200657 pinctrl-names = "default";
658 pinctrl-0 = <&pinmux_i2c0_pins>;
659
Simon Glass7df766e2014-12-10 08:55:55 -0700660 eeprom@2c {
661 reg = <0x2c>;
662 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700663 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200664 partitions {
665 compatible = "fixed-partitions";
666 #address-cells = <1>;
667 #size-cells = <1>;
668 bootcount_i2c: bootcount@10 {
669 reg = <10 2>;
670 };
671 };
Simon Glass7df766e2014-12-10 08:55:55 -0700672 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200673
Simon Glass336b2952015-05-22 15:42:17 -0600674 rtc_0: rtc@43 {
675 reg = <0x43>;
676 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700677 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600678 };
679
680 rtc_1: rtc@61 {
681 reg = <0x61>;
682 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700683 sandbox,emul = <&emul1>;
684 };
685
686 i2c_emul: emul {
687 reg = <0xff>;
688 compatible = "sandbox,i2c-emul-parent";
689 emul_eeprom: emul-eeprom {
690 compatible = "sandbox,i2c-eeprom";
691 sandbox,filename = "i2c.bin";
692 sandbox,size = <256>;
693 };
694 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700695 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700696 };
697 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700698 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600699 };
700 };
701
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200702 sandbox_pmic: sandbox_pmic {
703 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700704 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200705 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200706
707 mc34708: pmic@41 {
708 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700709 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200710 };
Simon Glass7df766e2014-12-10 08:55:55 -0700711 };
712
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100713 bootcount@0 {
714 compatible = "u-boot,bootcount-rtc";
715 rtc = <&rtc_1>;
716 offset = <0x13>;
717 };
718
Michal Simek4f18f922020-05-28 11:48:55 +0200719 bootcount {
720 compatible = "u-boot,bootcount-i2c-eeprom";
721 i2c-eeprom = <&bootcount_i2c>;
722 };
723
Marek Szyprowskiad398592021-02-18 11:33:18 +0100724 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100725 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100726 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100727 vdd-supply = <&buck2>;
728 vss-microvolts = <0>;
729 };
730
Simon Glass515dcff2020-02-06 09:55:00 -0700731 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700732 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700733 interrupt-controller;
734 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700735 };
736
Simon Glass90b6fef2016-01-18 19:52:26 -0700737 lcd {
738 u-boot,dm-pre-reloc;
739 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200740 pinctrl-names = "default";
741 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700742 xres = <1366>;
743 yres = <768>;
744 };
745
Simon Glassd783eb32015-07-06 12:54:34 -0600746 leds {
747 compatible = "gpio-leds";
748
749 iracibble {
750 gpios = <&gpio_a 1 0>;
751 label = "sandbox:red";
752 };
753
754 martinet {
755 gpios = <&gpio_a 2 0>;
756 label = "sandbox:green";
757 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200758
759 default_on {
760 gpios = <&gpio_a 5 0>;
761 label = "sandbox:default_on";
762 default-state = "on";
763 };
764
765 default_off {
766 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400767 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200768 default-state = "off";
769 };
Simon Glassd783eb32015-07-06 12:54:34 -0600770 };
771
Stephen Warren62f2c902016-05-16 17:41:37 -0600772 mbox: mbox {
773 compatible = "sandbox,mbox";
774 #mbox-cells = <1>;
775 };
776
777 mbox-test {
778 compatible = "sandbox,mbox-test";
779 mboxes = <&mbox 100>, <&mbox 1>;
780 mbox-names = "other", "test";
781 };
782
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900783 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400784 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900785 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400786 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900787 compatible = "sandbox,cpu_sandbox";
788 u-boot,dm-pre-reloc;
789 };
Mario Sixdea5df72018-08-06 10:23:44 +0200790
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900791 cpu-test2 {
792 compatible = "sandbox,cpu_sandbox";
793 u-boot,dm-pre-reloc;
794 };
Mario Sixdea5df72018-08-06 10:23:44 +0200795
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900796 cpu-test3 {
797 compatible = "sandbox,cpu_sandbox";
798 u-boot,dm-pre-reloc;
799 };
Mario Sixdea5df72018-08-06 10:23:44 +0200800 };
801
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500802 chipid: chipid {
803 compatible = "sandbox,soc";
804 };
805
Simon Glassc953aaf2018-12-10 10:37:34 -0700806 i2s: i2s {
807 compatible = "sandbox,i2s";
808 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700809 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700810 };
811
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200812 nop-test_0 {
813 compatible = "sandbox,nop_sandbox1";
814 nop-test_1 {
815 compatible = "sandbox,nop_sandbox2";
816 bind = "True";
817 };
818 nop-test_2 {
819 compatible = "sandbox,nop_sandbox2";
820 bind = "False";
821 };
822 };
823
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200824 misc-test {
825 compatible = "sandbox,misc_sandbox";
826 };
827
Simon Glasse4fef742017-04-23 20:02:07 -0600828 mmc2 {
829 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600830 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600831 };
832
833 mmc1 {
834 compatible = "sandbox,mmc";
835 };
836
837 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600838 compatible = "sandbox,mmc";
839 };
840
Simon Glass53a68b32019-02-16 20:24:50 -0700841 pch {
842 compatible = "sandbox,pch";
843 };
844
Tom Rini4a3ca482020-02-11 12:41:23 -0500845 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700846 compatible = "sandbox,pci";
847 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500848 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700849 #address-cells = <3>;
850 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600851 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700852 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700853 pci@0,0 {
854 compatible = "pci-generic";
855 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600856 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700857 };
Alex Margineanf1274432019-06-07 11:24:24 +0300858 pci@1,0 {
859 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600860 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
861 reg = <0x02000814 0 0 0 0
862 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600863 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300864 };
Simon Glass937bb472019-12-06 21:41:57 -0700865 p2sb-pci@2,0 {
866 compatible = "sandbox,p2sb";
867 reg = <0x02001010 0 0 0 0>;
868 sandbox,emul = <&p2sb_emul>;
869
870 adder {
871 intel,p2sb-port-id = <3>;
872 compatible = "sandbox,adder";
873 };
874 };
Simon Glass8c501022019-12-06 21:41:54 -0700875 pci@1e,0 {
876 compatible = "sandbox,pmc";
877 reg = <0xf000 0 0 0 0>;
878 sandbox,emul = <&pmc_emul1e>;
879 acpi-base = <0x400>;
880 gpe0-dwx-mask = <0xf>;
881 gpe0-dwx-shift-base = <4>;
882 gpe0-dw = <6 7 9>;
883 gpe0-sts = <0x20>;
884 gpe0-en = <0x30>;
885 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700886 pci@1f,0 {
887 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600888 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
889 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600890 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700891 };
892 };
893
Simon Glassb98ba4c2019-09-25 08:56:10 -0600894 pci-emul0 {
895 compatible = "sandbox,pci-emul-parent";
896 swap_case_emul0_0: emul0@0,0 {
897 compatible = "sandbox,swap-case";
898 };
899 swap_case_emul0_1: emul0@1,0 {
900 compatible = "sandbox,swap-case";
901 use-ea;
902 };
903 swap_case_emul0_1f: emul0@1f,0 {
904 compatible = "sandbox,swap-case";
905 };
Simon Glass937bb472019-12-06 21:41:57 -0700906 p2sb_emul: emul@2,0 {
907 compatible = "sandbox,p2sb-emul";
908 };
Simon Glass8c501022019-12-06 21:41:54 -0700909 pmc_emul1e: emul@1e,0 {
910 compatible = "sandbox,pmc-emul";
911 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600912 };
913
Tom Rini4a3ca482020-02-11 12:41:23 -0500914 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700915 compatible = "sandbox,pci";
916 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500917 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700918 #address-cells = <3>;
919 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700920 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
921 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
922 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700923 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200924 0x0c 0x00 0x1234 0x5678
925 0x10 0x00 0x1234 0x5678>;
926 pci@10,0 {
927 reg = <0x8000 0 0 0 0>;
928 };
Bin Meng408e5902018-08-03 01:14:41 -0700929 };
930
Tom Rini4a3ca482020-02-11 12:41:23 -0500931 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700932 compatible = "sandbox,pci";
933 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500934 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700935 #address-cells = <3>;
936 #size-cells = <2>;
937 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
938 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
939 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
940 pci@1f,0 {
941 compatible = "pci-generic";
942 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600943 sandbox,emul = <&swap_case_emul2_1f>;
944 };
945 };
946
947 pci-emul2 {
948 compatible = "sandbox,pci-emul-parent";
949 swap_case_emul2_1f: emul2@1f,0 {
950 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700951 };
952 };
953
Ramon Friedc64f19b2019-04-27 11:15:23 +0300954 pci_ep: pci_ep {
955 compatible = "sandbox,pci_ep";
956 };
957
Simon Glass9c433fe2017-04-23 20:10:44 -0600958 probing {
959 compatible = "simple-bus";
960 test1 {
961 compatible = "denx,u-boot-probe-test";
962 };
963
964 test2 {
965 compatible = "denx,u-boot-probe-test";
966 };
967
968 test3 {
969 compatible = "denx,u-boot-probe-test";
970 };
971
972 test4 {
973 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100974 first-syscon = <&syscon0>;
975 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100976 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600977 };
978 };
979
Stephen Warren92c67fa2016-07-13 13:45:31 -0600980 pwrdom: power-domain {
981 compatible = "sandbox,power-domain";
982 #power-domain-cells = <1>;
983 };
984
985 power-domain-test {
986 compatible = "sandbox,power-domain-test";
987 power-domains = <&pwrdom 2>;
988 };
989
Simon Glass5620cf82018-10-01 12:22:40 -0600990 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600991 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600992 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200993 pinctrl-names = "default";
994 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600995 };
996
997 pwm2 {
998 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600999 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001000 };
1001
Simon Glass3d355e62015-07-06 12:54:31 -06001002 ram {
1003 compatible = "sandbox,ram";
1004 };
1005
Simon Glassd860f222015-07-06 12:54:29 -06001006 reset@0 {
1007 compatible = "sandbox,warm-reset";
1008 };
1009
1010 reset@1 {
1011 compatible = "sandbox,reset";
1012 };
1013
Stephen Warren6488e642016-06-17 09:43:59 -06001014 resetc: reset-ctl {
1015 compatible = "sandbox,reset-ctl";
1016 #reset-cells = <1>;
1017 };
1018
1019 reset-ctl-test {
1020 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001021 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1022 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001023 };
1024
Sughosh Ganu23e37512019-12-28 23:58:31 +05301025 rng {
1026 compatible = "sandbox,sandbox-rng";
1027 };
1028
Nishanth Menonedf85812015-09-17 15:42:41 -05001029 rproc_1: rproc@1 {
1030 compatible = "sandbox,test-processor";
1031 remoteproc-name = "remoteproc-test-dev1";
1032 };
1033
1034 rproc_2: rproc@2 {
1035 compatible = "sandbox,test-processor";
1036 internal-memory-mapped;
1037 remoteproc-name = "remoteproc-test-dev2";
1038 };
1039
Simon Glass5620cf82018-10-01 12:22:40 -06001040 panel {
1041 compatible = "simple-panel";
1042 backlight = <&backlight 0 100>;
1043 };
1044
Ramon Fried26ed32e2018-07-02 02:57:59 +03001045 smem@0 {
1046 compatible = "sandbox,smem";
1047 };
1048
Simon Glass76072ac2018-12-10 10:37:36 -07001049 sound {
1050 compatible = "sandbox,sound";
1051 cpu {
1052 sound-dai = <&i2s 0>;
1053 };
1054
1055 codec {
1056 sound-dai = <&audio 0>;
1057 };
1058 };
1059
Simon Glass25348a42014-10-13 23:42:11 -06001060 spi@0 {
1061 #address-cells = <1>;
1062 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001063 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001064 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001065 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001066 pinctrl-names = "default";
1067 pinctrl-0 = <&pinmux_spi0_pins>;
1068
Simon Glass25348a42014-10-13 23:42:11 -06001069 spi.bin@0 {
1070 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001071 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001072 spi-max-frequency = <40000000>;
1073 sandbox,filename = "spi.bin";
1074 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001075 spi.bin@1 {
1076 reg = <1>;
1077 compatible = "spansion,m25p16", "jedec,spi-nor";
1078 spi-max-frequency = <50000000>;
1079 sandbox,filename = "spi.bin";
1080 spi-cpol;
1081 spi-cpha;
1082 };
Simon Glass25348a42014-10-13 23:42:11 -06001083 };
1084
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001085 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001086 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001087 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001088 };
1089
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001090 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001091 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001092 reg = <0x20 5
1093 0x28 6
1094 0x30 7
1095 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001096 };
1097
Patrick Delaunayee010432019-03-07 09:57:13 +01001098 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001099 compatible = "simple-mfd", "syscon";
1100 reg = <0x40 5
1101 0x48 6
1102 0x50 7
1103 0x58 8>;
1104 };
1105
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301106 syscon3: syscon@3 {
1107 compatible = "simple-mfd", "syscon";
1108 reg = <0x000100 0x10>;
1109
1110 muxcontroller0: a-mux-controller {
1111 compatible = "mmio-mux";
1112 #mux-control-cells = <1>;
1113
1114 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1115 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1116 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1117 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1118 u-boot,mux-autoprobe;
1119 };
1120 };
1121
1122 muxcontroller1: emul-mux-controller {
1123 compatible = "mux-emul";
1124 #mux-control-cells = <0>;
1125 u-boot,mux-autoprobe;
1126 idle-state = <0xabcd>;
1127 };
1128
Simon Glass791a17f2020-12-16 21:20:27 -07001129 testfdtm0 {
1130 compatible = "denx,u-boot-fdtm-test";
1131 };
1132
1133 testfdtm1: testfdtm1 {
1134 compatible = "denx,u-boot-fdtm-test";
1135 };
1136
1137 testfdtm2 {
1138 compatible = "denx,u-boot-fdtm-test";
1139 };
1140
Sean Anderson79d3bba2020-09-28 10:52:23 -04001141 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001142 compatible = "sandbox,timer";
1143 clock-frequency = <1000000>;
1144 };
1145
Sean Anderson79d3bba2020-09-28 10:52:23 -04001146 timer@1 {
1147 compatible = "sandbox,timer";
1148 sandbox,timebase-frequency-fallback;
1149 };
1150
Miquel Raynal80938c12018-05-15 11:57:27 +02001151 tpm2 {
1152 compatible = "sandbox,tpm2";
1153 };
1154
Simon Glass5b968632015-05-22 15:42:15 -06001155 uart0: serial {
1156 compatible = "sandbox,serial";
1157 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001158 pinctrl-names = "default";
1159 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001160 };
1161
Simon Glass31680482015-03-25 12:23:05 -06001162 usb_0: usb@0 {
1163 compatible = "sandbox,usb";
1164 status = "disabled";
1165 hub {
1166 compatible = "sandbox,usb-hub";
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1169 flash-stick {
1170 reg = <0>;
1171 compatible = "sandbox,usb-flash";
1172 };
1173 };
1174 };
1175
1176 usb_1: usb@1 {
1177 compatible = "sandbox,usb";
1178 hub {
1179 compatible = "usb-hub";
1180 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001181 #address-cells = <1>;
1182 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001183 hub-emul {
1184 compatible = "sandbox,usb-hub";
1185 #address-cells = <1>;
1186 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001187 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001188 reg = <0>;
1189 compatible = "sandbox,usb-flash";
1190 sandbox,filepath = "testflash.bin";
1191 };
1192
Simon Glass4700fe52015-11-08 23:48:01 -07001193 flash-stick@1 {
1194 reg = <1>;
1195 compatible = "sandbox,usb-flash";
1196 sandbox,filepath = "testflash1.bin";
1197 };
1198
1199 flash-stick@2 {
1200 reg = <2>;
1201 compatible = "sandbox,usb-flash";
1202 sandbox,filepath = "testflash2.bin";
1203 };
1204
Simon Glassc0ccc722015-11-08 23:48:08 -07001205 keyb@3 {
1206 reg = <3>;
1207 compatible = "sandbox,usb-keyb";
1208 };
1209
Simon Glass31680482015-03-25 12:23:05 -06001210 };
Michael Walle7c961322020-06-02 01:47:07 +02001211
1212 usbstor@1 {
1213 reg = <1>;
1214 };
1215 usbstor@3 {
1216 reg = <3>;
1217 };
Simon Glass31680482015-03-25 12:23:05 -06001218 };
1219 };
1220
1221 usb_2: usb@2 {
1222 compatible = "sandbox,usb";
1223 status = "disabled";
1224 };
1225
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001226 spmi: spmi@0 {
1227 compatible = "sandbox,spmi";
1228 #address-cells = <0x1>;
1229 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001230 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001231 pm8916@0 {
1232 compatible = "qcom,spmi-pmic";
1233 reg = <0x0 0x1>;
1234 #address-cells = <0x1>;
1235 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001236 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001237
1238 spmi_gpios: gpios@c000 {
1239 compatible = "qcom,pm8916-gpio";
1240 reg = <0xc000 0x400>;
1241 gpio-controller;
1242 gpio-count = <4>;
1243 #gpio-cells = <2>;
1244 gpio-bank-name="spmi";
1245 };
1246 };
1247 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001248
1249 wdt0: wdt@0 {
1250 compatible = "sandbox,wdt";
1251 };
Rob Clarka471b672018-01-10 11:33:30 +01001252
Mario Six95922152018-08-09 14:51:19 +02001253 axi: axi@0 {
1254 compatible = "sandbox,axi";
1255 #address-cells = <0x1>;
1256 #size-cells = <0x1>;
1257 store@0 {
1258 compatible = "sandbox,sandbox_store";
1259 reg = <0x0 0x400>;
1260 };
1261 };
1262
Rob Clarka471b672018-01-10 11:33:30 +01001263 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001264 #address-cells = <1>;
1265 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001266 setting = "sunrise ohoka";
1267 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001268 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001269 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001270 chosen-test {
1271 compatible = "denx,u-boot-fdt-test";
1272 reg = <9 1>;
1273 };
1274 };
Mario Six35616ef2018-03-12 14:53:33 +01001275
1276 translation-test@8000 {
1277 compatible = "simple-bus";
1278 reg = <0x8000 0x4000>;
1279
1280 #address-cells = <0x2>;
1281 #size-cells = <0x1>;
1282
1283 ranges = <0 0x0 0x8000 0x1000
1284 1 0x100 0x9000 0x1000
1285 2 0x200 0xA000 0x1000
1286 3 0x300 0xB000 0x1000
1287 >;
1288
Fabien Dessenne22236e02019-05-31 15:11:30 +02001289 dma-ranges = <0 0x000 0x10000000 0x1000
1290 1 0x100 0x20000000 0x1000
1291 >;
1292
Mario Six35616ef2018-03-12 14:53:33 +01001293 dev@0,0 {
1294 compatible = "denx,u-boot-fdt-dummy";
1295 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001296 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001297 };
1298
1299 dev@1,100 {
1300 compatible = "denx,u-boot-fdt-dummy";
1301 reg = <1 0x100 0x1000>;
1302
1303 };
1304
1305 dev@2,200 {
1306 compatible = "denx,u-boot-fdt-dummy";
1307 reg = <2 0x200 0x1000>;
1308 };
1309
1310
1311 noxlatebus@3,300 {
1312 compatible = "simple-bus";
1313 reg = <3 0x300 0x1000>;
1314
1315 #address-cells = <0x1>;
1316 #size-cells = <0x0>;
1317
1318 dev@42 {
1319 compatible = "denx,u-boot-fdt-dummy";
1320 reg = <0x42>;
1321 };
1322 };
1323 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001324
1325 osd {
1326 compatible = "sandbox,sandbox_osd";
1327 };
Tom Rinib93eea72018-09-30 18:16:51 -04001328
Jens Wiklander86afaa62018-09-25 16:40:16 +02001329 sandbox_tee {
1330 compatible = "sandbox,tee";
1331 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001332
1333 sandbox_virtio1 {
1334 compatible = "sandbox,virtio1";
1335 };
1336
1337 sandbox_virtio2 {
1338 compatible = "sandbox,virtio2";
1339 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001340
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001341 sandbox_scmi {
1342 compatible = "sandbox,scmi-devices";
1343 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001344 resets = <&reset_scmi0 3>;
Etienne Carriereb8f15cd2021-03-08 22:38:07 +01001345 regul0-supply = <&regul0_scmi0>;
1346 regul1-supply = <&regul1_scmi0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001347 };
1348
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001349 pinctrl {
1350 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001351
Sean Anderson3438e3b2020-09-14 11:01:57 -04001352 pinctrl-names = "default", "alternate";
1353 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1354 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001355
Sean Anderson3438e3b2020-09-14 11:01:57 -04001356 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001357 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001358 pins = "P5";
1359 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001360 bias-pull-up;
1361 input-disable;
1362 };
1363 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001364 pins = "P6";
1365 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001366 output-high;
1367 drive-open-drain;
1368 };
1369 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001370 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001371 bias-pull-down;
1372 input-enable;
1373 };
1374 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001375 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001376 bias-disable;
1377 };
1378 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001379
1380 pinctrl_i2c: i2c {
1381 groups {
1382 groups = "I2C_UART";
1383 function = "I2C";
1384 };
1385
1386 pins {
1387 pins = "P0", "P1";
1388 drive-open-drain;
1389 };
1390 };
1391
1392 pinctrl_i2s: i2s {
1393 groups = "SPI_I2S";
1394 function = "I2S";
1395 };
1396
1397 pinctrl_spi: spi {
1398 groups = "SPI_I2S";
1399 function = "SPI";
1400
1401 cs {
1402 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1403 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1404 };
1405 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001406 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001407
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001408 pinctrl-single-no-width {
1409 compatible = "pinctrl-single";
1410 reg = <0x0000 0x238>;
1411 #pinctrl-cells = <1>;
1412 pinctrl-single,function-mask = <0x7f>;
1413 };
1414
1415 pinctrl-single-pins {
1416 compatible = "pinctrl-single";
1417 reg = <0x0000 0x238>;
1418 #pinctrl-cells = <1>;
1419 pinctrl-single,register-width = <32>;
1420 pinctrl-single,function-mask = <0x7f>;
1421
1422 pinmux_pwm_pins: pinmux_pwm_pins {
1423 pinctrl-single,pins = < 0x48 0x06 >;
1424 };
1425
1426 pinmux_spi0_pins: pinmux_spi0_pins {
1427 pinctrl-single,pins = <
1428 0x190 0x0c
1429 0x194 0x0c
1430 0x198 0x23
1431 0x19c 0x0c
1432 >;
1433 };
1434
1435 pinmux_uart0_pins: pinmux_uart0_pins {
1436 pinctrl-single,pins = <
1437 0x70 0x30
1438 0x74 0x00
1439 >;
1440 };
1441 };
1442
1443 pinctrl-single-bits {
1444 compatible = "pinctrl-single";
1445 reg = <0x0000 0x50>;
1446 #pinctrl-cells = <2>;
1447 pinctrl-single,bit-per-mux;
1448 pinctrl-single,register-width = <32>;
1449 pinctrl-single,function-mask = <0xf>;
1450
1451 pinmux_i2c0_pins: pinmux_i2c0_pins {
1452 pinctrl-single,bits = <
1453 0x10 0x00002200 0x0000ff00
1454 >;
1455 };
1456
1457 pinmux_lcd_pins: pinmux_lcd_pins {
1458 pinctrl-single,bits = <
1459 0x40 0x22222200 0xffffff00
1460 0x44 0x22222222 0xffffffff
1461 0x48 0x00000022 0x000000ff
1462 0x48 0x02000000 0x0f000000
1463 0x4c 0x02000022 0x0f0000ff
1464 >;
1465 };
1466 };
1467
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001468 hwspinlock@0 {
1469 compatible = "sandbox,hwspinlock";
1470 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001471
1472 dma: dma {
1473 compatible = "sandbox,dma";
1474 #dma-cells = <1>;
1475
1476 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1477 dma-names = "m2m", "tx0", "rx0";
1478 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001479
Alex Marginean0649be52019-07-12 10:13:53 +03001480 /*
1481 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1482 * end of the test. If parent mdio is removed first, clean-up of the
1483 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1484 * active at the end of the test. That it turn doesn't allow the mdio
1485 * class to be destroyed, triggering an error.
1486 */
1487 mdio-mux-test {
1488 compatible = "sandbox,mdio-mux";
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1491 mdio-parent-bus = <&mdio>;
1492
1493 mdio-ch-test@0 {
1494 reg = <0>;
1495 };
1496 mdio-ch-test@1 {
1497 reg = <1>;
1498 };
1499 };
1500
1501 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001502 compatible = "sandbox,mdio";
1503 };
Sean Andersonb7860542020-06-24 06:41:12 -04001504
1505 pm-bus-test {
1506 compatible = "simple-pm-bus";
1507 clocks = <&clk_sandbox 4>;
1508 power-domains = <&pwrdom 1>;
1509 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001510
1511 resetc2: syscon-reset {
1512 compatible = "syscon-reset";
1513 #reset-cells = <1>;
1514 regmap = <&syscon0>;
1515 offset = <1>;
1516 mask = <0x27FFFFFF>;
1517 assert-high = <0>;
1518 };
1519
1520 syscon-reset-test {
1521 compatible = "sandbox,misc_sandbox";
1522 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1523 reset-names = "valid", "no_mask", "out_of_range";
1524 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301525
Simon Glass458b66a2020-11-05 06:32:05 -07001526 sysinfo {
1527 compatible = "sandbox,sysinfo-sandbox";
1528 };
1529
Sean Anderson1c830672021-04-20 10:50:58 -04001530 sysinfo-gpio {
1531 compatible = "gpio-sysinfo";
1532 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1533 revisions = <19>, <5>;
1534 names = "rev_a", "foo";
1535 };
1536
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301537 some_regmapped-bus {
1538 #address-cells = <0x1>;
1539 #size-cells = <0x1>;
1540
1541 ranges = <0x0 0x0 0x10>;
1542 compatible = "simple-bus";
1543
1544 regmap-test_0 {
1545 reg = <0 0x10>;
1546 compatible = "sandbox,regmap_test";
1547 };
1548 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001549};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001550
1551#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001552#include "cros-ec-keyboard.dtsi"