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Jagan Teki0c160292018-08-02 19:54:26 +05301// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -050011#include <clk/sunxi.h>
Jagan Teki0c160292018-08-02 19:54:26 +053012#include <dt-bindings/clock/sun5i-ccu.h>
13#include <dt-bindings/reset/sun5i-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Jagan Teki0c160292018-08-02 19:54:26 +053015
16static struct ccu_clk_gate a10s_gates[] = {
17 [CLK_AHB_OTG] = GATE(0x060, BIT(0)),
18 [CLK_AHB_EHCI] = GATE(0x060, BIT(1)),
19 [CLK_AHB_OHCI] = GATE(0x060, BIT(2)),
Andre Przywaraddf33c12019-01-29 15:54:09 +000020 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
21 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
22 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
Jagan Tekif4b29f42019-02-28 00:26:49 +053023 [CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +053024 [CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
25 [CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
26 [CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
Jagan Teki0c160292018-08-02 19:54:26 +053027
Andre Przywara3e9aa0b2022-05-04 22:10:28 +010028 [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
29
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050030 [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
31 [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
32 [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +053033 [CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
34 [CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
35 [CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
36 [CLK_APB1_UART3] = GATE(0x06c, BIT(19)),
37
Jagan Tekibc123132019-02-27 20:02:06 +053038 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
39 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
40 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
41
Jagan Teki0c160292018-08-02 19:54:26 +053042 [CLK_USB_OHCI] = GATE(0x0cc, BIT(6)),
43 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
44 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
45};
46
47static struct ccu_reset a10s_resets[] = {
48 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
49 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
50};
51
52static const struct ccu_desc a10s_ccu_desc = {
53 .gates = a10s_gates,
54 .resets = a10s_resets,
55};
56
57static int a10s_clk_bind(struct udevice *dev)
58{
59 return sunxi_reset_bind(dev, ARRAY_SIZE(a10s_resets));
60}
61
62static const struct udevice_id a10s_ccu_ids[] = {
63 { .compatible = "allwinner,sun5i-a10s-ccu",
64 .data = (ulong)&a10s_ccu_desc },
65 { .compatible = "allwinner,sun5i-a13-ccu",
66 .data = (ulong)&a10s_ccu_desc },
67 { }
68};
69
70U_BOOT_DRIVER(clk_sun5i_a10s) = {
71 .name = "sun5i_a10s_ccu",
72 .id = UCLASS_CLK,
73 .of_match = a10s_ccu_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -070074 .priv_auto = sizeof(struct ccu_priv),
Jagan Teki0c160292018-08-02 19:54:26 +053075 .ops = &sunxi_clk_ops,
76 .probe = sunxi_clk_probe,
77 .bind = a10s_clk_bind,
78};