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Jagan Teki0c160292018-08-02 19:54:26 +05301// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun5i-ccu.h>
13#include <dt-bindings/reset/sun5i-ccu.h>
14
15static struct ccu_clk_gate a10s_gates[] = {
16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)),
17 [CLK_AHB_EHCI] = GATE(0x060, BIT(1)),
18 [CLK_AHB_OHCI] = GATE(0x060, BIT(2)),
Andre Przywaraddf33c12019-01-29 15:54:09 +000019 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
20 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
21 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki0c160292018-08-02 19:54:26 +053022
Jagan Teki8cf08ea2018-12-30 21:29:24 +053023 [CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
24 [CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
25 [CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
26 [CLK_APB1_UART3] = GATE(0x06c, BIT(19)),
27
Jagan Teki0c160292018-08-02 19:54:26 +053028 [CLK_USB_OHCI] = GATE(0x0cc, BIT(6)),
29 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
30 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
31};
32
33static struct ccu_reset a10s_resets[] = {
34 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
35 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
36};
37
38static const struct ccu_desc a10s_ccu_desc = {
39 .gates = a10s_gates,
40 .resets = a10s_resets,
41};
42
43static int a10s_clk_bind(struct udevice *dev)
44{
45 return sunxi_reset_bind(dev, ARRAY_SIZE(a10s_resets));
46}
47
48static const struct udevice_id a10s_ccu_ids[] = {
49 { .compatible = "allwinner,sun5i-a10s-ccu",
50 .data = (ulong)&a10s_ccu_desc },
51 { .compatible = "allwinner,sun5i-a13-ccu",
52 .data = (ulong)&a10s_ccu_desc },
53 { }
54};
55
56U_BOOT_DRIVER(clk_sun5i_a10s) = {
57 .name = "sun5i_a10s_ccu",
58 .id = UCLASS_CLK,
59 .of_match = a10s_ccu_ids,
60 .priv_auto_alloc_size = sizeof(struct ccu_priv),
61 .ops = &sunxi_clk_ops,
62 .probe = sunxi_clk_probe,
63 .bind = a10s_clk_bind,
64};