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wdenk69141282003-07-07 20:07:54 +00001/*
Wolfgang Denk3edb6202014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenk69141282003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk69141282003-07-07 20:07:54 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
21#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
22
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0x40000000
24
wdenk69141282003-07-07 20:07:54 +000025#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denkf0d526a2009-07-28 22:13:52 +020026#define CONFIG_SYS_SMC_RXBUFLEN 128
27#define CONFIG_SYS_MAXIDLE 10
wdenk69141282003-07-07 20:07:54 +000028#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
29
wdenkfb229ae2003-08-07 22:18:11 +000030#define CONFIG_BOOTCOUNT_LIMIT
wdenk69141282003-07-07 20:07:54 +000031
wdenk69141282003-07-07 20:07:54 +000032
33#define CONFIG_BOARD_TYPES 1 /* support board types */
34
35#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +010036 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk69141282003-07-07 20:07:54 +000037 "echo"
38
39#undef CONFIG_BOOTARGS
40
41#define CONFIG_EXTRA_ENV_SETTINGS \
42 "netdev=eth0\0" \
43 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010044 "nfsroot=${serverip}:${rootpath}\0" \
wdenk69141282003-07-07 20:07:54 +000045 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010046 "addip=setenv bootargs ${bootargs} " \
47 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
48 ":${hostname}:${netdev}:off panic=1\0" \
wdenk69141282003-07-07 20:07:54 +000049 "flash_nfs=run nfsargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010050 "bootm ${kernel_addr}\0" \
wdenk69141282003-07-07 20:07:54 +000051 "flash_self=run ramargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010052 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
53 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk69141282003-07-07 20:07:54 +000054 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +020055 "hostname=TQM855M\0" \
56 "bootfile=TQM855M/uImage\0" \
Wolfgang Denk64ab5182007-09-16 02:39:35 +020057 "fdt_addr=40080000\0" \
58 "kernel_addr=400A0000\0" \
59 "ramdisk_addr=40280000\0" \
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +020060 "u-boot=TQM855M/u-image.bin\0" \
61 "load=tftp 200000 ${u-boot}\0" \
62 "update=prot off 40000000 +${filesize};" \
63 "era 40000000 +${filesize};" \
64 "cp.b 200000 40000000 ${filesize};" \
65 "sete filesize;save\0" \
wdenk69141282003-07-07 20:07:54 +000066 ""
67#define CONFIG_BOOTCOMMAND "run flash_self"
68
69#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk69141282003-07-07 20:07:54 +000071
72#undef CONFIG_WATCHDOG /* watchdog disabled */
73
wdenk69141282003-07-07 20:07:54 +000074#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
75
wdenk1ebf41e2004-01-02 14:00:00 +000076/* enable I2C and select the hardware/software driver */
Heiko Schocher479a4cf2013-01-29 08:53:15 +010077#define CONFIG_SYS_I2C
78#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
79#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
80#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenk1ebf41e2004-01-02 14:00:00 +000081/*
82 * Software (bit-bang) I2C driver configuration
83 */
84#define PB_SCL 0x00000020 /* PB 26 */
85#define PB_SDA 0x00000010 /* PB 27 */
86
87#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
88#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
89#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
90#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
91#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
92 else immr->im_cpm.cp_pbdat &= ~PB_SDA
93#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
94 else immr->im_cpm.cp_pbdat &= ~PB_SCL
95#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
wdenk1ebf41e2004-01-02 14:00:00 +000096
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
98#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
wdenk1ebf41e2004-01-02 14:00:00 +000099#if 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
101#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
102#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
wdenk1ebf41e2004-01-02 14:00:00 +0000103#endif
104
Jon Loeliger530ca672007-07-09 21:38:02 -0500105/*
106 * BOOTP options
107 */
108#define CONFIG_BOOTP_SUBNETMASK
109#define CONFIG_BOOTP_GATEWAY
110#define CONFIG_BOOTP_HOSTNAME
111#define CONFIG_BOOTP_BOOTPATH
112#define CONFIG_BOOTP_BOOTFILESIZE
113
wdenk69141282003-07-07 20:07:54 +0000114#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
115
Jon Loeligeredccb462007-07-04 22:30:50 -0500116/*
117 * Command line configuration.
118 */
Jon Loeligeredccb462007-07-04 22:30:50 -0500119#define CONFIG_CMD_DATE
Jon Loeligeredccb462007-07-04 22:30:50 -0500120#define CONFIG_CMD_EEPROM
121#define CONFIG_CMD_IDE
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200122#define CONFIG_CMD_JFFS2
wdenk69141282003-07-07 20:07:54 +0000123
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200124#define CONFIG_NETCONSOLE
125
wdenk69141282003-07-07 20:07:54 +0000126/*
127 * Miscellaneous configurable options
128 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk69141282003-07-07 20:07:54 +0000130
Wolfgang Denk274bac52006-10-28 02:29:14 +0200131#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
wdenk69141282003-07-07 20:07:54 +0000132
Jon Loeligeredccb462007-07-04 22:30:50 -0500133#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk69141282003-07-07 20:07:54 +0000135#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk69141282003-07-07 20:07:54 +0000137#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
139#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
140#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk69141282003-07-07 20:07:54 +0000141
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
143#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk69141282003-07-07 20:07:54 +0000144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk69141282003-07-07 20:07:54 +0000146
wdenk69141282003-07-07 20:07:54 +0000147/*
148 * Low Level Configuration Settings
149 * (address mappings, register initial values, etc.)
150 * You should know what you are doing if you make changes here.
151 */
152/*-----------------------------------------------------------------------
153 * Internal Memory Mapped Register
154 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_IMMR 0xFFF00000
wdenk69141282003-07-07 20:07:54 +0000156
157/*-----------------------------------------------------------------------
158 * Definitions for initial stack pointer and data area (in DPRAM)
159 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200161#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200162#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk69141282003-07-07 20:07:54 +0000164
165/*-----------------------------------------------------------------------
166 * Start addresses for the final memory configuration
167 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk69141282003-07-07 20:07:54 +0000169 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_SDRAM_BASE 0x00000000
171#define CONFIG_SYS_FLASH_BASE 0x40000000
172#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
173#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
174#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk69141282003-07-07 20:07:54 +0000175
176/*
177 * For booting Linux, the board info and command line data
178 * have to be in the first 8 MB of memory, since this is
179 * the maximum mapped by the Linux kernel during initialization.
180 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk69141282003-07-07 20:07:54 +0000182
183/*-----------------------------------------------------------------------
184 * FLASH organization
185 */
wdenk69141282003-07-07 20:07:54 +0000186
Martin Krausec098b0e2007-09-27 11:10:08 +0200187/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200189#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
191#define CONFIG_SYS_FLASH_EMPTY_INFO
192#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
193#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
194#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk69141282003-07-07 20:07:54 +0000195
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200196#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200197#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
198#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
199#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenk69141282003-07-07 20:07:54 +0000200
201/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200202#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
203#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk69141282003-07-07 20:07:54 +0000204
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk4ed40bb2007-09-16 17:10:04 +0200206
Wolfgang Denk8d82cc02008-09-16 18:02:19 +0200207#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
208
wdenk69141282003-07-07 20:07:54 +0000209/*-----------------------------------------------------------------------
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200210 * Dynamic MTD partition support
211 */
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100212#define CONFIG_CMD_MTDPARTS
Stefan Roese5dc958f2009-05-12 14:32:58 +0200213#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
214#define CONFIG_FLASH_CFI_MTD
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200215#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
216
217#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
218 "128k(dtb)," \
219 "1920k(kernel)," \
220 "5632(rootfs)," \
Wolfgang Denk1ec16772008-08-12 16:08:38 +0200221 "4m(data)"
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200222
223/*-----------------------------------------------------------------------
wdenk69141282003-07-07 20:07:54 +0000224 * Hardware Information Block
225 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
227#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
228#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenk69141282003-07-07 20:07:54 +0000229
230/*-----------------------------------------------------------------------
231 * Cache Configuration
232 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligeredccb462007-07-04 22:30:50 -0500234#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk69141282003-07-07 20:07:54 +0000236#endif
237
238/*-----------------------------------------------------------------------
239 * SYPCR - System Protection Control 11-9
240 * SYPCR can only be written once after reset!
241 *-----------------------------------------------------------------------
242 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
243 */
244#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk69141282003-07-07 20:07:54 +0000246 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
247#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk69141282003-07-07 20:07:54 +0000249#endif
250
251/*-----------------------------------------------------------------------
252 * SIUMCR - SIU Module Configuration 11-6
253 *-----------------------------------------------------------------------
254 * PCMCIA config., multi-function pin tri-state
255 */
256#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200257#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk69141282003-07-07 20:07:54 +0000258#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk69141282003-07-07 20:07:54 +0000260#endif /* CONFIG_CAN_DRIVER */
261
262/*-----------------------------------------------------------------------
263 * TBSCR - Time Base Status and Control 11-26
264 *-----------------------------------------------------------------------
265 * Clear Reference Interrupt Status, Timebase freezing enabled
266 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk69141282003-07-07 20:07:54 +0000268
269/*-----------------------------------------------------------------------
270 * RTCSC - Real-Time Clock Status and Control Register 11-27
271 *-----------------------------------------------------------------------
272 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200273#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk69141282003-07-07 20:07:54 +0000274
275/*-----------------------------------------------------------------------
276 * PISCR - Periodic Interrupt Status and Control 11-31
277 *-----------------------------------------------------------------------
278 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
279 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200280#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk69141282003-07-07 20:07:54 +0000281
282/*-----------------------------------------------------------------------
283 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
284 *-----------------------------------------------------------------------
285 * Reset PLL lock status sticky bit, timer expired status bit and timer
286 * interrupt status bit
wdenk69141282003-07-07 20:07:54 +0000287 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200288#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenk69141282003-07-07 20:07:54 +0000289
290/*-----------------------------------------------------------------------
291 * SCCR - System Clock and reset Control Register 15-27
292 *-----------------------------------------------------------------------
293 * Set clock output, timebase and RTC source and divider,
294 * power management and some other internal clocks
295 */
296#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200297#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenk69141282003-07-07 20:07:54 +0000298 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
299 SCCR_DFALCD00)
wdenk69141282003-07-07 20:07:54 +0000300
301/*-----------------------------------------------------------------------
302 * PCMCIA stuff
303 *-----------------------------------------------------------------------
304 *
305 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200306#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
307#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
308#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
309#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
310#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
311#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
312#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
313#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk69141282003-07-07 20:07:54 +0000314
315/*-----------------------------------------------------------------------
316 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
317 *-----------------------------------------------------------------------
318 */
319
Pavel Herrmann2c13c4a2012-10-09 07:01:56 +0000320#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenk69141282003-07-07 20:07:54 +0000321#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
322
323#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
324#undef CONFIG_IDE_LED /* LED for ide not supported */
325#undef CONFIG_IDE_RESET /* reset for ide not supported */
326
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200327#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
328#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk69141282003-07-07 20:07:54 +0000329
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200330#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk69141282003-07-07 20:07:54 +0000331
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200332#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk69141282003-07-07 20:07:54 +0000333
334/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200335#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk69141282003-07-07 20:07:54 +0000336
337/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200338#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk69141282003-07-07 20:07:54 +0000339
340/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200341#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk69141282003-07-07 20:07:54 +0000342
343/*-----------------------------------------------------------------------
344 *
345 *-----------------------------------------------------------------------
346 *
347 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200348#define CONFIG_SYS_DER 0
wdenk69141282003-07-07 20:07:54 +0000349
350/*
351 * Init Memory Controller:
352 *
353 * BR0/1 and OR0/1 (FLASH)
354 */
355
356#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
357#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
358
359/* used to re-map FLASH both when starting from SRAM or FLASH:
360 * restrict access enough to keep SRAM working (if any)
361 * but not too much to meddle with FLASH accesses
362 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200363#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
364#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk69141282003-07-07 20:07:54 +0000365
366/*
367 * FLASH timing:
368 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200369#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenk69141282003-07-07 20:07:54 +0000370 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenk69141282003-07-07 20:07:54 +0000371
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200372#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
373#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
374#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk69141282003-07-07 20:07:54 +0000375
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200376#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
377#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
378#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenk69141282003-07-07 20:07:54 +0000379
380/*
381 * BR2/3 and OR2/3 (SDRAM)
382 *
383 */
384#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
385#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
386#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
387
388/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200389#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk69141282003-07-07 20:07:54 +0000390
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200391#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
392#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk69141282003-07-07 20:07:54 +0000393
394#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200395#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
396#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk69141282003-07-07 20:07:54 +0000397#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200398#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
399#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
400#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
401#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenk69141282003-07-07 20:07:54 +0000402 BR_PS_8 | BR_MS_UPMB | BR_V )
403#endif /* CONFIG_CAN_DRIVER */
404
405/*
406 * Memory Periodic Timer Prescaler
407 *
408 * The Divider for PTA (refresh timer) configuration is based on an
409 * example SDRAM configuration (64 MBit, one bank). The adjustment to
410 * the number of chip selects (NCS) and the actually needed refresh
411 * rate is done by setting MPTPR.
412 *
413 * PTA is calculated from
414 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
415 *
416 * gclk CPU clock (not bus clock!)
417 * Trefresh Refresh cycle * 4 (four word bursts used)
418 *
419 * 4096 Rows from SDRAM example configuration
420 * 1000 factor s -> ms
421 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
422 * 4 Number of refresh cycles per period
423 * 64 Refresh cycle in ms per number of rows
424 * --------------------------------------------
425 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
426 *
427 * 50 MHz => 50.000.000 / Divider = 98
428 * 66 Mhz => 66.000.000 / Divider = 129
429 * 80 Mhz => 80.000.000 / Divider = 156
430 */
wdenkc78bf132004-04-24 23:23:30 +0000431
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200432#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
433#define CONFIG_SYS_MAMR_PTA 98
wdenk69141282003-07-07 20:07:54 +0000434
435/*
436 * For 16 MBit, refresh rates could be 31.3 us
437 * (= 64 ms / 2K = 125 / quad bursts).
438 * For a simpler initialization, 15.6 us is used instead.
439 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200440 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
441 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenk69141282003-07-07 20:07:54 +0000442 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200443#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
444#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk69141282003-07-07 20:07:54 +0000445
446/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200447#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
448#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk69141282003-07-07 20:07:54 +0000449
450/*
451 * MAMR settings for SDRAM
452 */
453
454/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200455#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk69141282003-07-07 20:07:54 +0000456 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
457 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
458/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200459#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk69141282003-07-07 20:07:54 +0000460 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
461 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
462
wdenk69141282003-07-07 20:07:54 +0000463#define CONFIG_SCC1_ENET
464#define CONFIG_FEC_ENET
Heiko Schocherc5e84052010-07-20 17:45:02 +0200465#define CONFIG_ETHPRIME "SCC"
wdenk69141282003-07-07 20:07:54 +0000466
Heiko Schocherc95fa8b2010-02-09 15:50:27 +0100467#define CONFIG_HWCONFIG 1
468
wdenk69141282003-07-07 20:07:54 +0000469#endif /* __CONFIG_H */