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git01.mediatek.com / filogic / uboot / 7c19f91043e86525c54cf339d53bf01c1b726931 / . / test / dm / clk.c
blob: 01417fbd8257d5149aa637959c2a30b350633f2c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]2/*
3 * Copyright (C) 2015 Google, Inc
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]4 */
5
6#include <common.h>
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]7#include <clk.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]8#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]9#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -0700[diff] [blame]10#include <malloc.h>
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]11#include <asm/clk.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]12#include <dm/test.h>
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]13#include <dm/device-internal.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]14#include <linux/err.h>
Simon Glass75c4d412020-07-19 10:15:37 -0600[diff] [blame]15#include <test/test.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]16#include <test/ut.h>
17
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]18/* Base test of the clk uclass */
19static int dm_test_clk_base(struct unit_test_state *uts)
20{
21 struct udevice *dev;
22 struct clk clk_method1;
23 struct clk clk_method2;
24
25 /* Get the device using the clk device */
26 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &dev));
27
28 /* Get the same clk port in 2 different ways and compare */
Samuel Hollandbae0f4f2023-01-21 18:02:51 -0600[diff] [blame]29 ut_assertok(clk_get_by_index(dev, 0, &clk_method1));
30 ut_assertok(clk_get_by_name(dev, NULL, &clk_method2));
31 ut_asserteq(clk_is_match(&clk_method1, &clk_method2), true);
32 ut_asserteq(clk_method1.id, clk_method2.id);
33
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]34 ut_assertok(clk_get_by_index(dev, 1, &clk_method1));
35 ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2));
Sekhar Noricf3119d2019-08-01 19:12:55 +0530[diff] [blame]36 ut_asserteq(clk_is_match(&clk_method1, &clk_method2), true);
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]37 ut_asserteq(clk_method1.id, clk_method2.id);
38
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200[diff] [blame]39 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test2", &dev));
40 ut_assertok(clk_set_defaults(dev, CLK_DEFAULTS_PRE));
41
42 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test3", &dev));
43 ut_assertok(clk_set_defaults(dev, CLK_DEFAULTS_PRE));
44
45 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test4", &dev));
46 ut_assertok(clk_set_defaults(dev, CLK_DEFAULTS_PRE));
47
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]48 return 0;
49}
50
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]51DM_TEST(dm_test_clk_base, UT_TESTF_SCAN_FDT);
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]52
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]53static int dm_test_clk(struct unit_test_state *uts)
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]54{
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]55 struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test;
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]56 ulong rate;
57
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]58 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed",
59 &dev_fixed));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]60
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]61 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed-factor",
62 &dev_fixed_factor));
63
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]64 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
65 &dev_clk));
66 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
67 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
68 ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
69 ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]70
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]71 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
72 &dev_test));
73 ut_assertok(sandbox_clk_test_get(dev_test));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]74 ut_assertok(sandbox_clk_test_devm_get(dev_test));
Fabrice Gasnier11192712018-07-24 16:31:28 +0200[diff] [blame]75 ut_assertok(sandbox_clk_test_valid(dev_test));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]76
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]77 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
78 SANDBOX_CLK_TEST_ID_DEVM_NULL));
79 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
80 SANDBOX_CLK_TEST_ID_DEVM_NULL,
81 0));
82 ut_asserteq(0, sandbox_clk_test_enable(dev_test,
83 SANDBOX_CLK_TEST_ID_DEVM_NULL));
84 ut_asserteq(0, sandbox_clk_test_disable(dev_test,
85 SANDBOX_CLK_TEST_ID_DEVM_NULL));
86
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]87 ut_asserteq(1234,
88 sandbox_clk_test_get_rate(dev_test,
89 SANDBOX_CLK_TEST_ID_FIXED));
90 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
91 SANDBOX_CLK_TEST_ID_SPI));
92 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
93 SANDBOX_CLK_TEST_ID_I2C));
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200[diff] [blame]94 ut_asserteq(321, sandbox_clk_test_get_rate(dev_test,
95 SANDBOX_CLK_TEST_ID_DEVM1));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]96 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
97 SANDBOX_CLK_TEST_ID_DEVM2));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]98
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]99 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED,
100 12345);
101 ut_assert(IS_ERR_VALUE(rate));
102 rate = sandbox_clk_test_get_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED);
103 ut_asserteq(1234, rate);
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]104
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]105 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
106 SANDBOX_CLK_TEST_ID_SPI,
107 1000));
108 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
109 SANDBOX_CLK_TEST_ID_I2C,
110 2000));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]111
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]112 ut_asserteq(1000, sandbox_clk_test_get_rate(dev_test,
113 SANDBOX_CLK_TEST_ID_SPI));
114 ut_asserteq(2000, sandbox_clk_test_get_rate(dev_test,
115 SANDBOX_CLK_TEST_ID_I2C));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]116
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]117 ut_asserteq(1000, sandbox_clk_test_set_rate(dev_test,
118 SANDBOX_CLK_TEST_ID_SPI,
119 10000));
120 ut_asserteq(2000, sandbox_clk_test_set_rate(dev_test,
121 SANDBOX_CLK_TEST_ID_I2C,
122 20000));
123
124 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_SPI, 0);
125 ut_assert(IS_ERR_VALUE(rate));
126 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_I2C, 0);
127 ut_assert(IS_ERR_VALUE(rate));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]128
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]129 ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
130 SANDBOX_CLK_TEST_ID_SPI));
131 ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
132 SANDBOX_CLK_TEST_ID_I2C));
133
Dario Binacchib7f85892020-12-30 00:06:31 +0100[diff] [blame]134 ut_asserteq(5000, sandbox_clk_test_round_rate(dev_test,
135 SANDBOX_CLK_TEST_ID_SPI,
136 5000));
137 ut_asserteq(7000, sandbox_clk_test_round_rate(dev_test,
138 SANDBOX_CLK_TEST_ID_I2C,
139 7000));
140
141 ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
142 SANDBOX_CLK_TEST_ID_SPI));
143 ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
144 SANDBOX_CLK_TEST_ID_I2C));
145
146 rate = sandbox_clk_test_round_rate(dev_test, SANDBOX_CLK_TEST_ID_SPI, 0);
147 ut_assert(IS_ERR_VALUE(rate));
148 rate = sandbox_clk_test_round_rate(dev_test, SANDBOX_CLK_TEST_ID_I2C, 0);
149 ut_assert(IS_ERR_VALUE(rate));
150
151 ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
152 SANDBOX_CLK_TEST_ID_SPI));
153 ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
154 SANDBOX_CLK_TEST_ID_I2C));
155
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]156 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
157 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
158 ut_asserteq(10000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
159 ut_asserteq(20000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
160
161 ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_SPI));
162 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
163 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
164
165 ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_I2C));
166 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
167 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
168
169 ut_assertok(sandbox_clk_test_disable(dev_test,
170 SANDBOX_CLK_TEST_ID_SPI));
171 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
172 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
173
174 ut_assertok(sandbox_clk_test_disable(dev_test,
175 SANDBOX_CLK_TEST_ID_I2C));
176 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
177 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
178
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]179 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
180 SANDBOX_CLK_ID_SPI));
181 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
182 SANDBOX_CLK_ID_I2C));
183 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
184 SANDBOX_CLK_ID_UART2));
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]185 ut_assertok(sandbox_clk_test_free(dev_test));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]186 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
187 SANDBOX_CLK_ID_SPI));
188 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
189 SANDBOX_CLK_ID_I2C));
190 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
191 SANDBOX_CLK_ID_UART2));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]192
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]193 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
194 SANDBOX_CLK_ID_UART1));
195 ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
196 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
197 SANDBOX_CLK_ID_UART1));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]198 return 0;
199}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]200DM_TEST(dm_test_clk, UT_TESTF_SCAN_FDT);
Neil Armstrong567a38b2018-04-03 11:44:19 +0200[diff] [blame]201
202static int dm_test_clk_bulk(struct unit_test_state *uts)
203{
204 struct udevice *dev_clk, *dev_test;
205
206 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
207 &dev_clk));
208 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
209 &dev_test));
210 ut_assertok(sandbox_clk_test_get_bulk(dev_test));
211
212 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
213 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
214
215 /* Fixed clock does not support enable, thus should not fail */
216 ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
217 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
218 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
219
220 /* Fixed clock does not support disable, thus should not fail */
221 ut_assertok(sandbox_clk_test_disable_bulk(dev_test));
222 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
223 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
224
225 /* Fixed clock does not support enable, thus should not fail */
226 ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
227 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
228 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
229
230 /* Fixed clock does not support disable, thus should not fail */
231 ut_assertok(sandbox_clk_test_release_bulk(dev_test));
232 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
233 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]234 ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
Neil Armstrong567a38b2018-04-03 11:44:19 +0200[diff] [blame]235
236 return 0;
237}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]238DM_TEST(dm_test_clk_bulk, UT_TESTF_SCAN_FDT);