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git01.mediatek.com / filogic / uboot / 7b85234a5f16eceecb2c9bccfc6cae6adddd883f / . / board / ms7722se / lowlevel_init.S
blob: d4484ef1f0b63799443b6d218909c76d03232f61 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]2/*
3 * Copyright (C) 2007
4 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Wolfgang Denk0a5c2142007-12-27 01:52:50 +0100[diff] [blame]5 *
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]6 * Copyright (C) 2007
7 * Kenati Technologies, Inc.
8 *
9 * board/ms7722se/lowlevel_init.S
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]10 */
11
12#include <config.h>
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]13
14#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]15#include <asm/macro.h>
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]16
17/*
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]18 * Board specific low level init code, called _very_ early in the
19 * startup sequence. Relocation to SDRAM has not happened yet, no
20 * stack is available, bss section has not been initialised, etc.
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]21 *
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]22 * (Note: As no stack is available, no subroutines can be called...).
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]23 */
24
25 .global lowlevel_init
26
27 .text
28 .align 2
29
30lowlevel_init:
31
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]32 /*
33 * Cache Control Register
34 * Instruction Cache Invalidate
35 */
36 write32 CCR_A, CCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]37
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]38 /*
39 * Address of MMU Control Register
40 * TI == TLB Invalidate bit
41 */
42 write32 MMUCR_A, MMUCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]43
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]44 /* Address of Power Control Register 0 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]45 write32 MSTPCR0_A, MSTPCR0_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]46
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]47 /* Address of Power Control Register 2 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]48 write32 MSTPCR2_A, MSTPCR2_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]49
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]50 write16 SBSCR_A, SBSCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]51
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]52 write16 PSCR_A, PSCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]53
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]54 /* 0xA4520004 (Watchdog Control / Status Register) */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]55! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]56
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]57 /* 0xA4520000 (Watchdog Count Register) */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]58 write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]59
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]60 /* 0xA4520004 (Watchdog Control / Status Register) */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]61 write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]62
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]63 /* 0xA4150000 Frequency control register */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]64 write32 FRQCR_A, FRQCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]65
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]66 write32 CCR_A, CCR_D_2
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]67
68bsc_init:
69
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]70 write16 PSELA_A, PSELA_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]71
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]72 write16 DRVCR_A, DRVCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]73
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]74 write16 PCCR_A, PCCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]75
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]76 write16 PECR_A, PECR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]77
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]78 write16 PJCR_A, PJCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]79
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]80 write16 PXCR_A, PXCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]81
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]82 write32 CMNCR_A, CMNCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]83
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]84 write32 CS0BCR_A, CS0BCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]85
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]86 write32 CS2BCR_A, CS2BCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]87
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]88 write32 CS4BCR_A, CS4BCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]89
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]90 write32 CS5ABCR_A, CS5ABCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]91
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]92 write32 CS5BBCR_A, CS5BBCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]93
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]94 write32 CS6ABCR_A, CS6ABCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]95
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]96 write32 CS0WCR_A, CS0WCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]97
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]98 write32 CS2WCR_A, CS2WCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]99
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]100 write32 CS4WCR_A, CS4WCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]101
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]102 write32 CS5AWCR_A, CS5AWCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]103
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]104 write32 CS5BWCR_A, CS5BWCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]105
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]106 write32 CS6AWCR_A, CS6AWCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]107
108 ! SDRAM initialization
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]109 write32 SDCR_A, SDCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]110
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]111 write32 SDWCR_A, SDWCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]112
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]113 write32 SDPCR_A, SDPCR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]114
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]115 write32 RTCOR_A, RTCOR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]116
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]117 write32 RTCSR_A, RTCSR_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]118
Nobuhiro Iwamatsufcbff802009-01-11 17:48:56 +0900[diff] [blame]119 write8 SDMR3_A, SDMR3_D
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]120
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]121 ! BL bit off (init = ON) (?!?)
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]122
123 stc sr, r0 ! BL bit off(init=ON)
124 mov.l SR_MASK_D, r1
125 and r1, r0
126 ldc r0, sr
127
128 rts
129 mov #0, r0
130
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]131 .align 2
132
Wolfgang Denk0a5c2142007-12-27 01:52:50 +0100[diff] [blame]133CCR_A: .long CCR
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]134MMUCR_A: .long MMUCR
135MSTPCR0_A: .long MSTPCR0
136MSTPCR2_A: .long MSTPCR2
137SBSCR_A: .long SBSCR
138PSCR_A: .long PSCR
139RWTCSR_A: .long RWTCSR
140RWTCNT_A: .long RWTCNT
141FRQCR_A: .long FRQCR
142
143CCR_D: .long 0x00000800
144CCR_D_2: .long 0x00000103
145MMUCR_D: .long 0x00000004
146MSTPCR0_D: .long 0x00001001
147MSTPCR2_D: .long 0xffffffff
148FRQCR_D: .long 0x07022538
149
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]150PSELA_A: .long 0xa405014E
151PSELA_D: .word 0x0A10
Wolfgang Denk0a5c2142007-12-27 01:52:50 +0100[diff] [blame]152 .align 2
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]153
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]154DRVCR_A: .long 0xa405018A
155DRVCR_D: .word 0x0554
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]156 .align 2
157
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]158PCCR_A: .long 0xa4050104
159PCCR_D: .word 0x8800
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]160 .align 2
161
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]162PECR_A: .long 0xa4050108
163PECR_D: .word 0x0000
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]164 .align 2
165
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]166PJCR_A: .long 0xa4050110
167PJCR_D: .word 0x1000
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]168 .align 2
169
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]170PXCR_A: .long 0xa4050148
171PXCR_D: .word 0x0AAA
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]172 .align 2
173
174CMNCR_A: .long CMNCR
175CMNCR_D: .long 0x00000013
176CS0BCR_A: .long CS0BCR ! Flash bank 1
177CS0BCR_D: .long 0x24920400
178CS2BCR_A: .long CS2BCR ! SRAM
179CS2BCR_D: .long 0x24920400
180CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
181CS4BCR_D: .long 0x24920400
182CS5ABCR_A: .long CS5ABCR ! Ext slot
183CS5ABCR_D: .long 0x24920400
184CS5BBCR_A: .long CS5BBCR ! USB controller
185CS5BBCR_D: .long 0x24920400
186CS6ABCR_A: .long CS6ABCR ! Ethernet
187CS6ABCR_D: .long 0x24920400
188
189CS0WCR_A: .long CS0WCR
190CS0WCR_D: .long 0x00000300
191CS2WCR_A: .long CS2WCR
192CS2WCR_D: .long 0x00000300
193CS4WCR_A: .long CS4WCR
194CS4WCR_D: .long 0x00000300
195CS5AWCR_A: .long CS5AWCR
196CS5AWCR_D: .long 0x00000300
197CS5BWCR_A: .long CS5BWCR
198CS5BWCR_D: .long 0x00000300
199CS6AWCR_A: .long CS6AWCR
200CS6AWCR_D: .long 0x00000300
201
202SDCR_A: .long SBSC_SDCR
203SDCR_D: .long 0x00020809
204SDWCR_A: .long SBSC_SDWCR
205SDWCR_D: .long 0x00164d0d
206SDPCR_A: .long SBSC_SDPCR
207SDPCR_D: .long 0x00000087
208RTCOR_A: .long SBSC_RTCOR
209RTCOR_D: .long 0xA55A0034
210RTCSR_A: .long SBSC_RTCSR
211RTCSR_D: .long 0xA55A0010
212SDMR3_A: .long 0xFE500180
Nobuhiro Iwamatsufcbff802009-01-11 17:48:56 +0900[diff] [blame]213SDMR3_D: .long 0x0
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]214
215 .align 1
216
217SBSCR_D: .word 0x0040
218PSCR_D: .word 0x0000
219RWTCSR_D_1: .word 0xA507
220RWTCSR_D_2: .word 0xA507
221RWTCNT_D: .word 0x5A00
Nobuhiro Iwamatsue58917e2008-09-18 19:34:36 +0900[diff] [blame]222 .align 2
Nobuhiro Iwamatsudabcc0e2007-09-23 02:31:13 +0900[diff] [blame]223
224SR_MASK_D: .long 0xEFFFFF0F