blob: 45163edd8dd7551dd39b6b50b6eeeebe43b6607b [file] [log] [blame]
Daniel Hellstrome045a4c2008-03-26 23:34:47 +01001/* Configuration header file for Gaisler Research AB's Template
2 * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
3 * Development board Stratix II edition, with the FPGA device
4 * EP2S60.
5 *
6 * (C) Copyright 2003-2005
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * (C) Copyright 2008
10 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
11 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010013 */
14
15#ifndef __CONFIG_H__
16#define __CONFIG_H__
17
Francois Retiefb131cc52015-10-29 00:02:48 +020018#define CONFIG_SYS_GENERIC_BOARD
Francois Retief703d0242015-10-28 16:49:02 +020019#define CONFIG_DISPLAY_BOARDINFO
Francois Retiefb131cc52015-10-29 00:02:48 +020020
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010021/*
22 * High Level Configuration Options
23 * (easy to change)
24 */
25
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010026/* Altera NIOS Development board, Stratix II board */
Wolfgang Denka1be4762008-05-20 16:00:29 +020027#define CONFIG_GR_EP2S60 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010028
29/* CPU / AMBA BUS configuration */
Wolfgang Denka1be4762008-05-20 16:00:29 +020030#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010031
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010032/* Define this is the GR-2S60-MEZZ mezzanine is available and you
33 * want to use the USB and GRETH functionality of the board
34 */
35#undef GR_2S60_MEZZ
36
37#ifdef GR_2S60_MEZZ
38#define USE_GRETH 1
39#define USE_GRUSB 1
40#endif
41
42/*
43 * Serial console configuration
44 */
45#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010047
48/* Partitions */
49#define CONFIG_DOS_PARTITION
50#define CONFIG_MAC_PARTITION
51#define CONFIG_ISO_PARTITION
52
53/*
54 * Supported commands
55 */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010056#define CONFIG_CMD_REGINFO
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010057#define CONFIG_CMD_PING
58#define CONFIG_CMD_DIAG
59#define CONFIG_CMD_IRQ
60
61/* USB support */
62#if USE_GRUSB
63#define CONFIG_USB_UHCI
64#define CONFIG_CMD_FAT
65#define CONFIG_CMD_EXT2
66#define CONFIG_CMD_USB
67#define CONFIG_USB_STORAGE
68/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD2a7a0312009-05-16 12:14:54 +020069#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010070#endif
71
72/*
73 * Autobooting
74 */
75#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
76
77#define CONFIG_PREBOOT "echo;" \
78 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
79 "echo"
80
81#undef CONFIG_BOOTARGS
82
83#define CONFIG_EXTRA_ENV_SETTINGS \
84 "netdev=eth0\0" \
85 "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
86 "nfsroot=${serverip}:${rootpath}\0" \
87 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
88 "addip=setenv bootargs ${bootargs} " \
89 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
90 ":${hostname}:${netdev}:off panic=1\0" \
91 "flash_nfs=run nfsargs addip;" \
92 "bootm ${kernel_addr}\0" \
93 "flash_self=run ramargs addip;" \
94 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
95 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
96 "scratch=40800000\0" \
Mike Frysingerc3c6bf12011-10-12 19:47:51 +000097 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010098 "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
99 ""
100
101#define CONFIG_NETMASK 255.255.255.0
102#define CONFIG_GATEWAYIP 192.168.0.1
103#define CONFIG_SERVERIP 192.168.0.20
104#define CONFIG_IPADDR 192.168.0.207
Joe Hershberger257ff782011-10-13 13:03:47 +0000105#define CONFIG_ROOTPATH "/export/rootfs"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100106#define CONFIG_HOSTNAME ml401
Joe Hershbergere4da2482011-10-13 13:03:48 +0000107#define CONFIG_BOOTFILE "/uImage"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100108
109#define CONFIG_BOOTCOMMAND "run flash_self"
110
111/* Memory MAP
112 *
113 * Flash:
114 * |--------------------------------|
115 * | 0x00000000 Text & Data & BSS | *
116 * | for Monitor | *
117 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
118 * | UNUSED / Growth | * 256kb
119 * |--------------------------------|
120 * | 0x00050000 Base custom area | *
121 * | kernel / FS | *
122 * | | * Rest of Flash
123 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
124 * | END-0x00008000 Environment | * 32kb
125 * |--------------------------------|
126 *
127 *
128 *
129 * Main Memory:
130 * |--------------------------------|
131 * | UNUSED / scratch area |
132 * | |
133 * | |
134 * | |
135 * | |
136 * |--------------------------------|
137 * | Monitor .Text / .DATA / .BSS | * 512kb
138 * | Relocated! | *
139 * |--------------------------------|
140 * | Monitor Malloc | * 128kb (contains relocated environment)
141 * |--------------------------------|
142 * | Monitor/kernel STACK | * 64kb
143 * |--------------------------------|
144 * | Page Table for MMU systems | * 2k
145 * |--------------------------------|
146 * | PROM Code accessed from Linux | * 6kb-128b
147 * |--------------------------------|
148 * | Global data (avail from kernel)| * 128b
149 * |--------------------------------|
150 *
151 */
152
153/*
154 * Flash configuration (8,16 or 32 MB)
155 * TEXT base always at 0xFFF00000
156 * ENV_ADDR always at 0xFFF40000
157 * FLASH_BASE at 0xFC000000 for 64 MB
158 * 0xFE000000 for 32 MB
159 * 0xFF000000 for 16 MB
160 * 0xFF800000 for 8 MB
161 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162/*#define CONFIG_SYS_NO_FLASH 1*/
163#define CONFIG_SYS_FLASH_BASE 0x00000000
164#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100165
166#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100169
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
171#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
172#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
173#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
174#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100175
176/*** CFI CONFIG ***/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200178#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_CFI
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100180/* Bypass cache when reading regs from flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100182/* Buffered writes (32byte/go) instead of single accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100184
185/*
186 * Environment settings
187 */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200188/*#define CONFIG_ENV_IS_NOWHERE 1*/
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200189#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200190/* CONFIG_ENV_ADDR need to be at sector boundary */
191#define CONFIG_ENV_SIZE 0x8000
192#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100194#define CONFIG_ENV_OVERWRITE 1
195
196/*
197 * Memory map
198 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199#define CONFIG_SYS_SDRAM_BASE 0x40000000
200#define CONFIG_SYS_SDRAM_SIZE 0x02000000
201#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100202
203/* no SRAM available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#undef CONFIG_SYS_SRAM_BASE
205#undef CONFIG_SYS_SRAM_SIZE
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100206
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
208#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
209#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100210
Wolfgang Denk0191e472010-10-26 14:34:52 +0200211#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100212
Wolfgang Denk0191e472010-10-26 14:34:52 +0200213#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100215
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
217#define CONFIG_SYS_STACK_SIZE (0x10000-32)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100218
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200219#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
221# define CONFIG_SYS_RAMBOOT 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100222#endif
223
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
225#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
226#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100227
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
229#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100230
231/* relocated monitor area */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
233#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100234
235/* make un relocated address from relocated address */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200236#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100237
238/*
239 * Ethernet configuration uses on board SMC91C111, however if a mezzanine
240 * with a PHY is attached the GRETH can be used on this board.
241 * Define USE_GRETH in order to use the mezzanine provided PHY with the
242 * onchip GRETH network MAC, note that this is not supported by the
243 * template design.
244 */
245#ifndef USE_GRETH
246
247/* USE SMC91C111 MAC */
Ben Warren0fd6aae2009-10-04 22:37:03 -0700248#define CONFIG_SMC91111 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100249#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
250#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
251#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
252/*#define CONFIG_SHOW_ACTIVITY*/
253#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
254
255#else
256
257/* USE GRETH Ethernet Driver */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100258#define CONFIG_GRETH 1
Masahiro Yamadacbafcdf2015-05-26 10:58:31 +0900259#endif
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100260
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100261#define CONFIG_PHY_ADDR 0x00
262
263/*
264 * Miscellaneous configurable options
265 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200266#define CONFIG_SYS_LONGHELP /* undef to save memory */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100267#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200268#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100269#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100271#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200272#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
273#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
274#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100275
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200276#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
277#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100278
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100280
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100281/*-----------------------------------------------------------------------
282 * USB stuff
283 *-----------------------------------------------------------------------
284 */
285#define CONFIG_USB_CLOCK 0x0001BBBB
286#define CONFIG_USB_CONFIG 0x00005000
287
288/***** Gaisler GRLIB IP-Cores Config ********/
289
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200290#define CONFIG_SYS_GRLIB_SDRAM 0
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100291
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100292/* No SDRAM Configuration */
293#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
294
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100295/* See, GRLIB Docs (grip.pdf) on how to set up
296 * These the memory controller registers.
297 */
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100298#define CONFIG_SYS_GRLIB_ESA_MCTRL1
299#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
300#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
301#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100302
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100303/* GRLIB FT-MCTRL configuration */
304#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
305#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
306#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
307#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100308
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100309/* DDR controller */
310#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
311#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100312
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100313/* no DDR2 Controller */
314#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100315
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100316/* Identification string */
Francois Retief703d0242015-10-28 16:49:02 +0200317#define CONFIG_IDENT_STRING " Gaisler LEON3 EP2S60"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100318
319/* default kernel command line */
320#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
321
322#endif /* __CONFIG_H */