| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Armadeus Systems |
| 4 | * |
| 5 | * Configuration settings for the OPOS6ULDev board |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __OPOS6ULDEV_CONFIG_H |
| 9 | #define __OPOS6ULDEV_CONFIG_H |
| 10 | |
| 11 | #include "mx6_common.h" |
| 12 | |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 13 | /* Miscellaneous configurable options */ |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 14 | |
| 15 | /* Physical Memory Map */ |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 16 | #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 17 | #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 18 | #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 19 | |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 20 | /* USB */ |
| 21 | #ifdef CONFIG_USB_EHCI_MX6 |
| Tom Rini | b9796e8 | 2022-12-04 10:04:56 -0500 | [diff] [blame] | 22 | #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| 23 | #define CFG_MXC_USB_FLAGS 0 |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 24 | #endif |
| 25 | |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 26 | /* LCD */ |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 27 | #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 28 | |
| Sébastien Szymanski | a7762e4 | 2017-03-07 14:33:25 +0100 | [diff] [blame] | 29 | #endif /* __OPOS6ULDEV_CONFIG_H */ |