SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * HW data initialization for OMAP4 |
| 4 | * |
| 5 | * (C) Copyright 2013 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Sricharan R <r.sricharan@ti.com> |
| 9 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 11 | */ |
| 12 | #include <common.h> |
| 13 | #include <asm/arch/omap.h> |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 14 | #include <asm/arch/sys_proto.h> |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 15 | #include <asm/omap_common.h> |
Lokesh Vutla | 61c517f | 2013-05-30 02:54:32 +0000 | [diff] [blame] | 16 | #include <asm/arch/clock.h> |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 17 | #include <asm/omap_gpio.h> |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 18 | #include <asm/io.h> |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 19 | |
| 20 | struct prcm_regs const **prcm = |
| 21 | (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 22 | struct dplls const **dplls_data = |
| 23 | (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 24 | struct vcores_data const **omap_vcores = |
| 25 | (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; |
Lokesh Vutla | 834b6b0 | 2013-02-04 04:22:04 +0000 | [diff] [blame] | 26 | struct omap_sys_ctrl_regs const **ctrl = |
SRICHARAN R | 4b1b61c | 2013-04-24 00:41:22 +0000 | [diff] [blame] | 27 | (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 28 | |
| 29 | /* |
| 30 | * The M & N values in the following tables are created using the |
| 31 | * following tool: |
| 32 | * tools/omap/clocks_get_m_n.c |
| 33 | * Please use this tool for creating the table for any new frequency. |
| 34 | */ |
| 35 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 36 | /* |
| 37 | * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF |
| 38 | * OMAP4460 OPP_NOM frequency |
| 39 | */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 40 | static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 41 | {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 42 | {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 43 | {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 44 | {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 45 | {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 46 | {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 47 | {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 48 | }; |
| 49 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 50 | /* |
| 51 | * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) |
| 52 | * OMAP4430 OPP_TURBO frequency |
Taras Kondratiuk | 6d2e261 | 2013-08-06 15:18:49 +0300 | [diff] [blame] | 53 | * OMAP4470 OPP_NOM frequency |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 54 | */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 55 | static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 56 | {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 57 | {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 58 | {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 59 | {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 60 | {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 61 | {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 62 | {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 63 | }; |
| 64 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 65 | /* |
| 66 | * dpll locked at 1200 MHz - MPU clk at 600 MHz |
| 67 | * OMAP4430 OPP_NOM frequency |
| 68 | */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 69 | static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 70 | {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 71 | {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 72 | {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 73 | {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 74 | {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 75 | {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 76 | {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 77 | }; |
| 78 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 79 | /* OMAP4460 OPP_NOM frequency */ |
Taras Kondratiuk | 6d2e261 | 2013-08-06 15:18:49 +0300 | [diff] [blame] | 80 | /* OMAP4470 OPP_NOM (Low Power) frequency */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 81 | static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 82 | {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ |
| 83 | {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ |
| 84 | {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 85 | {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 86 | {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ |
| 87 | {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ |
| 88 | {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 89 | }; |
| 90 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 91 | /* OMAP4430 ES1 OPP_NOM frequency */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 92 | static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 93 | {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ |
| 94 | {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ |
| 95 | {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 96 | {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 97 | {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ |
| 98 | {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ |
| 99 | {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 100 | }; |
| 101 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 102 | /* OMAP4430 ES2.X OPP_NOM frequency */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 103 | static const struct dpll_params |
| 104 | core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 105 | {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ |
| 106 | {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ |
| 107 | {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 108 | {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 109 | {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ |
| 110 | {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ |
| 111 | {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 112 | }; |
| 113 | |
| 114 | static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 115 | {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */ |
| 116 | {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */ |
| 117 | {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 118 | {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 119 | {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */ |
| 120 | {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */ |
| 121 | {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 125 | {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 126 | {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 127 | {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 128 | {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 129 | {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 130 | {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 131 | {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 132 | }; |
| 133 | |
| 134 | /* ABE M & N values with sys_clk as source */ |
| 135 | static const struct dpll_params |
| 136 | abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 137 | {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 138 | {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 139 | {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 140 | {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 141 | {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 142 | {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 143 | {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | /* ABE M & N values with 32K clock as source */ |
| 147 | static const struct dpll_params abe_dpll_params_32k_196608khz = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 148 | 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 149 | }; |
| 150 | |
| 151 | static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 152 | {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 153 | {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 154 | {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 155 | {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 156 | {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 157 | {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 158 | {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 159 | }; |
| 160 | |
| 161 | struct dplls omap4430_dplls_es1 = { |
| 162 | .mpu = mpu_dpll_params_1200mhz, |
| 163 | .core = core_dpll_params_es1_1524mhz, |
| 164 | .per = per_dpll_params_1536mhz, |
| 165 | .iva = iva_dpll_params_1862mhz, |
| 166 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 167 | .abe = abe_dpll_params_sysclk_196608khz, |
| 168 | #else |
| 169 | .abe = &abe_dpll_params_32k_196608khz, |
| 170 | #endif |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 171 | .usb = usb_dpll_params_1920mhz, |
| 172 | .ddr = NULL |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 173 | }; |
| 174 | |
Janne Grunau | d2b0a89 | 2014-02-16 21:57:18 +0100 | [diff] [blame] | 175 | struct dplls omap4430_dplls_es20 = { |
| 176 | .mpu = mpu_dpll_params_1200mhz, |
| 177 | .core = core_dpll_params_es2_1600mhz_ddr200mhz, |
| 178 | .per = per_dpll_params_1536mhz, |
| 179 | .iva = iva_dpll_params_1862mhz, |
| 180 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 181 | .abe = abe_dpll_params_sysclk_196608khz, |
| 182 | #else |
| 183 | .abe = &abe_dpll_params_32k_196608khz, |
| 184 | #endif |
| 185 | .usb = usb_dpll_params_1920mhz, |
| 186 | .ddr = NULL |
| 187 | }; |
| 188 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 189 | struct dplls omap4430_dplls = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 190 | .mpu = mpu_dpll_params_1200mhz, |
| 191 | .core = core_dpll_params_1600mhz, |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 192 | .per = per_dpll_params_1536mhz, |
| 193 | .iva = iva_dpll_params_1862mhz, |
| 194 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 195 | .abe = abe_dpll_params_sysclk_196608khz, |
| 196 | #else |
| 197 | .abe = &abe_dpll_params_32k_196608khz, |
| 198 | #endif |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 199 | .usb = usb_dpll_params_1920mhz, |
| 200 | .ddr = NULL |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 201 | }; |
| 202 | |
| 203 | struct dplls omap4460_dplls = { |
| 204 | .mpu = mpu_dpll_params_1400mhz, |
| 205 | .core = core_dpll_params_1600mhz, |
| 206 | .per = per_dpll_params_1536mhz, |
| 207 | .iva = iva_dpll_params_1862mhz, |
| 208 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 209 | .abe = abe_dpll_params_sysclk_196608khz, |
| 210 | #else |
| 211 | .abe = &abe_dpll_params_32k_196608khz, |
| 212 | #endif |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 213 | .usb = usb_dpll_params_1920mhz, |
| 214 | .ddr = NULL |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 215 | }; |
| 216 | |
Taras Kondratiuk | 6d2e261 | 2013-08-06 15:18:49 +0300 | [diff] [blame] | 217 | struct dplls omap4470_dplls = { |
| 218 | .mpu = mpu_dpll_params_1600mhz, |
| 219 | .core = core_dpll_params_1600mhz, |
| 220 | .per = per_dpll_params_1536mhz, |
| 221 | .iva = iva_dpll_params_1862mhz, |
| 222 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 223 | .abe = abe_dpll_params_sysclk_196608khz, |
| 224 | #else |
| 225 | .abe = &abe_dpll_params_32k_196608khz, |
| 226 | #endif |
| 227 | .usb = usb_dpll_params_1920mhz, |
| 228 | .ddr = NULL |
| 229 | }; |
| 230 | |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 231 | struct pmic_data twl6030_4430es1 = { |
| 232 | .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, |
Lubomir Popov | c8a3e76 | 2013-04-08 22:05:33 +0000 | [diff] [blame] | 233 | .step = 12660, /* 12.66 mV represented in uV */ |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 234 | /* The code starts at 1 not 0 */ |
| 235 | .start_code = 1, |
Lokesh Vutla | ae49f6d | 2013-05-30 02:54:33 +0000 | [diff] [blame] | 236 | .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, |
| 237 | .pmic_bus_init = sri2c_init, |
| 238 | .pmic_write = omap_vc_bypass_send_value, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 239 | }; |
| 240 | |
Taras Kondratiuk | 6d2e261 | 2013-08-06 15:18:49 +0300 | [diff] [blame] | 241 | /* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 242 | struct pmic_data twl6030 = { |
| 243 | .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, |
Lubomir Popov | c8a3e76 | 2013-04-08 22:05:33 +0000 | [diff] [blame] | 244 | .step = 12660, /* 12.66 mV represented in uV */ |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 245 | /* The code starts at 1 not 0 */ |
| 246 | .start_code = 1, |
Lokesh Vutla | ae49f6d | 2013-05-30 02:54:33 +0000 | [diff] [blame] | 247 | .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, |
| 248 | .pmic_bus_init = sri2c_init, |
| 249 | .pmic_write = omap_vc_bypass_send_value, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 250 | }; |
| 251 | |
| 252 | struct pmic_data tps62361 = { |
| 253 | .base_offset = TPS62361_BASE_VOLT_MV, |
| 254 | .step = 10000, /* 10 mV represented in uV */ |
| 255 | .start_code = 0, |
| 256 | .gpio = TPS62361_VSEL0_GPIO, |
Lokesh Vutla | ae49f6d | 2013-05-30 02:54:33 +0000 | [diff] [blame] | 257 | .gpio_en = 1, |
| 258 | .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, |
| 259 | .pmic_bus_init = sri2c_init, |
| 260 | .pmic_write = omap_vc_bypass_send_value, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 261 | }; |
| 262 | |
| 263 | struct vcores_data omap4430_volts_es1 = { |
| 264 | .mpu.value = 1325, |
| 265 | .mpu.addr = SMPS_REG_ADDR_VCORE1, |
| 266 | .mpu.pmic = &twl6030_4430es1, |
| 267 | |
| 268 | .core.value = 1200, |
| 269 | .core.addr = SMPS_REG_ADDR_VCORE3, |
| 270 | .core.pmic = &twl6030_4430es1, |
| 271 | |
| 272 | .mm.value = 1200, |
| 273 | .mm.addr = SMPS_REG_ADDR_VCORE2, |
| 274 | .mm.pmic = &twl6030_4430es1, |
| 275 | }; |
| 276 | |
| 277 | struct vcores_data omap4430_volts = { |
| 278 | .mpu.value = 1325, |
| 279 | .mpu.addr = SMPS_REG_ADDR_VCORE1, |
| 280 | .mpu.pmic = &twl6030, |
| 281 | |
| 282 | .core.value = 1200, |
| 283 | .core.addr = SMPS_REG_ADDR_VCORE3, |
| 284 | .core.pmic = &twl6030, |
| 285 | |
| 286 | .mm.value = 1200, |
| 287 | .mm.addr = SMPS_REG_ADDR_VCORE2, |
| 288 | .mm.pmic = &twl6030, |
| 289 | }; |
| 290 | |
| 291 | struct vcores_data omap4460_volts = { |
| 292 | .mpu.value = 1203, |
| 293 | .mpu.addr = TPS62361_REG_ADDR_SET1, |
| 294 | .mpu.pmic = &tps62361, |
| 295 | |
| 296 | .core.value = 1200, |
| 297 | .core.addr = SMPS_REG_ADDR_VCORE1, |
Lubomir Popov | c8a3e76 | 2013-04-08 22:05:33 +0000 | [diff] [blame] | 298 | .core.pmic = &twl6030, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 299 | |
| 300 | .mm.value = 1200, |
| 301 | .mm.addr = SMPS_REG_ADDR_VCORE2, |
Lubomir Popov | c8a3e76 | 2013-04-08 22:05:33 +0000 | [diff] [blame] | 302 | .mm.pmic = &twl6030, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 303 | }; |
| 304 | |
Lubomir Popov | 4ec12e9 | 2013-11-20 15:32:17 +0200 | [diff] [blame] | 305 | /* |
| 306 | * Take closest integer part of the mV value corresponding to a TWL6032 SMPS |
| 307 | * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. |
| 308 | */ |
Taras Kondratiuk | 6d2e261 | 2013-08-06 15:18:49 +0300 | [diff] [blame] | 309 | struct vcores_data omap4470_volts = { |
Lubomir Popov | 4ec12e9 | 2013-11-20 15:32:17 +0200 | [diff] [blame] | 310 | .mpu.value = 1202, |
Taras Kondratiuk | 6d2e261 | 2013-08-06 15:18:49 +0300 | [diff] [blame] | 311 | .mpu.addr = SMPS_REG_ADDR_SMPS1, |
| 312 | .mpu.pmic = &twl6030, |
| 313 | |
| 314 | .core.value = 1126, |
Lubomir Popov | 4ec12e9 | 2013-11-20 15:32:17 +0200 | [diff] [blame] | 315 | .core.addr = SMPS_REG_ADDR_SMPS2, |
Taras Kondratiuk | 6d2e261 | 2013-08-06 15:18:49 +0300 | [diff] [blame] | 316 | .core.pmic = &twl6030, |
| 317 | |
Lubomir Popov | 4ec12e9 | 2013-11-20 15:32:17 +0200 | [diff] [blame] | 318 | .mm.value = 1139, |
| 319 | .mm.addr = SMPS_REG_ADDR_SMPS5, |
Taras Kondratiuk | 6d2e261 | 2013-08-06 15:18:49 +0300 | [diff] [blame] | 320 | .mm.pmic = &twl6030, |
| 321 | }; |
| 322 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 323 | /* |
| 324 | * Enable essential clock domains, modules and |
| 325 | * do some additional special settings needed |
| 326 | */ |
| 327 | void enable_basic_clocks(void) |
| 328 | { |
| 329 | u32 const clk_domains_essential[] = { |
| 330 | (*prcm)->cm_l4per_clkstctrl, |
| 331 | (*prcm)->cm_l3init_clkstctrl, |
| 332 | (*prcm)->cm_memif_clkstctrl, |
| 333 | (*prcm)->cm_l4cfg_clkstctrl, |
| 334 | 0 |
| 335 | }; |
| 336 | |
| 337 | u32 const clk_modules_hw_auto_essential[] = { |
Lokesh Vutla | 15c2c70 | 2013-02-17 23:33:37 +0000 | [diff] [blame] | 338 | (*prcm)->cm_l3_gpmc_clkctrl, |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 339 | (*prcm)->cm_memif_emif_1_clkctrl, |
| 340 | (*prcm)->cm_memif_emif_2_clkctrl, |
| 341 | (*prcm)->cm_l4cfg_l4_cfg_clkctrl, |
| 342 | (*prcm)->cm_wkup_gpio1_clkctrl, |
| 343 | (*prcm)->cm_l4per_gpio2_clkctrl, |
| 344 | (*prcm)->cm_l4per_gpio3_clkctrl, |
| 345 | (*prcm)->cm_l4per_gpio4_clkctrl, |
| 346 | (*prcm)->cm_l4per_gpio5_clkctrl, |
| 347 | (*prcm)->cm_l4per_gpio6_clkctrl, |
| 348 | 0 |
| 349 | }; |
| 350 | |
| 351 | u32 const clk_modules_explicit_en_essential[] = { |
| 352 | (*prcm)->cm_wkup_gptimer1_clkctrl, |
| 353 | (*prcm)->cm_l3init_hsmmc1_clkctrl, |
| 354 | (*prcm)->cm_l3init_hsmmc2_clkctrl, |
| 355 | (*prcm)->cm_l4per_gptimer2_clkctrl, |
| 356 | (*prcm)->cm_wkup_wdtimer2_clkctrl, |
| 357 | (*prcm)->cm_l4per_uart3_clkctrl, |
| 358 | 0 |
| 359 | }; |
| 360 | |
| 361 | /* Enable optional additional functional clock for GPIO4 */ |
| 362 | setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, |
| 363 | GPIO4_CLKCTRL_OPTFCLKEN_MASK); |
| 364 | |
| 365 | /* Enable 96 MHz clock for MMC1 & MMC2 */ |
| 366 | setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, |
| 367 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 368 | setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, |
| 369 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 370 | |
| 371 | /* Select 32KHz clock as the source of GPTIMER1 */ |
| 372 | setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, |
| 373 | GPTIMER1_CLKCTRL_CLKSEL_MASK); |
| 374 | |
| 375 | /* Enable optional 48M functional clock for USB PHY */ |
| 376 | setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, |
| 377 | USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); |
| 378 | |
| 379 | do_enable_clocks(clk_domains_essential, |
| 380 | clk_modules_hw_auto_essential, |
| 381 | clk_modules_explicit_en_essential, |
| 382 | 1); |
| 383 | } |
| 384 | |
| 385 | void enable_basic_uboot_clocks(void) |
| 386 | { |
| 387 | u32 const clk_domains_essential[] = { |
| 388 | 0 |
| 389 | }; |
| 390 | |
| 391 | u32 const clk_modules_hw_auto_essential[] = { |
| 392 | (*prcm)->cm_l3init_hsusbotg_clkctrl, |
| 393 | (*prcm)->cm_l3init_usbphy_clkctrl, |
| 394 | (*prcm)->cm_l3init_usbphy_clkctrl, |
| 395 | (*prcm)->cm_clksel_usb_60mhz, |
| 396 | (*prcm)->cm_l3init_hsusbtll_clkctrl, |
| 397 | 0 |
| 398 | }; |
| 399 | |
| 400 | u32 const clk_modules_explicit_en_essential[] = { |
| 401 | (*prcm)->cm_l4per_mcspi1_clkctrl, |
| 402 | (*prcm)->cm_l4per_i2c1_clkctrl, |
| 403 | (*prcm)->cm_l4per_i2c2_clkctrl, |
| 404 | (*prcm)->cm_l4per_i2c3_clkctrl, |
| 405 | (*prcm)->cm_l4per_i2c4_clkctrl, |
| 406 | (*prcm)->cm_l3init_hsusbhost_clkctrl, |
| 407 | 0 |
| 408 | }; |
| 409 | |
| 410 | do_enable_clocks(clk_domains_essential, |
| 411 | clk_modules_hw_auto_essential, |
| 412 | clk_modules_explicit_en_essential, |
| 413 | 1); |
| 414 | } |
| 415 | |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 416 | void hw_data_init(void) |
| 417 | { |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 418 | u32 omap_rev = omap_revision(); |
| 419 | |
| 420 | (*prcm) = &omap4_prcm; |
| 421 | |
| 422 | switch (omap_rev) { |
| 423 | |
| 424 | case OMAP4430_ES1_0: |
| 425 | *dplls_data = &omap4430_dplls_es1; |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 426 | *omap_vcores = &omap4430_volts_es1; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 427 | break; |
| 428 | |
| 429 | case OMAP4430_ES2_0: |
Janne Grunau | d2b0a89 | 2014-02-16 21:57:18 +0100 | [diff] [blame] | 430 | *dplls_data = &omap4430_dplls_es20; |
| 431 | *omap_vcores = &omap4430_volts; |
| 432 | break; |
| 433 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 434 | case OMAP4430_ES2_1: |
| 435 | case OMAP4430_ES2_2: |
| 436 | case OMAP4430_ES2_3: |
| 437 | *dplls_data = &omap4430_dplls; |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 438 | *omap_vcores = &omap4430_volts; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 439 | break; |
| 440 | |
| 441 | case OMAP4460_ES1_0: |
| 442 | case OMAP4460_ES1_1: |
| 443 | *dplls_data = &omap4460_dplls; |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 444 | *omap_vcores = &omap4460_volts; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 445 | break; |
| 446 | |
Taras Kondratiuk | 6d2e261 | 2013-08-06 15:18:49 +0300 | [diff] [blame] | 447 | case OMAP4470_ES1_0: |
| 448 | *dplls_data = &omap4470_dplls; |
| 449 | *omap_vcores = &omap4470_volts; |
| 450 | break; |
| 451 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 452 | default: |
| 453 | printf("\n INVALID OMAP REVISION "); |
| 454 | } |
| 455 | |
Lokesh Vutla | 834b6b0 | 2013-02-04 04:22:04 +0000 | [diff] [blame] | 456 | *ctrl = &omap4_ctrl; |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 457 | } |