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Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05001/*
2 * WindRiver SBC8349 U-Boot configuration file.
3 * Copyright (c) 2006, 2007 Wind River Systems, Inc.
4 *
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on the MPC8349EMDS config.
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05009 */
10
11/*
12 * sbc8349 board configuration file.
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
Kim Phillipsd2f66b82015-03-17 12:00:45 -050018#define CONFIG_DISPLAY_BOARDINFO
19
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050020/*
21 * High Level Configuration Options
22 */
23#define CONFIG_E300 1 /* E300 Family */
Peter Tyser72f2d392009-05-22 17:23:25 -050024#define CONFIG_MPC834x 1 /* MPC834x family */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050025#define CONFIG_MPC8349 1 /* MPC8349 specific */
26#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
27
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020028#define CONFIG_SYS_TEXT_BASE 0xFF800000
29
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050030/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
31#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
32
Paul Gortmaker0aaee142009-08-21 16:21:58 -050033/*
34 * The default if PCI isn't enabled, or if no PCI clk setting is given
35 * is 66MHz; this is what the board defaults to when the PCI slot is
36 * physically empty. The board will automatically (i.e w/o jumpers)
37 * clock down to 33MHz if you insert a 33MHz PCI card.
38 */
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020039#ifdef CONFIG_PCI_33M
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050040#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
Paul Gortmaker0aaee142009-08-21 16:21:58 -050041#else /* 66M */
42#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050043#endif
44
45#ifndef CONFIG_SYS_CLK_FREQ
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020046#ifdef CONFIG_PCI_33M
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050047#define CONFIG_SYS_CLK_FREQ 33000000
48#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
Paul Gortmaker0aaee142009-08-21 16:21:58 -050049#else /* 66M */
50#define CONFIG_SYS_CLK_FREQ 66000000
51#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050052#endif
53#endif
54
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050055#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
56
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#define CONFIG_SYS_IMMR 0xE0000000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050058
Joe Hershberger10c26172011-10-11 23:57:25 -050059#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
61#define CONFIG_SYS_MEMTEST_END 0x00100000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050062
63/*
64 * DDR Setup
65 */
66#undef CONFIG_DDR_ECC /* only for ECC DDR module */
67#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
68#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
Joe Hershberger10c26172011-10-11 23:57:25 -050069#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050070
71/*
72 * 32-bit data path mode.
73 *
74 * Please note that using this mode for devices with the real density of 64-bit
75 * effectively reduces the amount of available memory due to the effect of
76 * wrapping around while translating address to row/columns, for example in the
77 * 256MB module the upper 128MB get aliased with contents of the lower
78 * 128MB); normally this define should be used for devices with real 32-bit
79 * data path.
80 */
81#undef CONFIG_DDR_32BIT
82
Joe Hershberger10c26172011-10-11 23:57:25 -050083#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
85#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
86#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050087 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
88#define CONFIG_DDR_2T_TIMING
89
90#if defined(CONFIG_SPD_EEPROM)
91/*
92 * Determine DDR configuration from I2C interface.
93 */
94#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
95
96#else
97/*
98 * Manually set up DDR parameters
99 * NB: manual DDR setup untested on sbc834x
100 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Joe Hershberger5ade3902011-10-11 23:57:31 -0500102#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
Joe Hershberger10c26172011-10-11 23:57:25 -0500103 | CSCONFIG_ROW_BIT_13 \
104 | CSCONFIG_COL_BIT_10)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200105#define CONFIG_SYS_DDR_TIMING_1 0x36332321
106#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
Joe Hershberger10c26172011-10-11 23:57:25 -0500107#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500109
110#if defined(CONFIG_DDR_32BIT)
111/* set burst length to 8 for 32-bit data path */
Joe Hershberger10c26172011-10-11 23:57:25 -0500112 /* DLL,normal,seq,4/2.5, 8 burst len */
113#define CONFIG_SYS_DDR_MODE 0x00000023
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500114#else
115/* the default burst length is 4 - for 64-bit data path */
Joe Hershberger10c26172011-10-11 23:57:25 -0500116 /* DLL,normal,seq,4/2.5, 4 burst len */
117#define CONFIG_SYS_DDR_MODE 0x00000022
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500118#endif
119#endif
120
121/*
122 * SDRAM on the Local Bus
123 */
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500124#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
125#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500126
127/*
128 * FLASH on the Local Bus
129 */
Joe Hershberger10c26172011-10-11 23:57:25 -0500130#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
131#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
133#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
134/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500135
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500136#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
137 | BR_PS_16 /* 16 bit port */ \
138 | BR_MS_GPCM /* MSEL = GPCM */ \
139 | BR_V) /* valid */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500140
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500141#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
142 | OR_GPCM_XAM \
143 | OR_GPCM_CSNT \
144 | OR_GPCM_ACS_DIV2 \
145 | OR_GPCM_XACS \
146 | OR_GPCM_SCY_15 \
147 | OR_GPCM_TRLX_SET \
148 | OR_GPCM_EHTR_SET \
149 | OR_GPCM_EAD)
150 /* 0xFF806FF7 */
151
Joe Hershberger10c26172011-10-11 23:57:25 -0500152 /* window base at flash base */
153#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500154#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500155
Joe Hershberger10c26172011-10-11 23:57:25 -0500156#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
157#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500158
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200159#undef CONFIG_SYS_FLASH_CHECKSUM
160#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
161#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500162
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200163#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500164
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
166#define CONFIG_SYS_RAMBOOT
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500167#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#undef CONFIG_SYS_RAMBOOT
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500169#endif
170
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger10c26172011-10-11 23:57:25 -0500172 /* Initial RAM address */
173#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
174 /* Size of used area in RAM*/
175#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500176
Joe Hershberger10c26172011-10-11 23:57:25 -0500177#define CONFIG_SYS_GBL_DATA_OFFSET \
178 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500180
Joe Hershberger10c26172011-10-11 23:57:25 -0500181#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
Kim Phillips831d2f62012-06-30 18:29:20 -0500182#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500183
184/*
185 * Local Bus LCRR and LBCR regs
186 * LCRR: DLL bypass, Clock divider is 4
187 * External Local Bus rate is
188 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
189 */
Kim Phillips328040a2009-09-25 18:19:44 -0500190#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
191#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_LBC_LBCR 0x00000000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500193
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500195
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#ifdef CONFIG_SYS_LB_SDRAM
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500197/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
198/*
199 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500201 *
202 * For BR2, need:
203 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
204 * port-size = 32-bits = BR2[19:20] = 11
205 * no parity checking = BR2[21:22] = 00
206 * SDRAM for MSEL = BR2[24:26] = 011
207 * Valid = BR[31] = 1
208 *
209 * 0 4 8 12 16 20 24 28
210 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500211 */
212
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500213#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
214 | BR_PS_32 \
215 | BR_MS_SDRAM \
216 | BR_V)
217 /* 0xF0001861 */
218#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
219#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500220
221/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500223 *
224 * For OR2, need:
225 * 64MB mask for AM, OR2[0:7] = 1111 1100
226 * XAM, OR2[17:18] = 11
227 * 9 columns OR2[19-21] = 010
228 * 13 rows OR2[23-25] = 100
229 * EAD set for extra time OR[31] = 1
230 *
231 * 0 4 8 12 16 20 24 28
232 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
233 */
234
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500235#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
236 | OR_SDRAM_XAM \
237 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
238 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
239 | OR_SDRAM_EAD)
240 /* 0xFC006901 */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500241
Joe Hershberger10c26172011-10-11 23:57:25 -0500242 /* LB sdram refresh timer, about 6us */
243#define CONFIG_SYS_LBC_LSRT 0x32000000
244 /* LB refresh timer prescal, 266MHz/32 */
245#define CONFIG_SYS_LBC_MRTPR 0x20000000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500246
Joe Hershberger10c26172011-10-11 23:57:25 -0500247#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
248 | LSDMR_BSMA1516 \
249 | LSDMR_RFCR8 \
250 | LSDMR_PRETOACT6 \
251 | LSDMR_ACTTORW3 \
252 | LSDMR_BL8 \
253 | LSDMR_WRC3 \
254 | LSDMR_CL3)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500255
256/*
257 * SDRAM Controller configuration sequence.
258 */
Kumar Galaac05b5e2009-03-26 01:34:39 -0500259#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
260#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
261#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
262#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
263#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500264#endif
265
266/*
267 * Serial Port
268 */
269#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270#define CONFIG_SYS_NS16550_SERIAL
271#define CONFIG_SYS_NS16550_REG_SIZE 1
272#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500273
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200274#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger10c26172011-10-11 23:57:25 -0500275 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500276
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200277#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
278#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500279
Kim Phillipsf3c14782007-02-27 18:41:08 -0600280#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips26c16d82010-04-15 17:36:05 -0500281#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500282/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283#define CONFIG_SYS_HUSH_PARSER
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500284
285/* pass open firmware flat tree */
Paul Gortmaker61a608c2007-12-20 12:58:51 -0500286#define CONFIG_OF_LIBFDT 1
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500287#define CONFIG_OF_BOARD_SETUP 1
Kim Phillipsfd47a742007-12-20 14:09:22 -0600288#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500289
290/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200291#define CONFIG_SYS_I2C
292#define CONFIG_SYS_I2C_FSL
293#define CONFIG_SYS_FSL_I2C_SPEED 400000
294#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
295#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
296#define CONFIG_SYS_FSL_I2C2_SPEED 400000
297#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
298#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
299#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
Paul Gortmaker04684f72009-10-02 18:54:20 -0400300/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500301
302/* TSEC */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger10c26172011-10-11 23:57:25 -0500304#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger10c26172011-10-11 23:57:25 -0500306#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500307
308/*
309 * General PCI
310 * Addresses are mapped 1-1.
311 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
313#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
314#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
315#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
316#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
317#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger10c26172011-10-11 23:57:25 -0500318#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
319#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
320#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500321
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200322#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
323#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
324#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
325#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
326#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
327#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger10c26172011-10-11 23:57:25 -0500328#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
329#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
330#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500331
332#if defined(CONFIG_PCI)
333
334#define PCI_64BIT
335#define PCI_ONE_PCI1
336#if defined(PCI_64BIT)
337#undef PCI_ALL_PCI1
338#undef PCI_TWO_PCI1
339#undef PCI_ONE_PCI1
340#endif
341
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500342#define CONFIG_PCI_PNP /* do pci plug-and-play */
343
344#undef CONFIG_EEPRO100
345#undef CONFIG_TULIP
346
347#if !defined(CONFIG_PCI_PNP)
348 #define PCI_ENET0_IOADDR 0xFIXME
349 #define PCI_ENET0_MEMADDR 0xFIXME
350 #define PCI_IDSEL_NUMBER 0xFIXME
351#endif
352
353#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200354#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500355
356#endif /* CONFIG_PCI */
357
358/*
359 * TSEC configuration
360 */
361#define CONFIG_TSEC_ENET /* TSEC ethernet support */
362
363#if defined(CONFIG_TSEC_ENET)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500364
Kim Phillips177e58f2007-05-16 16:52:19 -0500365#define CONFIG_TSEC1 1
366#define CONFIG_TSEC1_NAME "TSEC0"
367#define CONFIG_TSEC2 1
368#define CONFIG_TSEC2_NAME "TSEC1"
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500369#define CONFIG_PHY_BCM5421S 1
370#define TSEC1_PHY_ADDR 0x19
371#define TSEC2_PHY_ADDR 0x1a
372#define TSEC1_PHYIDX 0
373#define TSEC2_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500374#define TSEC1_FLAGS TSEC_GIGABIT
375#define TSEC2_FLAGS TSEC_GIGABIT
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500376
377/* Options are: TSEC[0-1] */
378#define CONFIG_ETHPRIME "TSEC0"
379
380#endif /* CONFIG_TSEC_ENET */
381
382/*
383 * Environment
384 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200385#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200386 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200387 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200388 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
389 #define CONFIG_ENV_SIZE 0x2000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500390
391/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200392#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
393#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500394
395#else
Joe Hershberger10c26172011-10-11 23:57:25 -0500396 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200397 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200398 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200399 #define CONFIG_ENV_SIZE 0x2000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500400#endif
401
402#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200403#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500404
Jon Loeliger1f166a22007-07-04 22:30:58 -0500405
406/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500407 * BOOTP options
408 */
409#define CONFIG_BOOTP_BOOTFILESIZE
410#define CONFIG_BOOTP_BOOTPATH
411#define CONFIG_BOOTP_GATEWAY
412#define CONFIG_BOOTP_HOSTNAME
413
414
415/*
Jon Loeliger1f166a22007-07-04 22:30:58 -0500416 * Command line configuration.
417 */
Jon Loeliger1f166a22007-07-04 22:30:58 -0500418#define CONFIG_CMD_I2C
419#define CONFIG_CMD_MII
420#define CONFIG_CMD_PING
421
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500422#if defined(CONFIG_PCI)
Paul Gortmaker61a608c2007-12-20 12:58:51 -0500423 #define CONFIG_CMD_PCI
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500424#endif
Jon Loeliger1f166a22007-07-04 22:30:58 -0500425
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500426#undef CONFIG_WATCHDOG /* watchdog disabled */
427
428/*
429 * Miscellaneous configurable options
430 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200431#define CONFIG_SYS_LONGHELP /* undef to save memory */
432#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500433
Jon Loeliger1f166a22007-07-04 22:30:58 -0500434#if defined(CONFIG_CMD_KGDB)
Joe Hershberger10c26172011-10-11 23:57:25 -0500435 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500436#else
Joe Hershberger10c26172011-10-11 23:57:25 -0500437 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500438#endif
439
Joe Hershberger10c26172011-10-11 23:57:25 -0500440 /* Print Buffer Size */
441#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
442#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
443 /* Boot Argument Buffer Size */
444#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500445
446/*
447 * For booting Linux, the board info and command line data
Ira W. Snyderc5a22d02010-09-10 15:42:32 -0700448 * have to be in the first 256 MB of memory, since this is
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500449 * the maximum mapped by the Linux kernel during initialization.
450 */
Joe Hershberger10c26172011-10-11 23:57:25 -0500451 /* Initial Memory map for Linux*/
452#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500453
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200454#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500455
456#if 1 /*528/264*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200457#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500458 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
459 HRCWL_DDR_TO_SCB_CLK_1X1 |\
460 HRCWL_CSB_TO_CLKIN |\
461 HRCWL_VCO_1X2 |\
462 HRCWL_CORE_TO_CSB_2X1)
463#elif 0 /*396/132*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200464#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500465 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
466 HRCWL_DDR_TO_SCB_CLK_1X1 |\
467 HRCWL_CSB_TO_CLKIN |\
468 HRCWL_VCO_1X4 |\
469 HRCWL_CORE_TO_CSB_3X1)
470#elif 0 /*264/132*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200471#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500472 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
473 HRCWL_DDR_TO_SCB_CLK_1X1 |\
474 HRCWL_CSB_TO_CLKIN |\
475 HRCWL_VCO_1X4 |\
476 HRCWL_CORE_TO_CSB_2X1)
477#elif 0 /*132/132*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200478#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500479 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
480 HRCWL_DDR_TO_SCB_CLK_1X1 |\
481 HRCWL_CSB_TO_CLKIN |\
482 HRCWL_VCO_1X4 |\
483 HRCWL_CORE_TO_CSB_1X1)
484#elif 0 /*264/264 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200485#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500486 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
487 HRCWL_DDR_TO_SCB_CLK_1X1 |\
488 HRCWL_CSB_TO_CLKIN |\
489 HRCWL_VCO_1X4 |\
490 HRCWL_CORE_TO_CSB_1X1)
491#endif
492
493#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200494#define CONFIG_SYS_HRCW_HIGH (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500495 HRCWH_PCI_HOST |\
496 HRCWH_64_BIT_PCI |\
497 HRCWH_PCI1_ARBITER_ENABLE |\
498 HRCWH_PCI2_ARBITER_DISABLE |\
499 HRCWH_CORE_ENABLE |\
500 HRCWH_FROM_0X00000100 |\
501 HRCWH_BOOTSEQ_DISABLE |\
502 HRCWH_SW_WATCHDOG_DISABLE |\
503 HRCWH_ROM_LOC_LOCAL_16BIT |\
504 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger10c26172011-10-11 23:57:25 -0500505 HRCWH_TSEC2M_IN_GMII)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500506#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200507#define CONFIG_SYS_HRCW_HIGH (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500508 HRCWH_PCI_HOST |\
509 HRCWH_32_BIT_PCI |\
510 HRCWH_PCI1_ARBITER_ENABLE |\
511 HRCWH_PCI2_ARBITER_ENABLE |\
512 HRCWH_CORE_ENABLE |\
513 HRCWH_FROM_0X00000100 |\
514 HRCWH_BOOTSEQ_DISABLE |\
515 HRCWH_SW_WATCHDOG_DISABLE |\
516 HRCWH_ROM_LOC_LOCAL_16BIT |\
517 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger10c26172011-10-11 23:57:25 -0500518 HRCWH_TSEC2M_IN_GMII)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500519#endif
520
521/* System IO Config */
Kim Phillipsf91cad62009-06-05 14:11:33 -0500522#define CONFIG_SYS_SICRH 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200523#define CONFIG_SYS_SICRL SICRL_LDP_A
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500524
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200525#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershberger10c26172011-10-11 23:57:25 -0500526#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
527 | HID0_ENABLE_INSTRUCTION_CACHE)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500528
Joe Hershberger10c26172011-10-11 23:57:25 -0500529/* #define CONFIG_SYS_HID0_FINAL (\
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500530 HID0_ENABLE_INSTRUCTION_CACHE |\
531 HID0_ENABLE_M_BIT |\
Joe Hershberger10c26172011-10-11 23:57:25 -0500532 HID0_ENABLE_ADDRESS_BROADCAST) */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500533
534
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200535#define CONFIG_SYS_HID2 HID2_HBE
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500536
Becky Bruce03ea1be2008-05-08 19:02:12 -0500537#define CONFIG_HIGH_BATS 1 /* High BATs supported */
538
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500539/* DDR @ 0x00000000 */
Joe Hershberger10c26172011-10-11 23:57:25 -0500540#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500541 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500542 | BATL_MEMCOHERENCE)
543#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
544 | BATU_BL_256M \
545 | BATU_VS \
546 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500547
548/* PCI @ 0x80000000 */
549#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000550#define CONFIG_PCI_INDIRECT_BRIDGE
Joe Hershberger10c26172011-10-11 23:57:25 -0500551#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500552 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500553 | BATL_MEMCOHERENCE)
554#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
555 | BATU_BL_256M \
556 | BATU_VS \
557 | BATU_VP)
558#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500559 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500560 | BATL_CACHEINHIBIT \
561 | BATL_GUARDEDSTORAGE)
562#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
563 | BATU_BL_256M \
564 | BATU_VS \
565 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500566#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200567#define CONFIG_SYS_IBAT1L (0)
568#define CONFIG_SYS_IBAT1U (0)
569#define CONFIG_SYS_IBAT2L (0)
570#define CONFIG_SYS_IBAT2U (0)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500571#endif
572
573#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger10c26172011-10-11 23:57:25 -0500574#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500575 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500576 | BATL_MEMCOHERENCE)
577#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
578 | BATU_BL_256M \
579 | BATU_VS \
580 | BATU_VP)
581#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500582 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500583 | BATL_CACHEINHIBIT \
584 | BATL_GUARDEDSTORAGE)
585#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
586 | BATU_BL_256M \
587 | BATU_VS \
588 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500589#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200590#define CONFIG_SYS_IBAT3L (0)
591#define CONFIG_SYS_IBAT3U (0)
592#define CONFIG_SYS_IBAT4L (0)
593#define CONFIG_SYS_IBAT4U (0)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500594#endif
595
596/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
Joe Hershberger10c26172011-10-11 23:57:25 -0500597#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500598 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500599 | BATL_CACHEINHIBIT \
600 | BATL_GUARDEDSTORAGE)
601#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
602 | BATU_BL_256M \
603 | BATU_VS \
604 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500605
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500606/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
607#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
Joe Hershbergerbfd89732011-10-11 23:57:28 -0500608 | BATL_PP_RW \
Joe Hershberger10c26172011-10-11 23:57:25 -0500609 | BATL_MEMCOHERENCE \
610 | BATL_GUARDEDSTORAGE)
Joe Hershbergerf05b9332011-10-11 23:57:30 -0500611#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
612 | BATU_BL_256M \
613 | BATU_VS \
614 | BATU_VP)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500615
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200616#define CONFIG_SYS_IBAT7L (0)
617#define CONFIG_SYS_IBAT7U (0)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500618
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200619#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
620#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
621#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
622#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
623#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
624#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
625#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
626#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
627#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
628#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
629#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
630#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
631#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
632#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
633#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
634#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500635
Jon Loeliger1f166a22007-07-04 22:30:58 -0500636#if defined(CONFIG_CMD_KGDB)
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500637#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500638#endif
639
640/*
641 * Environment Configuration
642 */
643#define CONFIG_ENV_OVERWRITE
644
645#if defined(CONFIG_TSEC_ENET)
Andy Fleming458c3892007-08-16 16:35:02 -0500646#define CONFIG_HAS_ETH0
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500647#define CONFIG_HAS_ETH1
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500648#endif
649
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500650#define CONFIG_HOSTNAME SBC8349
Joe Hershberger257ff782011-10-13 13:03:47 +0000651#define CONFIG_ROOTPATH "/tftpboot/rootfs"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000652#define CONFIG_BOOTFILE "uImage"
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500653
Joe Hershberger10c26172011-10-11 23:57:25 -0500654 /* default location for tftp and bootm */
655#define CONFIG_LOADADDR 800000
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500656
657#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Joe Hershberger10c26172011-10-11 23:57:25 -0500658#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500659
660#define CONFIG_BAUDRATE 115200
661
662#define CONFIG_EXTRA_ENV_SETTINGS \
663 "netdev=eth0\0" \
Detlev Zundel027fa492008-04-18 14:50:01 +0200664 "hostname=sbc8349\0" \
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500665 "nfsargs=setenv bootargs root=/dev/nfs rw " \
666 "nfsroot=${serverip}:${rootpath}\0" \
667 "ramargs=setenv bootargs root=/dev/ram rw\0" \
668 "addip=setenv bootargs ${bootargs} " \
669 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
670 ":${hostname}:${netdev}:off panic=1\0" \
671 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
672 "flash_nfs=run nfsargs addip addtty;" \
673 "bootm ${kernel_addr}\0" \
674 "flash_self=run ramargs addip addtty;" \
675 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
676 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
677 "bootm\0" \
678 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
Paul Gortmaker80b4bb72009-07-23 17:10:55 -0400679 "update=protect off ff800000 ff83ffff; " \
Joe Hershberger10c26172011-10-11 23:57:25 -0500680 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
Detlev Zundel406e5782008-03-06 16:45:53 +0100681 "upd=run load update\0" \
Kim Phillipsfd3a3fc2009-08-21 16:34:38 -0500682 "fdtaddr=780000\0" \
Detlev Zundel027fa492008-04-18 14:50:01 +0200683 "fdtfile=sbc8349.dtb\0" \
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500684 ""
685
Joe Hershberger10c26172011-10-11 23:57:25 -0500686#define CONFIG_NFSBOOTCOMMAND \
687 "setenv bootargs root=/dev/nfs rw " \
688 "nfsroot=$serverip:$rootpath " \
689 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
690 "$netdev:off " \
691 "console=$consoledev,$baudrate $othbootargs;" \
692 "tftp $loadaddr $bootfile;" \
693 "tftp $fdtaddr $fdtfile;" \
694 "bootm $loadaddr - $fdtaddr"
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500695
696#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger10c26172011-10-11 23:57:25 -0500697 "setenv bootargs root=/dev/ram rw " \
698 "console=$consoledev,$baudrate $othbootargs;" \
699 "tftp $ramdiskaddr $ramdiskfile;" \
700 "tftp $loadaddr $bootfile;" \
701 "tftp $fdtaddr $fdtfile;" \
702 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500703
704#define CONFIG_BOOTCOMMAND "run flash_self"
705
706#endif /* __CONFIG_H */