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git01.mediatek.com / filogic / uboot / 77c3cf1939dab2dcff0be20104c5d546c5541638 / . / dts / upstream / src / arm64 / freescale / imx8mp-venice-gw74xx.dts
blob: cae586cd45bdd59aa479e70bb290fc50b0392a3c [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12
13#include "imx8mp.dtsi"
14
15/ {
16 model = "Gateworks Venice GW74xx i.MX8MP board";
17 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
18
19 aliases {
20 ethernet0 = &eqos;
21 ethernet1 = &fec;
22 ethernet2 = &lan1;
23 ethernet3 = &lan2;
24 ethernet4 = &lan3;
25 ethernet5 = &lan4;
26 ethernet6 = &lan5;
27 };
28
29 chosen {
30 stdout-path = &uart2;
31 };
32
33 memory@40000000 {
34 device_type = "memory";
35 reg = <0x0 0x40000000 0 0x80000000>;
36 };
37
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]38 connector {
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_usbcon1>;
41 compatible = "gpio-usb-b-connector", "usb-b-connector";
42 type = "micro";
43 label = "Type-C";
44 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
45
46 port {
47 usb_dr_connector: endpoint {
48 remote-endpoint = <&usb3_dwc>;
49 };
50 };
51 };
52
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]53 gpio-keys {
54 compatible = "gpio-keys";
55
56 key-0 {
57 label = "user_pb";
58 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
59 linux,code = <BTN_0>;
60 };
61
62 key-1 {
63 label = "user_pb1x";
64 linux,code = <BTN_1>;
65 interrupt-parent = <&gsc>;
66 interrupts = <0>;
67 };
68
69 key-2 {
70 label = "key_erased";
71 linux,code = <BTN_2>;
72 interrupt-parent = <&gsc>;
73 interrupts = <1>;
74 };
75
76 key-3 {
77 label = "eeprom_wp";
78 linux,code = <BTN_3>;
79 interrupt-parent = <&gsc>;
80 interrupts = <2>;
81 };
82
83 key-4 {
84 label = "tamper";
85 linux,code = <BTN_4>;
86 interrupt-parent = <&gsc>;
87 interrupts = <5>;
88 };
89
90 key-5 {
91 label = "switch_hold";
92 linux,code = <BTN_5>;
93 interrupt-parent = <&gsc>;
94 interrupts = <7>;
95 };
96 };
97
98 led-controller {
99 compatible = "gpio-leds";
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_gpio_leds>;
102
103 led-0 {
104 function = LED_FUNCTION_HEARTBEAT;
105 color = <LED_COLOR_ID_GREEN>;
106 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
107 default-state = "on";
108 linux,default-trigger = "heartbeat";
109 };
110
111 led-1 {
112 function = LED_FUNCTION_STATUS;
113 color = <LED_COLOR_ID_RED>;
114 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
115 default-state = "off";
116 };
117 };
118
119 pcie0_refclk: pcie0-refclk {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <100000000>;
123 };
124
125 pps {
126 compatible = "pps-gpio";
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_pps>;
129 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
130 };
131
132 reg_usb2_vbus: regulator-usb2 {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_reg_usb2>;
135 compatible = "regulator-fixed";
136 regulator-name = "usb_usb2_vbus";
137 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
138 enable-active-high;
139 regulator-min-microvolt = <5000000>;
140 regulator-max-microvolt = <5000000>;
141 };
142
143 reg_can1_stby: regulator-can1-stby {
144 compatible = "regulator-fixed";
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_reg_can1>;
147 regulator-name = "can1_stby";
148 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
149 regulator-min-microvolt = <3300000>;
150 regulator-max-microvolt = <3300000>;
151 };
152
153 reg_can2_stby: regulator-can2-stby {
154 compatible = "regulator-fixed";
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_reg_can2>;
157 regulator-name = "can2_stby";
158 gpio = <&gpio5 5 GPIO_ACTIVE_LOW>;
159 regulator-min-microvolt = <3300000>;
160 regulator-max-microvolt = <3300000>;
161 };
162
163 reg_wifi_en: regulator-wifi-en {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_reg_wifi>;
166 compatible = "regulator-fixed";
167 regulator-name = "wl";
168 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
169 startup-delay-us = <70000>;
170 enable-active-high;
171 regulator-min-microvolt = <3300000>;
172 regulator-max-microvolt = <3300000>;
173 };
174};
175
176&A53_0 {
177 cpu-supply = <&reg_arm>;
178};
179
180&A53_1 {
181 cpu-supply = <&reg_arm>;
182};
183
184&A53_2 {
185 cpu-supply = <&reg_arm>;
186};
187
188&A53_3 {
189 cpu-supply = <&reg_arm>;
190};
191
192&ecspi1 {
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_spi1>;
195 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
196 status = "okay";
197
198 tpm@0 {
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]199 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]200 reg = <0x0>;
201 spi-max-frequency = <36000000>;
202 };
203};
204
205/* off-board header */
206&ecspi2 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi2>;
209 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
210 status = "okay";
211};
212
213&eqos {
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_eqos>;
216 phy-mode = "rgmii-id";
217 phy-handle = <&ethphy0>;
218 status = "okay";
219
220 mdio {
221 compatible = "snps,dwmac-mdio";
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 ethphy0: ethernet-phy@0 {
226 compatible = "ethernet-phy-ieee802.3-c22";
227 reg = <0x0>;
228 };
229 };
230};
231
232&fec {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_fec>;
235 phy-mode = "rgmii-id";
236 local-mac-address = [00 00 00 00 00 00];
237 status = "okay";
238
239 fixed-link {
240 speed = <1000>;
241 full-duplex;
242 };
243};
244
245&flexcan1 {
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_flexcan1>;
248 xceiver-supply = <&reg_can1_stby>;
249 status = "okay";
250};
251
252&flexcan2 {
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_flexcan2>;
255 xceiver-supply = <&reg_can2_stby>;
256 status = "okay";
257};
258
259&gpio1 {
260 gpio-line-names =
261 "", "", "", "", "", "", "", "",
262 "", "dio0", "", "dio1", "", "", "", "",
263 "", "", "", "", "", "", "", "",
264 "", "", "", "", "", "", "", "";
265};
266
267&gpio2 {
268 gpio-line-names =
269 "", "", "", "", "", "", "m2_pin20", "",
270 "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "",
271 "", "", "pcie2_wdis#", "", "", "", "", "",
272 "", "", "", "", "", "", "", "";
273};
274
275&gpio3 {
276 gpio-line-names =
277 "", "", "", "", "", "", "m2_rst", "",
278 "", "", "", "", "", "", "", "",
279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "";
281};
282
283&gpio4 {
284 gpio-line-names =
285 "", "", "m2_off#", "", "", "", "", "",
286 "", "", "", "", "", "", "", "",
287 "", "", "m2_wdis#", "", "", "", "", "",
288 "", "", "", "", "", "", "", "rs485_en";
289};
290
291&gpio5 {
292 gpio-line-names =
293 "rs485_hd", "rs485_term", "", "", "", "", "", "",
294 "", "", "", "", "", "", "", "",
295 "", "", "", "", "", "", "", "",
296 "", "", "", "", "", "", "", "";
297};
298
299&i2c1 {
300 clock-frequency = <100000>;
301 pinctrl-names = "default", "gpio";
302 pinctrl-0 = <&pinctrl_i2c1>;
303 pinctrl-1 = <&pinctrl_i2c1_gpio>;
304 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
305 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
306 status = "okay";
307
308 gsc: gsc@20 {
309 compatible = "gw,gsc";
310 reg = <0x20>;
311 pinctrl-0 = <&pinctrl_gsc>;
312 interrupt-parent = <&gpio4>;
313 interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
314 interrupt-controller;
315 #interrupt-cells = <1>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318
319 adc {
320 compatible = "gw,gsc-adc";
321 #address-cells = <1>;
322 #size-cells = <0>;
323
324 channel@6 {
325 gw,mode = <0>;
326 reg = <0x06>;
327 label = "temp";
328 };
329
330 channel@8 {
331 gw,mode = <3>;
332 reg = <0x08>;
333 label = "vdd_bat";
334 };
335
336 channel@16 {
337 gw,mode = <4>;
338 reg = <0x16>;
339 label = "fan_tach";
340 };
341
342 channel@82 {
343 gw,mode = <2>;
344 reg = <0x82>;
345 label = "vdd_adc1";
346 gw,voltage-divider-ohms = <10000 10000>;
347 };
348
349 channel@84 {
350 gw,mode = <2>;
351 reg = <0x84>;
352 label = "vdd_adc2";
353 gw,voltage-divider-ohms = <10000 10000>;
354 };
355
356 channel@86 {
357 gw,mode = <2>;
358 reg = <0x86>;
359 label = "vdd_vin";
360 gw,voltage-divider-ohms = <22100 1000>;
361 };
362
363 channel@88 {
364 gw,mode = <2>;
365 reg = <0x88>;
366 label = "vdd_3p3";
367 gw,voltage-divider-ohms = <10000 10000>;
368 };
369
370 channel@8c {
371 gw,mode = <2>;
372 reg = <0x8c>;
373 label = "vdd_2p5";
374 gw,voltage-divider-ohms = <10000 10000>;
375 };
376
377 channel@90 {
378 gw,mode = <2>;
379 reg = <0x90>;
380 label = "vdd_soc";
381 };
382
383 channel@92 {
384 gw,mode = <2>;
385 reg = <0x92>;
386 label = "vdd_arm";
387 };
388
389 channel@98 {
390 gw,mode = <2>;
391 reg = <0x98>;
392 label = "vdd_1p8";
393 };
394
395 channel@9a {
396 gw,mode = <2>;
397 reg = <0x9a>;
398 label = "vdd_1p2";
399 };
400
401 channel@9c {
402 gw,mode = <2>;
403 reg = <0x9c>;
404 label = "vdd_dram";
405 };
406
407 channel@a2 {
408 gw,mode = <2>;
409 reg = <0xa2>;
410 label = "vdd_gsc";
411 gw,voltage-divider-ohms = <10000 10000>;
412 };
413 };
414
415 fan-controller@a {
416 compatible = "gw,gsc-fan";
417 reg = <0x0a>;
418 };
419 };
420
421 gpio: gpio@23 {
422 compatible = "nxp,pca9555";
423 reg = <0x23>;
424 gpio-controller;
425 #gpio-cells = <2>;
426 interrupt-parent = <&gsc>;
427 interrupts = <4>;
428 };
429
430 eeprom@50 {
431 compatible = "atmel,24c02";
432 reg = <0x50>;
433 pagesize = <16>;
434 };
435
436 eeprom@51 {
437 compatible = "atmel,24c02";
438 reg = <0x51>;
439 pagesize = <16>;
440 };
441
442 eeprom@52 {
443 compatible = "atmel,24c02";
444 reg = <0x52>;
445 pagesize = <16>;
446 };
447
448 eeprom@53 {
449 compatible = "atmel,24c02";
450 reg = <0x53>;
451 pagesize = <16>;
452 };
453
454 rtc@68 {
455 compatible = "dallas,ds1672";
456 reg = <0x68>;
457 };
458};
459
460&i2c2 {
461 clock-frequency = <400000>;
462 pinctrl-names = "default", "gpio";
463 pinctrl-0 = <&pinctrl_i2c2>;
464 pinctrl-1 = <&pinctrl_i2c2_gpio>;
465 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
466 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
467 status = "okay";
468
469 accelerometer@19 {
470 compatible = "st,lis2de12";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_accel>;
473 reg = <0x19>;
474 st,drdy-int-pin = <1>;
475 interrupt-parent = <&gpio1>;
476 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
477 };
478
479 switch: switch@5f {
480 compatible = "microchip,ksz9897";
481 reg = <0x5f>;
482 pinctrl-0 = <&pinctrl_ksz>;
483 interrupt-parent = <&gpio4>;
484 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
485
486 ports {
487 #address-cells = <1>;
488 #size-cells = <0>;
489
490 lan1: port@0 {
491 reg = <0>;
492 label = "lan1";
493 phy-mode = "internal";
494 local-mac-address = [00 00 00 00 00 00];
495 };
496
497 lan2: port@1 {
498 reg = <1>;
499 label = "lan2";
500 phy-mode = "internal";
501 local-mac-address = [00 00 00 00 00 00];
502 };
503
504 lan3: port@2 {
505 reg = <2>;
506 label = "lan3";
507 phy-mode = "internal";
508 local-mac-address = [00 00 00 00 00 00];
509 };
510
511 lan4: port@3 {
512 reg = <3>;
513 label = "lan4";
514 phy-mode = "internal";
515 local-mac-address = [00 00 00 00 00 00];
516 };
517
518 lan5: port@4 {
519 reg = <4>;
520 label = "lan5";
521 phy-mode = "internal";
522 local-mac-address = [00 00 00 00 00 00];
523 };
524
525 port@5 {
526 reg = <5>;
527 ethernet = <&fec>;
528 phy-mode = "rgmii-id";
529
530 fixed-link {
531 speed = <1000>;
532 full-duplex;
533 };
534 };
535 };
536 };
537};
538
539&i2c3 {
540 clock-frequency = <400000>;
541 pinctrl-names = "default", "gpio";
542 pinctrl-0 = <&pinctrl_i2c3>;
543 pinctrl-1 = <&pinctrl_i2c3_gpio>;
544 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
545 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
546 status = "okay";
547
548 pmic@25 {
549 compatible = "nxp,pca9450c";
550 reg = <0x25>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_pmic>;
553 interrupt-parent = <&gpio3>;
554 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
555
556 regulators {
557 BUCK1 {
558 regulator-name = "BUCK1";
559 regulator-min-microvolt = <720000>;
560 regulator-max-microvolt = <1000000>;
561 regulator-boot-on;
562 regulator-always-on;
563 regulator-ramp-delay = <3125>;
564 };
565
566 reg_arm: BUCK2 {
567 regulator-name = "BUCK2";
568 regulator-min-microvolt = <720000>;
569 regulator-max-microvolt = <1025000>;
570 regulator-boot-on;
571 regulator-always-on;
572 regulator-ramp-delay = <3125>;
573 nxp,dvs-run-voltage = <950000>;
574 nxp,dvs-standby-voltage = <850000>;
575 };
576
577 BUCK4 {
578 regulator-name = "BUCK4";
579 regulator-min-microvolt = <3000000>;
580 regulator-max-microvolt = <3600000>;
581 regulator-boot-on;
582 regulator-always-on;
583 };
584
585 BUCK5 {
586 regulator-name = "BUCK5";
587 regulator-min-microvolt = <1650000>;
588 regulator-max-microvolt = <1950000>;
589 regulator-boot-on;
590 regulator-always-on;
591 };
592
593 BUCK6 {
594 regulator-name = "BUCK6";
595 regulator-min-microvolt = <1045000>;
596 regulator-max-microvolt = <1155000>;
597 regulator-boot-on;
598 regulator-always-on;
599 };
600
601 LDO1 {
602 regulator-name = "LDO1";
603 regulator-min-microvolt = <1650000>;
604 regulator-max-microvolt = <1950000>;
605 regulator-boot-on;
606 regulator-always-on;
607 };
608
609 LDO3 {
610 regulator-name = "LDO3";
611 regulator-min-microvolt = <1710000>;
612 regulator-max-microvolt = <1890000>;
613 regulator-boot-on;
614 regulator-always-on;
615 };
616
617 LDO5 {
618 regulator-name = "LDO5";
619 regulator-min-microvolt = <1800000>;
620 regulator-max-microvolt = <3300000>;
621 regulator-boot-on;
622 regulator-always-on;
623 };
624 };
625 };
626};
627
628/* off-board header */
629&i2c4 {
630 clock-frequency = <400000>;
631 pinctrl-names = "default", "gpio";
632 pinctrl-0 = <&pinctrl_i2c4>;
633 pinctrl-1 = <&pinctrl_i2c4_gpio>;
634 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
635 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
636 status = "okay";
637};
638
639&pcie_phy {
640 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
641 fsl,clkreq-unsupported;
642 clocks = <&pcie0_refclk>;
643 clock-names = "ref";
644 status = "okay";
645};
646
647&pcie {
648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_pcie0>;
650 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
651 status = "okay";
652};
653
654/* GPS / off-board header */
655&uart1 {
656 pinctrl-names = "default";
657 pinctrl-0 = <&pinctrl_uart1>;
658 status = "okay";
659};
660
661/* RS232 console */
662&uart2 {
663 pinctrl-names = "default";
664 pinctrl-0 = <&pinctrl_uart2>;
665 status = "okay";
666};
667
668/* bluetooth HCI */
669&uart3 {
670 pinctrl-names = "default";
671 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
672 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
673 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
674 status = "okay";
675
676 bluetooth {
677 compatible = "brcm,bcm4330-bt";
678 shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
679 };
680};
681
682&uart4 {
683 pinctrl-names = "default";
684 pinctrl-0 = <&pinctrl_uart4>;
685 status = "okay";
686};
687
688/* USB1 - Type C front panel */
689&usb3_0 {
690 pinctrl-names = "default";
691 pinctrl-0 = <&pinctrl_usb1>;
692 fsl,over-current-active-low;
693 status = "okay";
694};
695
696&usb3_phy0 {
697 status = "okay";
698};
699
700&usb_dwc3_0 {
701 /* dual role is implemented but not a full featured OTG */
702 adp-disable;
703 hnp-disable;
704 srp-disable;
705 dr_mode = "otg";
706 usb-role-switch;
707 role-switch-default-mode = "peripheral";
708 status = "okay";
709
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]710 port {
711 usb3_dwc: endpoint {
712 remote-endpoint = <&usb_dr_connector>;
713 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]714 };
715};
716
717/* USB2 - USB3.0 Hub */
718&usb3_phy1 {
719 vbus-supply = <&reg_usb2_vbus>;
720 status = "okay";
721};
722
723&usb3_1 {
724 fsl,permanently-attached;
725 fsl,disable-port-power-control;
726 status = "okay";
727};
728
729&usb_dwc3_1 {
730 dr_mode = "host";
731 status = "okay";
732};
733
734/* SDIO WiFi */
735&usdhc1 {
736 pinctrl-names = "default", "state_100mhz", "state_200mhz";
737 pinctrl-0 = <&pinctrl_usdhc1>;
738 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
739 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
740 bus-width = <4>;
741 non-removable;
742 vmmc-supply = <&reg_wifi_en>;
743 #address-cells = <1>;
744 #size-cells = <0>;
745 status = "okay";
746
747 wifi@0 {
748 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
749 reg = <0>;
750 };
751};
752
753/* eMMC */
754&usdhc3 {
755 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
756 assigned-clock-rates = <400000000>;
757 pinctrl-names = "default", "state_100mhz", "state_200mhz";
758 pinctrl-0 = <&pinctrl_usdhc3>;
759 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
760 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
761 bus-width = <8>;
762 non-removable;
763 status = "okay";
764};
765
766&wdog1 {
767 pinctrl-names = "default";
768 pinctrl-0 = <&pinctrl_wdog>;
769 fsl,ext-reset-output;
770 status = "okay";
771};
772
773&iomuxc {
774 pinctrl-names = "default";
775 pinctrl-0 = <&pinctrl_hog>;
776
777 pinctrl_hog: hoggrp {
778 fsl,pins = <
779 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
780 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
781 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */
782 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
783 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */
784 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */
785 MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */
786 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
787 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
788 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
789 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
790 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
791 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
792 >;
793 };
794
795 pinctrl_accel: accelgrp {
796 fsl,pins = <
797 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
798 >;
799 };
800
801 pinctrl_eqos: eqosgrp {
802 fsl,pins = <
803 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
804 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
805 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
806 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
807 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
808 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
809 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
810 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
811 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
812 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
813 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
814 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
815 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
816 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
817 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
818 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
819 >;
820 };
821
822 pinctrl_fec: fecgrp {
823 fsl,pins = <
824 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
825 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
826 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
827 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
828 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
829 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
830 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
831 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
832 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
833 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
834 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
835 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
836 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
837 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
838 >;
839 };
840
841 pinctrl_flexcan1: flexcan1grp {
842 fsl,pins = <
843 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
844 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
845 >;
846 };
847
848 pinctrl_flexcan2: flexcan2grp {
849 fsl,pins = <
850 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
851 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
852 >;
853 };
854
855 pinctrl_gsc: gscgrp {
856 fsl,pins = <
857 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
858 >;
859 };
860
861 pinctrl_i2c1: i2c1grp {
862 fsl,pins = <
863 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
864 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
865 >;
866 };
867
868 pinctrl_i2c1_gpio: i2c1gpiogrp {
869 fsl,pins = <
870 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
871 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
872 >;
873 };
874
875 pinctrl_i2c2: i2c2grp {
876 fsl,pins = <
877 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
878 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
879 >;
880 };
881
882 pinctrl_i2c2_gpio: i2c2gpiogrp {
883 fsl,pins = <
884 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
885 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
886 >;
887 };
888
889 pinctrl_i2c3: i2c3grp {
890 fsl,pins = <
891 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
892 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
893 >;
894 };
895
896 pinctrl_i2c3_gpio: i2c3gpiogrp {
897 fsl,pins = <
898 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
899 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
900 >;
901 };
902
903 pinctrl_i2c4: i2c4grp {
904 fsl,pins = <
905 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
906 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
907 >;
908 };
909
910 pinctrl_i2c4_gpio: i2c4gpiogrp {
911 fsl,pins = <
912 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
913 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
914 >;
915 };
916
917 pinctrl_ksz: kszgrp {
918 fsl,pins = <
919 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
920 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
921 >;
922 };
923
924 pinctrl_gpio_leds: ledgrp {
925 fsl,pins = <
926 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
927 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
928 >;
929 };
930
931 pinctrl_pcie0: pciegrp {
932 fsl,pins = <
933 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106
934 >;
935 };
936
937 pinctrl_pmic: pmicgrp {
938 fsl,pins = <
939 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
940 >;
941 };
942
943 pinctrl_pps: ppsgrp {
944 fsl,pins = <
945 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
946 >;
947 };
948
949 pinctrl_reg_can1: regcan1grp {
950 fsl,pins = <
951 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
952 >;
953 };
954
955 pinctrl_reg_can2: regcan2grp {
956 fsl,pins = <
957 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154
958 >;
959 };
960
961 pinctrl_reg_usb2: regusb2grp {
962 fsl,pins = <
963 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
964 >;
965 };
966
967 pinctrl_reg_wifi: regwifigrp {
968 fsl,pins = <
969 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
970 >;
971 };
972
973 pinctrl_spi1: spi1grp {
974 fsl,pins = <
975 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82
976 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82
977 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82
978 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
979 >;
980 };
981
982 pinctrl_spi2: spi2grp {
983 fsl,pins = <
984 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
985 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
986 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
987 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
988 >;
989 };
990
991 pinctrl_uart1: uart1grp {
992 fsl,pins = <
993 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
994 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
995 >;
996 };
997
998 pinctrl_uart2: uart2grp {
999 fsl,pins = <
1000 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
1001 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
1002 >;
1003 };
1004
1005 pinctrl_uart3: uart3grp {
1006 fsl,pins = <
1007 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
1008 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
1009 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
1010 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
1011 >;
1012 };
1013
1014 pinctrl_uart3_gpio: uart3gpiogrp {
1015 fsl,pins = <
1016 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
1017 >;
1018 };
1019
1020 pinctrl_uart4: uart4grp {
1021 fsl,pins = <
1022 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
1023 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
1024 >;
1025 };
1026
1027 pinctrl_usb1: usb1grp {
1028 fsl,pins = <
1029 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
1030 >;
1031 };
1032
1033 pinctrl_usbcon1: usb1congrp {
1034 fsl,pins = <
1035 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
1036 >;
1037 };
1038
1039 pinctrl_usdhc1: usdhc1grp {
1040 fsl,pins = <
1041 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
1042 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
1043 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
1044 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
1045 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
1046 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
1047 >;
1048 };
1049
1050 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1051 fsl,pins = <
1052 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
1053 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
1054 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
1055 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
1056 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
1057 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
1058 >;
1059 };
1060
1061 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1062 fsl,pins = <
1063 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
1064 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
1065 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
1066 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
1067 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
1068 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
1069 >;
1070 };
1071
1072 pinctrl_usdhc3: usdhc3grp {
1073 fsl,pins = <
1074 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
1075 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
1076 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
1077 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
1078 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
1079 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
1080 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
1081 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
1082 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
1083 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
1084 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
1085 >;
1086 };
1087
1088 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1089 fsl,pins = <
1090 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1091 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1092 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1093 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1094 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1095 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1096 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1097 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1098 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1099 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1100 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1101 >;
1102 };
1103
1104 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1105 fsl,pins = <
1106 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1107 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1108 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1109 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1110 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1111 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1112 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1113 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1114 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1115 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1116 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1117 >;
1118 };
1119
1120 pinctrl_wdog: wdoggrp {
1121 fsl,pins = <
1122 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
1123 >;
1124 };
1125};