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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm64 / freescale / imx8mp-venice-gw74xx.dts
blob: 2ab9f4cc12cc9d020f83d8793b8bf5e079bebc79 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12
13#include "imx8mp.dtsi"
14
15/ {
16 model = "Gateworks Venice GW74xx i.MX8MP board";
17 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
18
19 aliases {
20 ethernet0 = &eqos;
21 ethernet1 = &fec;
22 ethernet2 = &lan1;
23 ethernet3 = &lan2;
24 ethernet4 = &lan3;
25 ethernet5 = &lan4;
26 ethernet6 = &lan5;
27 };
28
29 chosen {
30 stdout-path = &uart2;
31 };
32
33 memory@40000000 {
34 device_type = "memory";
35 reg = <0x0 0x40000000 0 0x80000000>;
36 };
37
38 gpio-keys {
39 compatible = "gpio-keys";
40
41 key-0 {
42 label = "user_pb";
43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
44 linux,code = <BTN_0>;
45 };
46
47 key-1 {
48 label = "user_pb1x";
49 linux,code = <BTN_1>;
50 interrupt-parent = <&gsc>;
51 interrupts = <0>;
52 };
53
54 key-2 {
55 label = "key_erased";
56 linux,code = <BTN_2>;
57 interrupt-parent = <&gsc>;
58 interrupts = <1>;
59 };
60
61 key-3 {
62 label = "eeprom_wp";
63 linux,code = <BTN_3>;
64 interrupt-parent = <&gsc>;
65 interrupts = <2>;
66 };
67
68 key-4 {
69 label = "tamper";
70 linux,code = <BTN_4>;
71 interrupt-parent = <&gsc>;
72 interrupts = <5>;
73 };
74
75 key-5 {
76 label = "switch_hold";
77 linux,code = <BTN_5>;
78 interrupt-parent = <&gsc>;
79 interrupts = <7>;
80 };
81 };
82
83 led-controller {
84 compatible = "gpio-leds";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_gpio_leds>;
87
88 led-0 {
89 function = LED_FUNCTION_HEARTBEAT;
90 color = <LED_COLOR_ID_GREEN>;
91 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
92 default-state = "on";
93 linux,default-trigger = "heartbeat";
94 };
95
96 led-1 {
97 function = LED_FUNCTION_STATUS;
98 color = <LED_COLOR_ID_RED>;
99 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
100 default-state = "off";
101 };
102 };
103
104 pcie0_refclk: pcie0-refclk {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <100000000>;
108 };
109
110 pps {
111 compatible = "pps-gpio";
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_pps>;
114 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
115 };
116
117 reg_usb2_vbus: regulator-usb2 {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_reg_usb2>;
120 compatible = "regulator-fixed";
121 regulator-name = "usb_usb2_vbus";
122 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
123 enable-active-high;
124 regulator-min-microvolt = <5000000>;
125 regulator-max-microvolt = <5000000>;
126 };
127
128 reg_can1_stby: regulator-can1-stby {
129 compatible = "regulator-fixed";
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_reg_can1>;
132 regulator-name = "can1_stby";
133 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
134 regulator-min-microvolt = <3300000>;
135 regulator-max-microvolt = <3300000>;
136 };
137
138 reg_can2_stby: regulator-can2-stby {
139 compatible = "regulator-fixed";
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_reg_can2>;
142 regulator-name = "can2_stby";
143 gpio = <&gpio5 5 GPIO_ACTIVE_LOW>;
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
146 };
147
148 reg_wifi_en: regulator-wifi-en {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_reg_wifi>;
151 compatible = "regulator-fixed";
152 regulator-name = "wl";
153 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
154 startup-delay-us = <70000>;
155 enable-active-high;
156 regulator-min-microvolt = <3300000>;
157 regulator-max-microvolt = <3300000>;
158 };
159};
160
161&A53_0 {
162 cpu-supply = <&reg_arm>;
163};
164
165&A53_1 {
166 cpu-supply = <&reg_arm>;
167};
168
169&A53_2 {
170 cpu-supply = <&reg_arm>;
171};
172
173&A53_3 {
174 cpu-supply = <&reg_arm>;
175};
176
177&ecspi1 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_spi1>;
180 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
181 status = "okay";
182
183 tpm@0 {
184 compatible = "tcg,tpm_tis-spi";
185 #address-cells = <0x1>;
186 #size-cells = <0x1>;
187 reg = <0x0>;
188 spi-max-frequency = <36000000>;
189 };
190};
191
192/* off-board header */
193&ecspi2 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_spi2>;
196 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
197 status = "okay";
198};
199
200&eqos {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_eqos>;
203 phy-mode = "rgmii-id";
204 phy-handle = <&ethphy0>;
205 status = "okay";
206
207 mdio {
208 compatible = "snps,dwmac-mdio";
209 #address-cells = <1>;
210 #size-cells = <0>;
211
212 ethphy0: ethernet-phy@0 {
213 compatible = "ethernet-phy-ieee802.3-c22";
214 reg = <0x0>;
215 };
216 };
217};
218
219&fec {
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_fec>;
222 phy-mode = "rgmii-id";
223 local-mac-address = [00 00 00 00 00 00];
224 status = "okay";
225
226 fixed-link {
227 speed = <1000>;
228 full-duplex;
229 };
230};
231
232&flexcan1 {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_flexcan1>;
235 xceiver-supply = <&reg_can1_stby>;
236 status = "okay";
237};
238
239&flexcan2 {
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_flexcan2>;
242 xceiver-supply = <&reg_can2_stby>;
243 status = "okay";
244};
245
246&gpio1 {
247 gpio-line-names =
248 "", "", "", "", "", "", "", "",
249 "", "dio0", "", "dio1", "", "", "", "",
250 "", "", "", "", "", "", "", "",
251 "", "", "", "", "", "", "", "";
252};
253
254&gpio2 {
255 gpio-line-names =
256 "", "", "", "", "", "", "m2_pin20", "",
257 "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "",
258 "", "", "pcie2_wdis#", "", "", "", "", "",
259 "", "", "", "", "", "", "", "";
260};
261
262&gpio3 {
263 gpio-line-names =
264 "", "", "", "", "", "", "m2_rst", "",
265 "", "", "", "", "", "", "", "",
266 "", "", "", "", "", "", "", "",
267 "", "", "", "", "", "", "", "";
268};
269
270&gpio4 {
271 gpio-line-names =
272 "", "", "m2_off#", "", "", "", "", "",
273 "", "", "", "", "", "", "", "",
274 "", "", "m2_wdis#", "", "", "", "", "",
275 "", "", "", "", "", "", "", "rs485_en";
276};
277
278&gpio5 {
279 gpio-line-names =
280 "rs485_hd", "rs485_term", "", "", "", "", "", "",
281 "", "", "", "", "", "", "", "",
282 "", "", "", "", "", "", "", "",
283 "", "", "", "", "", "", "", "";
284};
285
286&i2c1 {
287 clock-frequency = <100000>;
288 pinctrl-names = "default", "gpio";
289 pinctrl-0 = <&pinctrl_i2c1>;
290 pinctrl-1 = <&pinctrl_i2c1_gpio>;
291 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
292 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
293 status = "okay";
294
295 gsc: gsc@20 {
296 compatible = "gw,gsc";
297 reg = <0x20>;
298 pinctrl-0 = <&pinctrl_gsc>;
299 interrupt-parent = <&gpio4>;
300 interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
301 interrupt-controller;
302 #interrupt-cells = <1>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305
306 adc {
307 compatible = "gw,gsc-adc";
308 #address-cells = <1>;
309 #size-cells = <0>;
310
311 channel@6 {
312 gw,mode = <0>;
313 reg = <0x06>;
314 label = "temp";
315 };
316
317 channel@8 {
318 gw,mode = <3>;
319 reg = <0x08>;
320 label = "vdd_bat";
321 };
322
323 channel@16 {
324 gw,mode = <4>;
325 reg = <0x16>;
326 label = "fan_tach";
327 };
328
329 channel@82 {
330 gw,mode = <2>;
331 reg = <0x82>;
332 label = "vdd_adc1";
333 gw,voltage-divider-ohms = <10000 10000>;
334 };
335
336 channel@84 {
337 gw,mode = <2>;
338 reg = <0x84>;
339 label = "vdd_adc2";
340 gw,voltage-divider-ohms = <10000 10000>;
341 };
342
343 channel@86 {
344 gw,mode = <2>;
345 reg = <0x86>;
346 label = "vdd_vin";
347 gw,voltage-divider-ohms = <22100 1000>;
348 };
349
350 channel@88 {
351 gw,mode = <2>;
352 reg = <0x88>;
353 label = "vdd_3p3";
354 gw,voltage-divider-ohms = <10000 10000>;
355 };
356
357 channel@8c {
358 gw,mode = <2>;
359 reg = <0x8c>;
360 label = "vdd_2p5";
361 gw,voltage-divider-ohms = <10000 10000>;
362 };
363
364 channel@90 {
365 gw,mode = <2>;
366 reg = <0x90>;
367 label = "vdd_soc";
368 };
369
370 channel@92 {
371 gw,mode = <2>;
372 reg = <0x92>;
373 label = "vdd_arm";
374 };
375
376 channel@98 {
377 gw,mode = <2>;
378 reg = <0x98>;
379 label = "vdd_1p8";
380 };
381
382 channel@9a {
383 gw,mode = <2>;
384 reg = <0x9a>;
385 label = "vdd_1p2";
386 };
387
388 channel@9c {
389 gw,mode = <2>;
390 reg = <0x9c>;
391 label = "vdd_dram";
392 };
393
394 channel@a2 {
395 gw,mode = <2>;
396 reg = <0xa2>;
397 label = "vdd_gsc";
398 gw,voltage-divider-ohms = <10000 10000>;
399 };
400 };
401
402 fan-controller@a {
403 compatible = "gw,gsc-fan";
404 reg = <0x0a>;
405 };
406 };
407
408 gpio: gpio@23 {
409 compatible = "nxp,pca9555";
410 reg = <0x23>;
411 gpio-controller;
412 #gpio-cells = <2>;
413 interrupt-parent = <&gsc>;
414 interrupts = <4>;
415 };
416
417 eeprom@50 {
418 compatible = "atmel,24c02";
419 reg = <0x50>;
420 pagesize = <16>;
421 };
422
423 eeprom@51 {
424 compatible = "atmel,24c02";
425 reg = <0x51>;
426 pagesize = <16>;
427 };
428
429 eeprom@52 {
430 compatible = "atmel,24c02";
431 reg = <0x52>;
432 pagesize = <16>;
433 };
434
435 eeprom@53 {
436 compatible = "atmel,24c02";
437 reg = <0x53>;
438 pagesize = <16>;
439 };
440
441 rtc@68 {
442 compatible = "dallas,ds1672";
443 reg = <0x68>;
444 };
445};
446
447&i2c2 {
448 clock-frequency = <400000>;
449 pinctrl-names = "default", "gpio";
450 pinctrl-0 = <&pinctrl_i2c2>;
451 pinctrl-1 = <&pinctrl_i2c2_gpio>;
452 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
453 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
454 status = "okay";
455
456 accelerometer@19 {
457 compatible = "st,lis2de12";
458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_accel>;
460 reg = <0x19>;
461 st,drdy-int-pin = <1>;
462 interrupt-parent = <&gpio1>;
463 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
464 };
465
466 switch: switch@5f {
467 compatible = "microchip,ksz9897";
468 reg = <0x5f>;
469 pinctrl-0 = <&pinctrl_ksz>;
470 interrupt-parent = <&gpio4>;
471 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
472
473 ports {
474 #address-cells = <1>;
475 #size-cells = <0>;
476
477 lan1: port@0 {
478 reg = <0>;
479 label = "lan1";
480 phy-mode = "internal";
481 local-mac-address = [00 00 00 00 00 00];
482 };
483
484 lan2: port@1 {
485 reg = <1>;
486 label = "lan2";
487 phy-mode = "internal";
488 local-mac-address = [00 00 00 00 00 00];
489 };
490
491 lan3: port@2 {
492 reg = <2>;
493 label = "lan3";
494 phy-mode = "internal";
495 local-mac-address = [00 00 00 00 00 00];
496 };
497
498 lan4: port@3 {
499 reg = <3>;
500 label = "lan4";
501 phy-mode = "internal";
502 local-mac-address = [00 00 00 00 00 00];
503 };
504
505 lan5: port@4 {
506 reg = <4>;
507 label = "lan5";
508 phy-mode = "internal";
509 local-mac-address = [00 00 00 00 00 00];
510 };
511
512 port@5 {
513 reg = <5>;
514 ethernet = <&fec>;
515 phy-mode = "rgmii-id";
516
517 fixed-link {
518 speed = <1000>;
519 full-duplex;
520 };
521 };
522 };
523 };
524};
525
526&i2c3 {
527 clock-frequency = <400000>;
528 pinctrl-names = "default", "gpio";
529 pinctrl-0 = <&pinctrl_i2c3>;
530 pinctrl-1 = <&pinctrl_i2c3_gpio>;
531 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
532 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
533 status = "okay";
534
535 pmic@25 {
536 compatible = "nxp,pca9450c";
537 reg = <0x25>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_pmic>;
540 interrupt-parent = <&gpio3>;
541 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
542
543 regulators {
544 BUCK1 {
545 regulator-name = "BUCK1";
546 regulator-min-microvolt = <720000>;
547 regulator-max-microvolt = <1000000>;
548 regulator-boot-on;
549 regulator-always-on;
550 regulator-ramp-delay = <3125>;
551 };
552
553 reg_arm: BUCK2 {
554 regulator-name = "BUCK2";
555 regulator-min-microvolt = <720000>;
556 regulator-max-microvolt = <1025000>;
557 regulator-boot-on;
558 regulator-always-on;
559 regulator-ramp-delay = <3125>;
560 nxp,dvs-run-voltage = <950000>;
561 nxp,dvs-standby-voltage = <850000>;
562 };
563
564 BUCK4 {
565 regulator-name = "BUCK4";
566 regulator-min-microvolt = <3000000>;
567 regulator-max-microvolt = <3600000>;
568 regulator-boot-on;
569 regulator-always-on;
570 };
571
572 BUCK5 {
573 regulator-name = "BUCK5";
574 regulator-min-microvolt = <1650000>;
575 regulator-max-microvolt = <1950000>;
576 regulator-boot-on;
577 regulator-always-on;
578 };
579
580 BUCK6 {
581 regulator-name = "BUCK6";
582 regulator-min-microvolt = <1045000>;
583 regulator-max-microvolt = <1155000>;
584 regulator-boot-on;
585 regulator-always-on;
586 };
587
588 LDO1 {
589 regulator-name = "LDO1";
590 regulator-min-microvolt = <1650000>;
591 regulator-max-microvolt = <1950000>;
592 regulator-boot-on;
593 regulator-always-on;
594 };
595
596 LDO3 {
597 regulator-name = "LDO3";
598 regulator-min-microvolt = <1710000>;
599 regulator-max-microvolt = <1890000>;
600 regulator-boot-on;
601 regulator-always-on;
602 };
603
604 LDO5 {
605 regulator-name = "LDO5";
606 regulator-min-microvolt = <1800000>;
607 regulator-max-microvolt = <3300000>;
608 regulator-boot-on;
609 regulator-always-on;
610 };
611 };
612 };
613};
614
615/* off-board header */
616&i2c4 {
617 clock-frequency = <400000>;
618 pinctrl-names = "default", "gpio";
619 pinctrl-0 = <&pinctrl_i2c4>;
620 pinctrl-1 = <&pinctrl_i2c4_gpio>;
621 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
622 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
623 status = "okay";
624};
625
626&pcie_phy {
627 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
628 fsl,clkreq-unsupported;
629 clocks = <&pcie0_refclk>;
630 clock-names = "ref";
631 status = "okay";
632};
633
634&pcie {
635 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_pcie0>;
637 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
638 status = "okay";
639};
640
641/* GPS / off-board header */
642&uart1 {
643 pinctrl-names = "default";
644 pinctrl-0 = <&pinctrl_uart1>;
645 status = "okay";
646};
647
648/* RS232 console */
649&uart2 {
650 pinctrl-names = "default";
651 pinctrl-0 = <&pinctrl_uart2>;
652 status = "okay";
653};
654
655/* bluetooth HCI */
656&uart3 {
657 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
659 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
660 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
661 status = "okay";
662
663 bluetooth {
664 compatible = "brcm,bcm4330-bt";
665 shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
666 };
667};
668
669&uart4 {
670 pinctrl-names = "default";
671 pinctrl-0 = <&pinctrl_uart4>;
672 status = "okay";
673};
674
675/* USB1 - Type C front panel */
676&usb3_0 {
677 pinctrl-names = "default";
678 pinctrl-0 = <&pinctrl_usb1>;
679 fsl,over-current-active-low;
680 status = "okay";
681};
682
683&usb3_phy0 {
684 status = "okay";
685};
686
687&usb_dwc3_0 {
688 /* dual role is implemented but not a full featured OTG */
689 adp-disable;
690 hnp-disable;
691 srp-disable;
692 dr_mode = "otg";
693 usb-role-switch;
694 role-switch-default-mode = "peripheral";
695 status = "okay";
696
697 connector {
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_usbcon1>;
700 compatible = "gpio-usb-b-connector", "usb-b-connector";
701 type = "micro";
702 label = "Type-C";
703 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
704 };
705};
706
707/* USB2 - USB3.0 Hub */
708&usb3_phy1 {
709 vbus-supply = <&reg_usb2_vbus>;
710 status = "okay";
711};
712
713&usb3_1 {
714 fsl,permanently-attached;
715 fsl,disable-port-power-control;
716 status = "okay";
717};
718
719&usb_dwc3_1 {
720 dr_mode = "host";
721 status = "okay";
722};
723
724/* SDIO WiFi */
725&usdhc1 {
726 pinctrl-names = "default", "state_100mhz", "state_200mhz";
727 pinctrl-0 = <&pinctrl_usdhc1>;
728 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
729 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
730 bus-width = <4>;
731 non-removable;
732 vmmc-supply = <&reg_wifi_en>;
733 #address-cells = <1>;
734 #size-cells = <0>;
735 status = "okay";
736
737 wifi@0 {
738 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
739 reg = <0>;
740 };
741};
742
743/* eMMC */
744&usdhc3 {
745 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
746 assigned-clock-rates = <400000000>;
747 pinctrl-names = "default", "state_100mhz", "state_200mhz";
748 pinctrl-0 = <&pinctrl_usdhc3>;
749 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
750 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
751 bus-width = <8>;
752 non-removable;
753 status = "okay";
754};
755
756&wdog1 {
757 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_wdog>;
759 fsl,ext-reset-output;
760 status = "okay";
761};
762
763&iomuxc {
764 pinctrl-names = "default";
765 pinctrl-0 = <&pinctrl_hog>;
766
767 pinctrl_hog: hoggrp {
768 fsl,pins = <
769 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
770 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
771 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */
772 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
773 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */
774 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */
775 MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */
776 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
777 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
778 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
779 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
780 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
781 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
782 >;
783 };
784
785 pinctrl_accel: accelgrp {
786 fsl,pins = <
787 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
788 >;
789 };
790
791 pinctrl_eqos: eqosgrp {
792 fsl,pins = <
793 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
794 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
795 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
796 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
797 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
798 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
799 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
800 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
801 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
802 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
803 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
804 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
805 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
806 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
807 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
808 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
809 >;
810 };
811
812 pinctrl_fec: fecgrp {
813 fsl,pins = <
814 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
815 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
816 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
817 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
818 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
819 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
820 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
821 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
822 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
823 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
824 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
825 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
826 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
827 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
828 >;
829 };
830
831 pinctrl_flexcan1: flexcan1grp {
832 fsl,pins = <
833 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
834 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
835 >;
836 };
837
838 pinctrl_flexcan2: flexcan2grp {
839 fsl,pins = <
840 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
841 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
842 >;
843 };
844
845 pinctrl_gsc: gscgrp {
846 fsl,pins = <
847 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
848 >;
849 };
850
851 pinctrl_i2c1: i2c1grp {
852 fsl,pins = <
853 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
854 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
855 >;
856 };
857
858 pinctrl_i2c1_gpio: i2c1gpiogrp {
859 fsl,pins = <
860 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
861 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
862 >;
863 };
864
865 pinctrl_i2c2: i2c2grp {
866 fsl,pins = <
867 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
868 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
869 >;
870 };
871
872 pinctrl_i2c2_gpio: i2c2gpiogrp {
873 fsl,pins = <
874 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
875 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
876 >;
877 };
878
879 pinctrl_i2c3: i2c3grp {
880 fsl,pins = <
881 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
882 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
883 >;
884 };
885
886 pinctrl_i2c3_gpio: i2c3gpiogrp {
887 fsl,pins = <
888 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
889 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
890 >;
891 };
892
893 pinctrl_i2c4: i2c4grp {
894 fsl,pins = <
895 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
896 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
897 >;
898 };
899
900 pinctrl_i2c4_gpio: i2c4gpiogrp {
901 fsl,pins = <
902 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
903 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
904 >;
905 };
906
907 pinctrl_ksz: kszgrp {
908 fsl,pins = <
909 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
910 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
911 >;
912 };
913
914 pinctrl_gpio_leds: ledgrp {
915 fsl,pins = <
916 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
917 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
918 >;
919 };
920
921 pinctrl_pcie0: pciegrp {
922 fsl,pins = <
923 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106
924 >;
925 };
926
927 pinctrl_pmic: pmicgrp {
928 fsl,pins = <
929 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
930 >;
931 };
932
933 pinctrl_pps: ppsgrp {
934 fsl,pins = <
935 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
936 >;
937 };
938
939 pinctrl_reg_can1: regcan1grp {
940 fsl,pins = <
941 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
942 >;
943 };
944
945 pinctrl_reg_can2: regcan2grp {
946 fsl,pins = <
947 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154
948 >;
949 };
950
951 pinctrl_reg_usb2: regusb2grp {
952 fsl,pins = <
953 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
954 >;
955 };
956
957 pinctrl_reg_wifi: regwifigrp {
958 fsl,pins = <
959 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
960 >;
961 };
962
963 pinctrl_spi1: spi1grp {
964 fsl,pins = <
965 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82
966 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82
967 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82
968 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
969 >;
970 };
971
972 pinctrl_spi2: spi2grp {
973 fsl,pins = <
974 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
975 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
976 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
977 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
978 >;
979 };
980
981 pinctrl_uart1: uart1grp {
982 fsl,pins = <
983 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
984 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
985 >;
986 };
987
988 pinctrl_uart2: uart2grp {
989 fsl,pins = <
990 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
991 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
992 >;
993 };
994
995 pinctrl_uart3: uart3grp {
996 fsl,pins = <
997 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
998 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
999 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
1000 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
1001 >;
1002 };
1003
1004 pinctrl_uart3_gpio: uart3gpiogrp {
1005 fsl,pins = <
1006 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
1007 >;
1008 };
1009
1010 pinctrl_uart4: uart4grp {
1011 fsl,pins = <
1012 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
1013 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
1014 >;
1015 };
1016
1017 pinctrl_usb1: usb1grp {
1018 fsl,pins = <
1019 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
1020 >;
1021 };
1022
1023 pinctrl_usbcon1: usb1congrp {
1024 fsl,pins = <
1025 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
1026 >;
1027 };
1028
1029 pinctrl_usdhc1: usdhc1grp {
1030 fsl,pins = <
1031 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
1032 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
1033 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
1034 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
1035 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
1036 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
1037 >;
1038 };
1039
1040 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1041 fsl,pins = <
1042 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
1043 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
1044 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
1045 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
1046 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
1047 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
1048 >;
1049 };
1050
1051 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1052 fsl,pins = <
1053 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
1054 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
1055 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
1056 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
1057 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
1058 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
1059 >;
1060 };
1061
1062 pinctrl_usdhc3: usdhc3grp {
1063 fsl,pins = <
1064 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
1065 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
1066 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
1067 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
1068 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
1069 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
1070 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
1071 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
1072 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
1073 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
1074 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
1075 >;
1076 };
1077
1078 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1079 fsl,pins = <
1080 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1081 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1082 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1083 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1084 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1085 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1086 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1087 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1088 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1089 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1090 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1091 >;
1092 };
1093
1094 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1095 fsl,pins = <
1096 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1097 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1098 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1099 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1100 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1101 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1102 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1103 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1104 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1105 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1106 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1107 >;
1108 };
1109
1110 pinctrl_wdog: wdoggrp {
1111 fsl,pins = <
1112 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
1113 >;
1114 };
1115};