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wdenk7a428cc2003-06-15 22:40:42 +00001/*
Jerry Huang0caea1a2010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Flemingad347bb2008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk7a428cc2003-06-15 22:40:42 +00006 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenk7a428cc2003-06-15 22:40:42 +00008 */
9
10#ifndef _MMC_H_
11#define _MMC_H_
wdenk7a428cc2003-06-15 22:40:42 +000012
Andy Flemingad347bb2008-10-30 16:41:01 -050013#include <linux/list.h>
Lad, Prabhakar8dc6df82012-06-24 21:35:20 +000014#include <linux/compiler.h>
Mateusz Zalega05d2f412014-04-30 13:04:15 +020015#include <part.h>
Andy Flemingad347bb2008-10-30 16:41:01 -050016
Pantelis Antonioua095bfd2015-01-23 12:12:01 +020017/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
18#define SD_VERSION_SD (1U << 31)
19#define MMC_VERSION_MMC (1U << 30)
20
21#define MAKE_SDMMC_VERSION(a, b, c) \
22 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
23#define MAKE_SD_VERSION(a, b, c) \
24 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
25#define MAKE_MMC_VERSION(a, b, c) \
26 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
27
28#define EXTRACT_SDMMC_MAJOR_VERSION(x) \
29 (((u32)(x) >> 16) & 0xff)
30#define EXTRACT_SDMMC_MINOR_VERSION(x) \
31 (((u32)(x) >> 8) & 0xff)
32#define EXTRACT_SDMMC_CHANGE_VERSION(x) \
33 ((u32)(x) & 0xff)
34
35#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
36#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
37#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
38#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
39
40#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
41#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
42#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
43#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
44#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
45#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
46#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
47#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
48#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
49#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
50#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
51#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
Stefan Wahren1243cd82016-06-16 17:54:06 +000052#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
Andy Flemingad347bb2008-10-30 16:41:01 -050053
Jaehoon Chung0d1791d2014-05-16 13:59:53 +090054#define MMC_MODE_HS (1 << 0)
55#define MMC_MODE_HS_52MHz (1 << 1)
56#define MMC_MODE_4BIT (1 << 2)
57#define MMC_MODE_8BIT (1 << 3)
58#define MMC_MODE_SPI (1 << 4)
Rob Herring5fd3edd2015-03-23 17:56:59 -050059#define MMC_MODE_DDR_52MHz (1 << 5)
Ɓukasz Majewskib6fe0dc2012-03-12 22:07:18 +000060
Andy Flemingad347bb2008-10-30 16:41:01 -050061#define SD_DATA_4BIT 0x00040000
62
Pantelis Antonioua095bfd2015-01-23 12:12:01 +020063#define IS_SD(x) ((x)->version & SD_VERSION_SD)
Andrew Gabbasov90cccbf2015-03-19 07:44:02 -050064#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
Andy Flemingad347bb2008-10-30 16:41:01 -050065
66#define MMC_DATA_READ 1
67#define MMC_DATA_WRITE 2
68
69#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
70#define UNUSABLE_ERR -17 /* Unusable Card */
71#define COMM_ERR -18 /* Communications Error */
72#define TIMEOUT -19
Andrew Gabbasov3a669bc2015-03-19 07:44:07 -050073#define SWITCH_ERR -20 /* Card reports failure to switch mode */
Andy Flemingad347bb2008-10-30 16:41:01 -050074
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020075#define MMC_CMD_GO_IDLE_STATE 0
76#define MMC_CMD_SEND_OP_COND 1
77#define MMC_CMD_ALL_SEND_CID 2
78#define MMC_CMD_SET_RELATIVE_ADDR 3
79#define MMC_CMD_SET_DSR 4
Andy Flemingad347bb2008-10-30 16:41:01 -050080#define MMC_CMD_SWITCH 6
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020081#define MMC_CMD_SELECT_CARD 7
Andy Flemingad347bb2008-10-30 16:41:01 -050082#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020083#define MMC_CMD_SEND_CSD 9
84#define MMC_CMD_SEND_CID 10
Andy Flemingad347bb2008-10-30 16:41:01 -050085#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020086#define MMC_CMD_SEND_STATUS 13
87#define MMC_CMD_SET_BLOCKLEN 16
88#define MMC_CMD_READ_SINGLE_BLOCK 17
89#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Pierre Aubert343cd9f2014-04-24 10:30:06 +020090#define MMC_CMD_SET_BLOCK_COUNT 23
Andy Flemingad347bb2008-10-30 16:41:01 -050091#define MMC_CMD_WRITE_SINGLE_BLOCK 24
92#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wenea526762011-06-22 17:03:31 +000093#define MMC_CMD_ERASE_GROUP_START 35
94#define MMC_CMD_ERASE_GROUP_END 36
95#define MMC_CMD_ERASE 38
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +020096#define MMC_CMD_APP_CMD 55
Thomas Chou1254c3d2010-12-24 13:12:21 +000097#define MMC_CMD_SPI_READ_OCR 58
98#define MMC_CMD_SPI_CRC_ON_OFF 59
Amar1104e9b2013-04-27 11:42:58 +053099#define MMC_CMD_RES_MAN 62
100
101#define MMC_CMD62_ARG1 0xefac62ec
102#define MMC_CMD62_ARG2 0xcbaea7
103
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +0200104
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +0200105#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Flemingad347bb2008-10-30 16:41:01 -0500106#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +0200107#define SD_CMD_SEND_IF_COND 8
Otavio Salvadorfad3e062015-02-17 10:42:43 -0200108#define SD_CMD_SWITCH_UHS18V 11
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +0200109
110#define SD_CMD_APP_SET_BUS_WIDTH 6
Lei Wenea526762011-06-22 17:03:31 +0000111#define SD_CMD_ERASE_WR_BLK_START 32
112#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +0200113#define SD_CMD_APP_SEND_OP_COND 41
Andy Flemingad347bb2008-10-30 16:41:01 -0500114#define SD_CMD_APP_SEND_SCR 51
115
116/* SCR definitions in different words */
117#define SD_HIGHSPEED_BUSY 0x00020000
118#define SD_HIGHSPEED_SUPPORTED 0x00020000
119
Thomas Chou225d4c02011-04-19 03:48:31 +0000120#define OCR_BUSY 0x80000000
121#define OCR_HCS 0x40000000
Raffaele Recalcati1df837e2011-03-11 02:01:13 +0000122#define OCR_VOLTAGE_MASK 0x007FFF80
123#define OCR_ACCESS_MODE 0x60000000
Andy Flemingad347bb2008-10-30 16:41:01 -0500124
Eric Nelson957e0662015-12-07 07:50:01 -0700125#define MMC_ERASE_ARG 0x00000000
126#define MMC_SECURE_ERASE_ARG 0x80000000
127#define MMC_TRIM_ARG 0x00000001
128#define MMC_DISCARD_ARG 0x00000003
129#define MMC_SECURE_TRIM1_ARG 0x80000001
130#define MMC_SECURE_TRIM2_ARG 0x80008000
Lei Wenea526762011-06-22 17:03:31 +0000131
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000132#define MMC_STATUS_MASK (~0x0206BF7F)
Andrew Gabbasove80682f2014-04-03 04:34:32 -0500133#define MMC_STATUS_SWITCH_ERROR (1 << 7)
Thomas Chou225d4c02011-04-19 03:48:31 +0000134#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
135#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Chou45385002011-04-19 03:48:32 +0000136#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati01a0dc62011-03-11 02:01:12 +0000137
Jan Kloetzke31789322012-02-05 22:29:12 +0000138#define MMC_STATE_PRG (7 << 9)
139
Andy Flemingad347bb2008-10-30 16:41:01 -0500140#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
141#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
142#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
143#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
144#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
145#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
146#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
147#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
148#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
149#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
150#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
151#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
152#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
153#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
154#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
155#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
156#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
157
158#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
159#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
160 addressed by index which are
161 1 in value field */
162#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
163 addressed by index, which are
164 1 in value field */
165#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
166
167#define SD_SWITCH_CHECK 0
168#define SD_SWITCH_SWITCH 1
169
170/*
171 * EXT_CSD fields
172 */
Diego Santa Cruz3b62d842014-12-23 10:50:22 +0100173#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
174#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
Stephen Warrene315ae82013-06-11 15:14:01 -0600175#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Markus Niebel6d398922014-11-18 15:11:42 +0100176#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
Oliver Metzb3f14092013-10-01 20:32:07 +0200177#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100178#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
Lei Wen217467f2011-10-03 20:35:10 +0000179#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
Tom Rini35a3ea12014-02-07 14:15:20 -0500180#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Diego Santa Cruz80200272014-12-23 10:50:31 +0100181#define EXT_CSD_WR_REL_PARAM 166 /* R */
182#define EXT_CSD_WR_REL_SET 167 /* R/W */
Stephen Warrene315ae82013-06-11 15:14:01 -0600183#define EXT_CSD_RPMB_MULT 168 /* RO */
Lei Wen217467f2011-10-03 20:35:10 +0000184#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Amar1104e9b2013-04-27 11:42:58 +0530185#define EXT_CSD_BOOT_BUS_WIDTH 177
Lei Wen217467f2011-10-03 20:35:10 +0000186#define EXT_CSD_PART_CONF 179 /* R/W */
187#define EXT_CSD_BUS_WIDTH 183 /* R/W */
188#define EXT_CSD_HS_TIMING 185 /* R/W */
189#define EXT_CSD_REV 192 /* RO */
190#define EXT_CSD_CARD_TYPE 196 /* RO */
191#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
Stephen Warrene315ae82013-06-11 15:14:01 -0600192#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Lei Wen217467f2011-10-03 20:35:10 +0000193#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren009784c2012-07-30 10:55:43 +0000194#define EXT_CSD_BOOT_MULT 226 /* RO */
Andy Flemingad347bb2008-10-30 16:41:01 -0500195
196/*
197 * EXT_CSD field definitions
198 */
199
Thomas Chou225d4c02011-04-19 03:48:31 +0000200#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
201#define EXT_CSD_CMD_SET_SECURE (1 << 1)
202#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Flemingad347bb2008-10-30 16:41:01 -0500203
Thomas Chou225d4c02011-04-19 03:48:31 +0000204#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
205#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900206#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
207#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
208#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
209 | EXT_CSD_CARD_TYPE_DDR_1_2V)
Andy Flemingad347bb2008-10-30 16:41:01 -0500210
211#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
212#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
213#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Jaehoon Chung38ce30b2014-05-16 13:59:54 +0900214#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
215#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
Haavard Skinnemoen31e5ad02008-05-22 11:09:59 +0200216
Amar1104e9b2013-04-27 11:42:58 +0530217#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
218#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
219#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
220#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
221
222#define EXT_CSD_BOOT_ACK(x) (x << 6)
223#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
224#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
225
Tom Rini4cf854c2014-02-05 10:24:22 -0500226#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
227#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
228#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
Amar1104e9b2013-04-27 11:42:58 +0530229
Markus Niebel6d398922014-11-18 15:11:42 +0100230#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
231
Diego Santa Cruzc145f9e2014-12-23 10:50:17 +0100232#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
233#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
234
Diego Santa Cruz80200272014-12-23 10:50:31 +0100235#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
236
237#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
238#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
239
Andy Fleming724ecf02008-10-30 16:31:39 -0500240#define R1_ILLEGAL_COMMAND (1 << 22)
241#define R1_APP_CMD (1 << 5)
242
Andy Flemingad347bb2008-10-30 16:41:01 -0500243#define MMC_RSP_PRESENT (1 << 0)
Thomas Chou225d4c02011-04-19 03:48:31 +0000244#define MMC_RSP_136 (1 << 1) /* 136 bit response */
245#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
246#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
247#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Flemingad347bb2008-10-30 16:41:01 -0500248
Thomas Chou225d4c02011-04-19 03:48:31 +0000249#define MMC_RSP_NONE (0)
250#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Flemingad347bb2008-10-30 16:41:01 -0500251#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
252 MMC_RSP_BUSY)
Thomas Chou225d4c02011-04-19 03:48:31 +0000253#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
254#define MMC_RSP_R3 (MMC_RSP_PRESENT)
255#define MMC_RSP_R4 (MMC_RSP_PRESENT)
256#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
257#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
258#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Flemingad347bb2008-10-30 16:41:01 -0500259
Lei Wen31b99802011-05-02 16:26:26 +0000260#define MMCPART_NOAVAILABLE (0xff)
261#define PART_ACCESS_MASK (0x7)
262#define PART_SUPPORT (0x1)
Diego Santa Cruzc145f9e2014-12-23 10:50:17 +0100263#define ENHNCD_SUPPORT (0x2)
Oliver Metzb3f14092013-10-01 20:32:07 +0200264#define PART_ENH_ATTRIB (0x1f)
wdenk7a428cc2003-06-15 22:40:42 +0000265
Simon Glassa09c2b72013-04-03 08:54:30 +0000266/* Maximum block size for MMC */
267#define MMC_MAX_BLOCK_LEN 512
268
Amar1104e9b2013-04-27 11:42:58 +0530269/* The number of MMC physical partitions. These consist of:
270 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
271 */
272#define MMC_NUM_BOOT_PARTITION 2
Pierre Aubert343cd9f2014-04-24 10:30:06 +0200273#define MMC_PART_RPMB 3 /* RPMB partition number */
Amar1104e9b2013-04-27 11:42:58 +0530274
Simon Glass1e8eb1b2015-06-23 15:38:48 -0600275/* Driver model support */
276
277/**
278 * struct mmc_uclass_priv - Holds information about a device used by the uclass
279 */
280struct mmc_uclass_priv {
281 struct mmc *mmc;
282};
283
284/**
285 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
286 *
287 * Provided that the device is already probed and ready for use, this value
288 * will be available.
289 *
290 * @dev: Device
291 * @return associated mmc struct pointer if available, else NULL
292 */
293struct mmc *mmc_get_mmc_dev(struct udevice *dev);
294
295/* End of driver model support */
296
Andy Fleming724ecf02008-10-30 16:31:39 -0500297struct mmc_cid {
298 unsigned long psn;
299 unsigned short oid;
300 unsigned char mid;
301 unsigned char prv;
302 unsigned char mdt;
303 char pnm[7];
304};
305
Andy Flemingad347bb2008-10-30 16:41:01 -0500306struct mmc_cmd {
307 ushort cmdidx;
308 uint resp_type;
309 uint cmdarg;
Rabin Vincentbdf7a682009-04-05 13:30:55 +0530310 uint response[4];
Andy Flemingad347bb2008-10-30 16:41:01 -0500311};
312
313struct mmc_data {
314 union {
315 char *dest;
316 const char *src; /* src buffers don't get written to */
317 };
318 uint flags;
319 uint blocks;
320 uint blocksize;
321};
322
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200323/* forward decl. */
324struct mmc;
325
326struct mmc_ops {
327 int (*send_cmd)(struct mmc *mmc,
328 struct mmc_cmd *cmd, struct mmc_data *data);
329 void (*set_ios)(struct mmc *mmc);
330 int (*init)(struct mmc *mmc);
331 int (*getcd)(struct mmc *mmc);
332 int (*getwp)(struct mmc *mmc);
333};
334
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200335struct mmc_config {
336 const char *name;
337 const struct mmc_ops *ops;
338 uint host_caps;
339 uint voltages;
340 uint f_min;
341 uint f_max;
342 uint b_max;
343 unsigned char part_type;
344};
345
346/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
Andy Flemingad347bb2008-10-30 16:41:01 -0500347struct mmc {
Simon Glass59bc6f22016-05-01 13:52:41 -0600348#ifndef CONFIG_BLK
Andy Flemingad347bb2008-10-30 16:41:01 -0500349 struct list_head link;
Simon Glass59bc6f22016-05-01 13:52:41 -0600350#endif
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200351 const struct mmc_config *cfg; /* provided configuration */
Andy Flemingad347bb2008-10-30 16:41:01 -0500352 uint version;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200353 void *priv;
Lei Wen31b99802011-05-02 16:26:26 +0000354 uint has_init;
Andy Flemingad347bb2008-10-30 16:41:01 -0500355 int high_capacity;
356 uint bus_width;
357 uint clock;
358 uint card_caps;
Andy Flemingad347bb2008-10-30 16:41:01 -0500359 uint ocr;
Markus Niebel03951412013-12-16 13:40:46 +0100360 uint dsr;
361 uint dsr_imp;
Andy Flemingad347bb2008-10-30 16:41:01 -0500362 uint scr[2];
363 uint csd[4];
Rabin Vincentbdf7a682009-04-05 13:30:55 +0530364 uint cid[4];
Andy Flemingad347bb2008-10-30 16:41:01 -0500365 ushort rca;
Diego Santa Cruzc145f9e2014-12-23 10:50:17 +0100366 u8 part_support;
367 u8 part_attr;
Diego Santa Cruz37a50b92014-12-23 10:50:33 +0100368 u8 wr_rel_set;
Lei Wen31b99802011-05-02 16:26:26 +0000369 char part_config;
Andy Flemingad347bb2008-10-30 16:41:01 -0500370 uint tran_speed;
371 uint read_bl_len;
372 uint write_bl_len;
Diego Santa Cruz747f6fa2014-12-23 10:50:24 +0100373 uint erase_grp_size; /* in 512-byte sectors */
Diego Santa Cruz61b78fe2014-12-23 10:50:25 +0100374 uint hc_wp_grp_size; /* in 512-byte sectors */
Andy Flemingad347bb2008-10-30 16:41:01 -0500375 u64 capacity;
Stephen Warrene315ae82013-06-11 15:14:01 -0600376 u64 capacity_user;
377 u64 capacity_boot;
378 u64 capacity_rpmb;
379 u64 capacity_gp[4];
Diego Santa Cruz3b62d842014-12-23 10:50:22 +0100380 u64 enh_user_start;
381 u64 enh_user_size;
Simon Glass59bc6f22016-05-01 13:52:41 -0600382#ifndef CONFIG_BLK
Simon Glasse3394752016-02-29 15:25:34 -0700383 struct blk_desc block_dev;
Simon Glass59bc6f22016-05-01 13:52:41 -0600384#endif
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000385 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
386 char init_in_progress; /* 1 if we have done mmc_start_init() */
387 char preinit; /* start init as early as possible */
Andrew Gabbasov9fc2a412014-12-01 06:59:09 -0600388 int ddr_mode;
Simon Glass77ca42b2016-05-01 13:52:34 -0600389#ifdef CONFIG_DM_MMC
390 struct udevice *dev; /* Device for this MMC controller */
391#endif
Andy Flemingad347bb2008-10-30 16:41:01 -0500392};
393
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100394struct mmc_hwpart_conf {
395 struct {
396 uint enh_start; /* in 512-byte sectors */
397 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
Diego Santa Cruz80200272014-12-23 10:50:31 +0100398 unsigned wr_rel_change : 1;
399 unsigned wr_rel_set : 1;
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100400 } user;
401 struct {
402 uint size; /* in 512-byte sectors */
Diego Santa Cruz80200272014-12-23 10:50:31 +0100403 unsigned enhanced : 1;
404 unsigned wr_rel_change : 1;
405 unsigned wr_rel_set : 1;
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100406 } gp_part[4];
407};
408
409enum mmc_hwpart_conf_mode {
410 MMC_HWPART_CONF_CHECK,
411 MMC_HWPART_CONF_SET,
412 MMC_HWPART_CONF_COMPLETE,
413};
414
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200415struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
Simon Glassa70a1462016-05-01 13:52:40 -0600416
417/**
418 * mmc_bind() - Set up a new MMC device ready for probing
419 *
420 * A child block device is bound with the IF_TYPE_MMC interface type. This
421 * allows the device to be used with CONFIG_BLK
422 *
423 * @dev: MMC device to set up
424 * @mmc: MMC struct
425 * @cfg: MMC configuration
426 * @return 0 if OK, -ve on error
427 */
428int mmc_bind(struct udevice *dev, struct mmc *mmc,
429 const struct mmc_config *cfg);
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200430void mmc_destroy(struct mmc *mmc);
Simon Glassa70a1462016-05-01 13:52:40 -0600431
432/**
433 * mmc_unbind() - Unbind a MMC device's child block device
434 *
435 * @dev: MMC device
436 * @return 0 if OK, -ve on error
437 */
438int mmc_unbind(struct udevice *dev);
Andy Flemingad347bb2008-10-30 16:41:01 -0500439int mmc_initialize(bd_t *bis);
440int mmc_init(struct mmc *mmc);
441int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang0caea1a2010-11-25 17:06:07 +0000442void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Flemingad347bb2008-10-30 16:41:01 -0500443struct mmc *find_mmc_device(int dev_num);
Steve Sakomane4548302010-07-01 12:12:42 -0700444int mmc_set_dev(int dev_num);
Andy Flemingad347bb2008-10-30 16:41:01 -0500445void print_mmc_devices(char separator);
Lei Wend430d7c2011-05-02 16:26:25 +0000446int get_mmc_num(void);
Diego Santa Cruz69eb71a02014-12-23 10:50:29 +0100447int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
448 enum mmc_hwpart_conf_mode mode);
Thierry Redingb9c8b772012-01-02 01:15:37 +0000449int mmc_getcd(struct mmc *mmc);
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +0200450int board_mmc_getcd(struct mmc *mmc);
Nikita Kiryanov020f2612012-12-03 02:19:46 +0000451int mmc_getwp(struct mmc *mmc);
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +0200452int board_mmc_getwp(struct mmc *mmc);
Markus Niebel03951412013-12-16 13:40:46 +0100453int mmc_set_dsr(struct mmc *mmc, u16 val);
Amar1104e9b2013-04-27 11:42:58 +0530454/* Function to change the size of boot partition and rpmb partitions */
455int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
456 unsigned long rpmbsize);
Tom Rinif8c6f792014-02-05 10:24:21 -0500457/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
458int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
Tom Rini4cf854c2014-02-05 10:24:22 -0500459/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
460int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
Tom Rini35a3ea12014-02-07 14:15:20 -0500461/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
462int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
Pierre Aubert343cd9f2014-04-24 10:30:06 +0200463/* Functions to read / write the RPMB partition */
464int mmc_rpmb_set_key(struct mmc *mmc, void *key);
465int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
466int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
467 unsigned short cnt, unsigned char *key);
468int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
469 unsigned short cnt, unsigned char *key);
Che-Liang Chiou4a2c7d72012-11-28 15:21:13 +0000470/**
471 * Start device initialization and return immediately; it does not block on
472 * polling OCR (operation condition register) status. Then you should call
473 * mmc_init, which would block on polling OCR status and complete the device
474 * initializatin.
475 *
476 * @param mmc Pointer to a MMC device struct
477 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
478 */
479int mmc_start_init(struct mmc *mmc);
480
481/**
482 * Set preinit flag of mmc device.
483 *
484 * This will cause the device to be pre-inited during mmc_initialize(),
485 * which may save boot time if the device is not accessed until later.
486 * Some eMMC devices take 200-300ms to init, but unfortunately they
487 * must be sent a series of commands to even get them to start preparing
488 * for operation.
489 *
490 * @param mmc Pointer to a MMC device struct
491 * @param preinit preinit flag value
492 */
493void mmc_set_preinit(struct mmc *mmc, int preinit);
494
Paul Burtond4519552013-09-04 16:12:26 +0100495#ifdef CONFIG_MMC_SPI
Tom Rini23bcc9b2014-03-28 16:55:29 -0400496#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
Paul Burtond4519552013-09-04 16:12:26 +0100497#else
498#define mmc_host_is_spi(mmc) 0
499#endif
Thomas Chou1254c3d2010-12-24 13:12:21 +0000500struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyerc718a562010-08-13 10:31:06 +0200501
Paul Kocialkowski2439fe92014-11-08 20:55:45 +0100502void board_mmc_power_init(void);
Fabio Estevam72fed482014-02-15 14:51:59 -0200503int board_mmc_init(bd_t *bis);
Jeroen Hofsteeaedeeaa2014-07-12 21:24:08 +0200504int cpu_mmc_init(bd_t *bis);
Jeroen Hofsteed491ad02014-10-08 22:58:05 +0200505int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
Clemens Gruber6362b112016-01-26 16:20:38 +0100506int mmc_get_env_dev(void);
Fabio Estevam72fed482014-02-15 14:51:59 -0200507
Simon Glass509805b2015-01-27 22:13:39 -0700508struct pci_device_id;
509
510/**
511 * pci_mmc_init() - set up PCI MMC devices
512 *
513 * This finds all the matching PCI IDs and sets them up as MMC devices.
514 *
515 * @name: Name to use for devices
Simon Glass0b619282015-11-29 13:18:08 -0700516 * @mmc_supported: PCI IDs to search for, terminated by {0, 0}
Simon Glass509805b2015-01-27 22:13:39 -0700517 */
Simon Glass0b619282015-11-29 13:18:08 -0700518int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
Simon Glass509805b2015-01-27 22:13:39 -0700519
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200520/* Set block count limit because of 16 bit register limit on some hardware*/
521#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
522#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
523#endif
524
Simon Glass8d60adb2016-05-01 13:52:27 -0600525/**
526 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
527 *
528 * @mmc: MMC device
529 * @return block device if found, else NULL
530 */
531struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
532
wdenk7a428cc2003-06-15 22:40:42 +0000533#endif /* _MMC_H_ */