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Heiko Schocherdc5f4e42007-02-16 07:57:42 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocherdc5f4e42007-02-16 07:57:42 +01006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
15
Masahiro Yamada608ed2c2014-01-16 11:03:07 +090016#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010017#define CONFIG_JUPITER 1 /* ... on Jupiter board */
Anatolij Gustschinccab47e2015-08-13 23:57:56 +020018#define CONFIG_DISPLAY_BOARDINFO
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010019
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020020/*
21 * Valid values for CONFIG_SYS_TEXT_BASE are:
22 * 0xFFF00000 boot high (standard configuration)
23 * 0x00100000 boot from RAM (for testing only)
24 */
25#ifndef CONFIG_SYS_TEXT_BASE
26#define CONFIG_SYS_TEXT_BASE 0xFFF00000
27#endif
28
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020029#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010030
31#define CONFIG_BOARD_EARLY_INIT_R 1
32#define CONFIG_BOARD_EARLY_INIT_F 1
33
Becky Bruce03ea1be2008-05-08 19:02:12 -050034#define CONFIG_HIGH_BATS 1 /* High BATs supported */
35
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010036/*
37 * Serial console configuration
38 */
39#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
40#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010042
43/*
44 * PCI Mapping:
45 * 0x40000000 - 0x4fffffff - PCI Memory
46 * 0x50000000 - 0x50ffffff - PCI IO Space
47 */
Wolfgang Denk2f7f2d92007-03-08 21:49:27 +010048/*#define CONFIG_PCI */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010049
50#if defined(CONFIG_PCI)
51#define CONFIG_PCI_PNP 1
52#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liew521f97b2008-03-30 01:19:06 -050053#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010054
55#define CONFIG_PCI_MEM_BUS 0x40000000
56#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
57#define CONFIG_PCI_MEM_SIZE 0x10000000
58
59#define CONFIG_PCI_IO_BUS 0x50000000
60#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
61#define CONFIG_PCI_IO_SIZE 0x01000000
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010062#endif
63
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_XLB_PIPELINING 1
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010065
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010066#define CONFIG_MII 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010068
69/* Partitions */
70#define CONFIG_MAC_PARTITION
71#define CONFIG_DOS_PARTITION
72#define CONFIG_ISO_PARTITION
73
74#define CONFIG_TIMESTAMP /* Print image info with timestamp */
75
76/*
Jon Loeliger140b69c2007-07-10 09:38:02 -050077 * BOOTP options
78 */
79#define CONFIG_BOOTP_BOOTFILESIZE
80#define CONFIG_BOOTP_BOOTPATH
81#define CONFIG_BOOTP_GATEWAY
82#define CONFIG_BOOTP_HOSTNAME
83
Jon Loeliger140b69c2007-07-10 09:38:02 -050084/*
Jon Loeligerca8b5662007-07-04 22:32:51 -050085 * Command line configuration.
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010086 */
Jon Loeligerca8b5662007-07-04 22:32:51 -050087
Jon Loeliger140b69c2007-07-10 09:38:02 -050088#if defined(CONFIG_PCI)
89#define CODFIG_CMD_PCI
90#endif
91
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010092/*
93 * Autobooting
94 */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010095
96#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +010097 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Heiko Schocherdc5f4e42007-02-16 07:57:42 +010098 "echo"
99
100#undef CONFIG_BOOTARGS
101
102#define CONFIG_EXTRA_ENV_SETTINGS \
103 "netdev=eth0\0" \
104 "nfsargs=setenv bootargs root=/dev/nfs rw " \
105 "nfsroot=${serverip}:${rootpath}\0" \
106 "ramargs=setenv bootargs root=/dev/ram rw\0" \
107 "addip=setenv bootargs ${bootargs} " \
108 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
109 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk7108f362007-03-13 16:05:55 +0100110 "flash_nfs=run nfsargs addip addcons;" \
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100111 "bootm ${kernel_addr}\0" \
112 "flash_self=run ramargs addip;" \
113 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Wolfgang Denk7108f362007-03-13 16:05:55 +0100114 "addcons=setenv bootargs ${bootargs} console=${contyp}," \
Heiko Schocher162bbec2007-03-13 09:40:59 +0100115 "${baudrate}\0" \
116 "contyp=ttyS0\0" \
Wolfgang Denk7108f362007-03-13 16:05:55 +0100117 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
Heiko Schocher162bbec2007-03-13 09:40:59 +0100118 "bootm\0" \
119 "rootpath=/opt/eldk/ppc_6xx\0" \
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100120 "bootfile=/tftpboot/jupiter/uImage\0" \
121 ""
122
123#define CONFIG_BOOTCOMMAND "run flash_self"
124
125/*
126 * IPB Bus clocking configuration.
127 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100129
130#if 0
131/* pass open firmware flat tree */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100132#define OF_CPU "PowerPC,5200@0"
133#define OF_SOC "soc5200@f0000000"
134#define OF_TBCLK (bd->bi_busfreq / 8)
135#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
136#endif
137
138#if 0
139/*
140 * I2C configuration
141 */
142#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
146#define CONFIG_SYS_I2C_SLAVE 0x7F
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100147
148/*
149 * EEPROM configuration
150 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
152#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
153#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
154#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100155#endif
156
157/*
158 * Flash configuration
159 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_FLASH_BASE 0xFF000000
161#define CONFIG_SYS_FLASH_SIZE 0x01000000
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100162
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100164
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200165#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100166
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
168#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100169
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100171
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200172#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_CFI
174#define CONFIG_SYS_FLASH_EMPTY_INFO
175#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
176#define CONFIG_SYS_UPDATE_FLASH_SIZE 1
177#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100178
179/*
180 * Environment settings
181 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200182#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200183#define CONFIG_ENV_SIZE 0x20000
184#define CONFIG_ENV_SECT_SIZE 0x20000
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100185#define CONFIG_ENV_OVERWRITE 1
186
Heiko Schocher162bbec2007-03-13 09:40:59 +0100187/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200188#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
189#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Heiko Schocher162bbec2007-03-13 09:40:59 +0100190
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100191/*
192 * Memory map
193 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#define CONFIG_SYS_MBAR 0xF0000000
195#define CONFIG_SYS_SDRAM_BASE 0x00000000
196#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100197
198/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200200#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100201
Wolfgang Denk0191e472010-10-26 14:34:52 +0200202#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100204
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200205#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
207# define CONFIG_SYS_RAMBOOT 1
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100208#endif
209
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
211#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
212#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100213
214/*
215 * Ethernet configuration
216 */
217#define CONFIG_MPC5xxx_FEC 1
Ben Warrenbc1b9172009-02-05 23:58:25 -0800218#define CONFIG_MPC5xxx_FEC_MII100
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100219/*
Ben Warrenbc1b9172009-02-05 23:58:25 -0800220 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100221 */
Ben Warrenbc1b9172009-02-05 23:58:25 -0800222/* #define CONFIG_MPC5xxx_FEC_MII10 */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100223#define CONFIG_PHY_ADDR 0x00
224
225/*
226 * GPIO configuration
227 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100229
230/*
231 * Miscellaneous configurable options
232 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define CONFIG_SYS_LONGHELP /* undef to save memory */
Heiko Schocher162bbec2007-03-13 09:40:59 +0100234
235#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jon Loeligerca8b5662007-07-04 22:32:51 -0500236#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200237#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100238#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200239#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100240#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200241#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
242#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
243#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100244
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
246#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
247#define CONFIG_SYS_ALT_MEMTEST 1
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100248
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200249#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100250
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerca8b5662007-07-04 22:32:51 -0500252#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200253# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerca8b5662007-07-04 22:32:51 -0500254#endif
255
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100256/*
257 * Various low-level settings
258 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
260#define CONFIG_SYS_HID0_FINAL HID0_ICE
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100261
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
263#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
264#define CONFIG_SYS_BOOTCS_CFG 0x00047801
265#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
266#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100267
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200268#define CONFIG_SYS_CS_BURST 0x00000000
269#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100270
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200271#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Heiko Schocherdc5f4e42007-02-16 07:57:42 +0100272
273#endif /* __CONFIG_H */