Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / freescale / imx8mm-phyboard-polis-rdk.dts
blob: 92e62fe319290b44bc2961ffeb55f5195cbaaea2 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12#include "imx8mm-phycore-som.dtsi"
13
14/ {
15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
16 compatible = "phytec,imx8mm-phyboard-polis-rdk",
17 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
18
19 chosen {
20 stdout-path = &uart3;
21 };
22
23 bt_osc_32k: bt-lp-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
26 clock-output-names = "bt_osc_32k";
27 #clock-cells = <0>;
28 };
29
30 can_osc_40m: can-clock {
31 compatible = "fixed-clock";
32 clock-frequency = <40000000>;
33 clock-output-names = "can_osc_40m";
34 #clock-cells = <0>;
35 };
36
37 fan {
38 compatible = "gpio-fan";
39 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
40 gpio-fan,speed-map = <0 0
41 13000 1>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_fan>;
44 #cooling-cells = <2>;
45 };
46
47 leds {
48 compatible = "gpio-leds";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_leds>;
51
52 led-0 {
53 color = <LED_COLOR_ID_RED>;
54 function = LED_FUNCTION_DISK;
55 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
56 linux,default-trigger = "mmc2";
57 };
58
59 led-1 {
60 color = <LED_COLOR_ID_BLUE>;
61 function = LED_FUNCTION_DISK;
62 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "mmc1";
64 };
65
66 led-2 {
67 color = <LED_COLOR_ID_GREEN>;
68 function = LED_FUNCTION_CPU;
69 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
70 linux,default-trigger = "heartbeat";
71 };
72 };
73
74 usdhc1_pwrseq: pwr-seq {
75 compatible = "mmc-pwrseq-simple";
76 post-power-on-delay-ms = <100>;
77 power-off-delay-us = <60>;
78 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
79 };
80
81 reg_can_en: regulator-can-en {
82 compatible = "regulator-fixed";
83 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_can_en>;
86 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <3300000>;
88 regulator-name = "CAN_EN";
89 startup-delay-us = <20>;
90 };
91
92 reg_usb_otg1_vbus: regulator-usb-otg1 {
93 compatible = "regulator-fixed";
94 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
95 enable-active-high;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
98 regulator-name = "usb_otg1_vbus";
99 regulator-max-microvolt = <5000000>;
100 regulator-min-microvolt = <5000000>;
101 };
102
103 reg_usdhc2_vmmc: regulator-usdhc2 {
104 compatible = "regulator-fixed";
105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
106 enable-active-high;
107 off-on-delay-us = <20000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
110 regulator-max-microvolt = <3300000>;
111 regulator-min-microvolt = <3300000>;
112 regulator-name = "VSD_3V3";
113 };
114
115 reg_vcc_3v3: regulator-vcc-3v3 {
116 compatible = "regulator-fixed";
117 regulator-max-microvolt = <3300000>;
118 regulator-min-microvolt = <3300000>;
119 regulator-name = "VCC_3V3";
120 };
121};
122
123/* SPI - CAN MCP251XFD */
124&ecspi1 {
125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_ecspi1>;
128 status = "okay";
129
130 can0: can@0 {
131 compatible = "microchip,mcp251xfd";
132 clocks = <&can_osc_40m>;
133 interrupt-parent = <&gpio1>;
134 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can_int>;
137 reg = <0>;
138 spi-max-frequency = <20000000>;
139 xceiver-supply = <&reg_can_en>;
140 };
141};
142
143/* TPM */
144&ecspi2 {
145 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_ecspi2>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 status = "okay";
151
152 tpm: tpm@0 {
153 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
154 interrupt-parent = <&gpio2>;
155 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_tpm>;
158 reg = <0>;
159 spi-max-frequency = <43000000>;
160 };
161};
162
163&gpio1 {
164 gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT",
165 "", "", "", "RESET_ETHPHY",
166 "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
167 "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
168};
169
170&gpio2 {
171 gpio-line-names = "", "", "", "",
172 "", "", "BT_REG_ON", "WL_REG_ON",
173 "BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
174 "X_SD2_CD_B", "", "", "",
175 "", "", "", "SD2_RESET_B";
176};
177
178&gpio4 {
179 gpio-line-names = "", "", "", "",
180 "", "", "", "",
181 "FAN", "miniPCIe_nPERST", "", "",
182 "COEX1", "COEX2";
183};
184
185&gpio5 {
186 gpio-line-names = "", "", "", "",
187 "", "", "", "",
188 "", "ECSPI1_SS0";
189};
190
191&i2c4 {
192 clock-frequency = <400000>;
193 pinctrl-names = "default", "gpio";
194 pinctrl-0 = <&pinctrl_i2c4>;
195 pinctrl-1 = <&pinctrl_i2c4_gpio>;
196 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
197 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
198};
199
200/* PCIe */
201&pcie0 {
202 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
203 <&clk IMX8MM_CLK_PCIE1_CTRL>;
204 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
205 <&clk IMX8MM_SYS_PLL2_250M>;
206 assigned-clock-rates = <10000000>, <250000000>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_pcie>;
209 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
210 status = "okay";
211};
212
213&pcie_phy {
214 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
215 fsl,clkreq-unsupported;
216 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
217 fsl,tx-deemph-gen1 = <0x2d>;
218 fsl,tx-deemph-gen2 = <0xf>;
219 status = "okay";
220};
221
222&rv3028 {
223 trickle-resistor-ohms = <3000>;
224};
225
226&snvs_pwrkey {
227 status = "okay";
228};
229
230/* UART - RS232/RS485 */
231&uart1 {
232 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
233 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_uart1>;
236 uart-has-rtscts;
237 status = "okay";
238};
239
240/* UART - Sterling-LWB Bluetooth */
241&uart2 {
242 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
243 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
244 fsl,dte-mode;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_uart2_bt>;
247 uart-has-rtscts;
248 status = "okay";
249
250 bluetooth {
251 compatible = "brcm,bcm43438-bt";
252 clocks = <&bt_osc_32k>;
253 clock-names = "lpo";
254 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
255 interrupt-names = "host-wakeup";
256 interrupt-parent = <&gpio2>;
257 interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
258 max-speed = <2000000>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_bt>;
261 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
262 vddio-supply = <&reg_vcc_3v3>;
263 };
264};
265
266/* UART - console */
267&uart3 {
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_uart3>;
270 status = "okay";
271};
272
273/* USB */
274&usbotg1 {
275 adp-disable;
276 dr_mode = "otg";
277 over-current-active-low;
278 samsung,picophy-pre-emp-curr-control = <3>;
279 samsung,picophy-dc-vol-level-adjust = <7>;
280 srp-disable;
281 vbus-supply = <&reg_usb_otg1_vbus>;
282 status = "okay";
283};
284
285&usbotg2 {
286 disable-over-current;
287 dr_mode = "host";
288 samsung,picophy-pre-emp-curr-control = <3>;
289 samsung,picophy-dc-vol-level-adjust = <7>;
290 status = "okay";
291};
292
293/* SDIO - Sterling-LWB Wifi */
294&usdhc1 {
295 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
296 assigned-clock-rates = <200000000>;
297 bus-width = <4>;
298 mmc-pwrseq = <&usdhc1_pwrseq>;
299 non-removable;
300 no-1-8-v;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 status = "okay";
306
307 brcmf: wifi@1 {
308 compatible = "brcm,bcm4329-fmac";
309 reg = <1>;
310 };
311};
312
313/* SD-Card */
314&usdhc2 {
315 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
316 assigned-clock-rates = <200000000>;
317 bus-width = <4>;
318 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
319 disable-wp;
320 pinctrl-names = "default", "state_100mhz", "state_200mhz";
321 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
322 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
323 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
324 vmmc-supply = <&reg_usdhc2_vmmc>;
325 vqmmc-supply = <&reg_nvcc_sd2>;
326 status = "okay";
327};
328
329&iomuxc {
330 pinctrl_bt: btgrp {
331 fsl,pins = <
332 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
333 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
334 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
335 >;
336 };
337
338 pinctrl_can_en: can-engrp {
339 fsl,pins = <
340 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
341 >;
342 };
343
344 pinctrl_can_int: can-intgrp {
345 fsl,pins = <
346 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
347 >;
348 };
349
350 pinctrl_ecspi1: ecspi1grp {
351 fsl,pins = <
352 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
353 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
354 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
355 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
356 >;
357 };
358
359 pinctrl_ecspi2: ecspi2grp {
360 fsl,pins = <
361 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x80
362 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x80
363 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x80
364 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00
365 >;
366 };
367
368 pinctrl_fan: fan0grp {
369 fsl,pins = <
370 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
371 >;
372 };
373
374 pinctrl_i2c4: i2c4grp {
375 fsl,pins = <
376 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
377 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
378 >;
379 };
380
381 pinctrl_i2c4_gpio: i2c4gpiogrp {
382 fsl,pins = <
383 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e2
384 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e2
385 >;
386 };
387
388 pinctrl_leds: leds1grp {
389 fsl,pins = <
390 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
391 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
392 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
393 >;
394 };
395
396 pinctrl_pcie: pciegrp {
397 fsl,pins = <
398 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
399 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
400 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
401 >;
402 };
403
404 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
405 fsl,pins = <
406 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
407 >;
408 };
409
410 pinctrl_tpm: tpmgrp {
411 fsl,pins = <
412 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
413 >;
414 };
415
416 pinctrl_uart1: uart1grp {
417 fsl,pins = <
418 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
419 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
420 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
421 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
422 >;
423 };
424
425 pinctrl_uart2_bt: uart2btgrp {
426 fsl,pins = <
427 MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
428 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
429 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
430 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
431 >;
432 };
433
434 pinctrl_uart3: uart3grp {
435 fsl,pins = <
436 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
437 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
438 >;
439 };
440
441 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
442 fsl,pins = <
443 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
444 >;
445 };
446
447 pinctrl_usdhc1: usdhc1grp {
448 fsl,pins = <
449 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
450 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
451 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
452 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
453 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
454 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
455 >;
456 };
457
458 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
459 fsl,pins = <
460 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
461 >;
462 };
463
464 pinctrl_usdhc2: usdhc2grp {
465 fsl,pins = <
466 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
467 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
468 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
469 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
470 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
471 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
472 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
473 >;
474 };
475
476 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
477 fsl,pins = <
478 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
479 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
480 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
481 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
482 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
483 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
484 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
485 >;
486 };
487
488 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
489 fsl,pins = <
490 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
491 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
492 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
493 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
494 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
495 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
496 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
497 >;
498 };
499
500 pinctrl_wlan: wlangrp {
501 fsl,pins = <
502 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
503 >;
504 };
505};