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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm64 / freescale / fsl-ls208xa.dtsi
blob: ccba0a135b247e8c2f96e12c319c61c3d4efbd08 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017-2020 NXP
7 *
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 *
10 */
11
12#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13#include <dt-bindings/thermal/thermal.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16/ {
17 compatible = "fsl,ls2080a";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 crypto = &crypto;
24 rtc1 = &ftm_alarm0;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 serial2 = &serial2;
28 serial3 = &serial3;
29 };
30
31 cpu: cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 };
35
36 memory@80000000 {
37 device_type = "memory";
38 reg = <0x00000000 0x80000000 0 0x80000000>;
39 /* DRAM space - 1, size : 2 GB DRAM */
40 };
41
42 sysclk: sysclk {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <100000000>;
46 clock-output-names = "sysclk";
47 };
48
49 gic: interrupt-controller@6000000 {
50 compatible = "arm,gic-v3";
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
56 #interrupt-cells = <3>;
57 #address-cells = <2>;
58 #size-cells = <2>;
59 ranges;
60 interrupt-controller;
61 interrupts = <1 9 0x4>;
62
63 its: msi-controller@6020000 {
64 compatible = "arm,gic-v3-its";
65 msi-controller;
66 reg = <0x0 0x6020000 0 0x20000>;
67 };
68 };
69
70 rstcr: syscon@1e60000 {
71 compatible = "fsl,ls2080a-rstcr", "syscon";
72 reg = <0x0 0x1e60000 0x0 0x4>;
73 };
74
75 reboot {
76 compatible = "syscon-reboot";
77 regmap = <&rstcr>;
78 offset = <0x0>;
79 mask = <0x2>;
80 };
81
82 thermal-zones {
83 ddr-controller1 {
84 polling-delay-passive = <1000>;
85 polling-delay = <5000>;
86 thermal-sensors = <&tmu 1>;
87
88 trips {
89 ddr-ctrler1-crit {
90 temperature = <95000>;
91 hysteresis = <2000>;
92 type = "critical";
93 };
94 };
95 };
96
97 ddr-controller2 {
98 polling-delay-passive = <1000>;
99 polling-delay = <5000>;
100 thermal-sensors = <&tmu 2>;
101
102 trips {
103 ddr-ctrler2-crit {
104 temperature = <95000>;
105 hysteresis = <2000>;
106 type = "critical";
107 };
108 };
109 };
110
111 ddr-controller3 {
112 polling-delay-passive = <1000>;
113 polling-delay = <5000>;
114 thermal-sensors = <&tmu 3>;
115
116 trips {
117 ddr-ctrler3-crit {
118 temperature = <95000>;
119 hysteresis = <2000>;
120 type = "critical";
121 };
122 };
123 };
124
125 core-cluster1 {
126 polling-delay-passive = <1000>;
127 polling-delay = <5000>;
128 thermal-sensors = <&tmu 4>;
129
130 trips {
131 core_cluster1_alert: core-cluster1-alert {
132 temperature = <85000>;
133 hysteresis = <2000>;
134 type = "passive";
135 };
136
137 core-cluster1-crit {
138 temperature = <95000>;
139 hysteresis = <2000>;
140 type = "critical";
141 };
142 };
143
144 cooling-maps {
145 map0 {
146 trip = <&core_cluster1_alert>;
147 cooling-device =
148 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
149 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
150 };
151 };
152 };
153
154 core-cluster2 {
155 polling-delay-passive = <1000>;
156 polling-delay = <5000>;
157 thermal-sensors = <&tmu 5>;
158
159 trips {
160 core_cluster2_alert: core-cluster2-alert {
161 temperature = <85000>;
162 hysteresis = <2000>;
163 type = "passive";
164 };
165
166 core-cluster2-crit {
167 temperature = <95000>;
168 hysteresis = <2000>;
169 type = "critical";
170 };
171 };
172
173 cooling-maps {
174 map0 {
175 trip = <&core_cluster2_alert>;
176 cooling-device =
177 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
179 };
180 };
181 };
182
183 core-cluster3 {
184 polling-delay-passive = <1000>;
185 polling-delay = <5000>;
186 thermal-sensors = <&tmu 6>;
187
188 trips {
189 core_cluster3_alert: core-cluster3-alert {
190 temperature = <85000>;
191 hysteresis = <2000>;
192 type = "passive";
193 };
194
195 core-cluster3-crit {
196 temperature = <95000>;
197 hysteresis = <2000>;
198 type = "critical";
199 };
200 };
201
202 cooling-maps {
203 map0 {
204 trip = <&core_cluster3_alert>;
205 cooling-device =
206 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
208 };
209 };
210 };
211
212 core-cluster4 {
213 polling-delay-passive = <1000>;
214 polling-delay = <5000>;
215 thermal-sensors = <&tmu 7>;
216
217 trips {
218 core_cluster4_alert: core-cluster4-alert {
219 temperature = <85000>;
220 hysteresis = <2000>;
221 type = "passive";
222 };
223
224 core-cluster4-crit {
225 temperature = <95000>;
226 hysteresis = <2000>;
227 type = "critical";
228 };
229 };
230
231 cooling-maps {
232 map0 {
233 trip = <&core_cluster4_alert>;
234 cooling-device =
235 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
236 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
237 };
238 };
239 };
240 };
241
242 timer: timer {
243 compatible = "arm,armv8-timer";
244 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
245 <1 14 4>, /* Physical Non-Secure PPI, active-low */
246 <1 11 4>, /* Virtual PPI, active-low */
247 <1 10 4>; /* Hypervisor PPI, active-low */
248 };
249
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]250 psci {
251 compatible = "arm,psci-0.2";
252 method = "smc";
253 };
254
255 soc {
256 compatible = "simple-bus";
257 #address-cells = <2>;
258 #size-cells = <2>;
259 ranges;
260 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
261
262 clockgen: clocking@1300000 {
263 compatible = "fsl,ls2080a-clockgen";
264 reg = <0 0x1300000 0 0xa0000>;
265 #clock-cells = <2>;
266 clocks = <&sysclk>;
267 };
268
269 dcfg: dcfg@1e00000 {
270 compatible = "fsl,ls2080a-dcfg", "syscon";
271 reg = <0x0 0x1e00000 0x0 0x10000>;
272 little-endian;
273 };
274
275 sfp: efuse@1e80000 {
276 compatible = "fsl,ls1028a-sfp";
277 reg = <0x0 0x1e80000 0x0 0x10000>;
278 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
279 QORIQ_CLK_PLL_DIV(4)>;
280 clock-names = "sfp";
281 };
282
283 isc: syscon@1f70000 {
284 compatible = "fsl,ls2080a-isc", "syscon";
285 reg = <0x0 0x1f70000 0x0 0x10000>;
286 little-endian;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 ranges = <0x0 0x0 0x1f70000 0x10000>;
290
291 extirq: interrupt-controller@14 {
292 compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
293 #interrupt-cells = <2>;
294 #address-cells = <0>;
295 interrupt-controller;
296 reg = <0x14 4>;
297 interrupt-map =
298 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
299 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
300 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
301 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
302 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
303 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
304 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
305 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
306 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
307 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
308 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
309 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-map-mask = <0xf 0x0>;
311 };
312 };
313
314 tmu: tmu@1f80000 {
315 compatible = "fsl,qoriq-tmu";
316 reg = <0x0 0x1f80000 0x0 0x10000>;
317 interrupts = <0 23 0x4>;
318 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]319 fsl,tmu-calibration =
320 <0x00000000 0x00000026>,
321 <0x00000001 0x0000002d>,
322 <0x00000002 0x00000032>,
323 <0x00000003 0x00000039>,
324 <0x00000004 0x0000003f>,
325 <0x00000005 0x00000046>,
326 <0x00000006 0x0000004d>,
327 <0x00000007 0x00000054>,
328 <0x00000008 0x0000005a>,
329 <0x00000009 0x00000061>,
330 <0x0000000a 0x0000006a>,
331 <0x0000000b 0x00000071>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]332
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]333 <0x00010000 0x00000025>,
334 <0x00010001 0x0000002c>,
335 <0x00010002 0x00000035>,
336 <0x00010003 0x0000003d>,
337 <0x00010004 0x00000045>,
338 <0x00010005 0x0000004e>,
339 <0x00010006 0x00000057>,
340 <0x00010007 0x00000061>,
341 <0x00010008 0x0000006b>,
342 <0x00010009 0x00000076>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]343
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]344 <0x00020000 0x00000029>,
345 <0x00020001 0x00000033>,
346 <0x00020002 0x0000003d>,
347 <0x00020003 0x00000049>,
348 <0x00020004 0x00000056>,
349 <0x00020005 0x00000061>,
350 <0x00020006 0x0000006d>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]351
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]352 <0x00030000 0x00000021>,
353 <0x00030001 0x0000002a>,
354 <0x00030002 0x0000003c>,
355 <0x00030003 0x0000004e>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]356 little-endian;
357 #thermal-sensor-cells = <1>;
358 };
359
360 serial0: serial@21c0500 {
361 compatible = "fsl,ns16550", "ns16550a";
362 reg = <0x0 0x21c0500 0x0 0x100>;
363 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
364 QORIQ_CLK_PLL_DIV(4)>;
365 interrupts = <0 32 0x4>; /* Level high type */
366 };
367
368 serial1: serial@21c0600 {
369 compatible = "fsl,ns16550", "ns16550a";
370 reg = <0x0 0x21c0600 0x0 0x100>;
371 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
372 QORIQ_CLK_PLL_DIV(4)>;
373 interrupts = <0 32 0x4>; /* Level high type */
374 };
375
376 serial2: serial@21d0500 {
377 compatible = "fsl,ns16550", "ns16550a";
378 reg = <0x0 0x21d0500 0x0 0x100>;
379 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
380 QORIQ_CLK_PLL_DIV(4)>;
381 interrupts = <0 33 0x4>; /* Level high type */
382 };
383
384 serial3: serial@21d0600 {
385 compatible = "fsl,ns16550", "ns16550a";
386 reg = <0x0 0x21d0600 0x0 0x100>;
387 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
388 QORIQ_CLK_PLL_DIV(4)>;
389 interrupts = <0 33 0x4>; /* Level high type */
390 };
391
392 cluster1_core0_watchdog: wdt@c000000 {
393 compatible = "arm,sp805", "arm,primecell";
394 reg = <0x0 0xc000000 0x0 0x1000>;
395 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
396 QORIQ_CLK_PLL_DIV(4)>,
397 <&clockgen QORIQ_CLK_PLATFORM_PLL
398 QORIQ_CLK_PLL_DIV(4)>;
399 clock-names = "wdog_clk", "apb_pclk";
400 };
401
402 cluster1_core1_watchdog: wdt@c010000 {
403 compatible = "arm,sp805", "arm,primecell";
404 reg = <0x0 0xc010000 0x0 0x1000>;
405 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
406 QORIQ_CLK_PLL_DIV(4)>,
407 <&clockgen QORIQ_CLK_PLATFORM_PLL
408 QORIQ_CLK_PLL_DIV(4)>;
409 clock-names = "wdog_clk", "apb_pclk";
410 };
411
412 cluster2_core0_watchdog: wdt@c100000 {
413 compatible = "arm,sp805", "arm,primecell";
414 reg = <0x0 0xc100000 0x0 0x1000>;
415 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
416 QORIQ_CLK_PLL_DIV(4)>,
417 <&clockgen QORIQ_CLK_PLATFORM_PLL
418 QORIQ_CLK_PLL_DIV(4)>;
419 clock-names = "wdog_clk", "apb_pclk";
420 };
421
422 cluster2_core1_watchdog: wdt@c110000 {
423 compatible = "arm,sp805", "arm,primecell";
424 reg = <0x0 0xc110000 0x0 0x1000>;
425 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
426 QORIQ_CLK_PLL_DIV(4)>,
427 <&clockgen QORIQ_CLK_PLATFORM_PLL
428 QORIQ_CLK_PLL_DIV(4)>;
429 clock-names = "wdog_clk", "apb_pclk";
430 };
431
432 cluster3_core0_watchdog: wdt@c200000 {
433 compatible = "arm,sp805", "arm,primecell";
434 reg = <0x0 0xc200000 0x0 0x1000>;
435 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
436 QORIQ_CLK_PLL_DIV(4)>,
437 <&clockgen QORIQ_CLK_PLATFORM_PLL
438 QORIQ_CLK_PLL_DIV(4)>;
439 clock-names = "wdog_clk", "apb_pclk";
440 };
441
442 cluster3_core1_watchdog: wdt@c210000 {
443 compatible = "arm,sp805", "arm,primecell";
444 reg = <0x0 0xc210000 0x0 0x1000>;
445 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
446 QORIQ_CLK_PLL_DIV(4)>,
447 <&clockgen QORIQ_CLK_PLATFORM_PLL
448 QORIQ_CLK_PLL_DIV(4)>;
449 clock-names = "wdog_clk", "apb_pclk";
450 };
451
452 cluster4_core0_watchdog: wdt@c300000 {
453 compatible = "arm,sp805", "arm,primecell";
454 reg = <0x0 0xc300000 0x0 0x1000>;
455 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
456 QORIQ_CLK_PLL_DIV(4)>,
457 <&clockgen QORIQ_CLK_PLATFORM_PLL
458 QORIQ_CLK_PLL_DIV(4)>;
459 clock-names = "wdog_clk", "apb_pclk";
460 };
461
462 cluster4_core1_watchdog: wdt@c310000 {
463 compatible = "arm,sp805", "arm,primecell";
464 reg = <0x0 0xc310000 0x0 0x1000>;
465 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
466 QORIQ_CLK_PLL_DIV(4)>,
467 <&clockgen QORIQ_CLK_PLATFORM_PLL
468 QORIQ_CLK_PLL_DIV(4)>;
469 clock-names = "wdog_clk", "apb_pclk";
470 };
471
472 crypto: crypto@8000000 {
473 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
474 fsl,sec-era = <8>;
475 #address-cells = <1>;
476 #size-cells = <1>;
477 ranges = <0x0 0x00 0x8000000 0x100000>;
478 reg = <0x00 0x8000000 0x0 0x100000>;
479 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
480 dma-coherent;
481
482 sec_jr0: jr@10000 {
483 compatible = "fsl,sec-v5.0-job-ring",
484 "fsl,sec-v4.0-job-ring";
485 reg = <0x10000 0x10000>;
486 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
487 };
488
489 sec_jr1: jr@20000 {
490 compatible = "fsl,sec-v5.0-job-ring",
491 "fsl,sec-v4.0-job-ring";
492 reg = <0x20000 0x10000>;
493 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
494 };
495
496 sec_jr2: jr@30000 {
497 compatible = "fsl,sec-v5.0-job-ring",
498 "fsl,sec-v4.0-job-ring";
499 reg = <0x30000 0x10000>;
500 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
501 };
502
503 sec_jr3: jr@40000 {
504 compatible = "fsl,sec-v5.0-job-ring",
505 "fsl,sec-v4.0-job-ring";
506 reg = <0x40000 0x10000>;
507 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
508 };
509 };
510
511 console@8340020 {
512 compatible = "fsl,dpaa2-console";
513 reg = <0x00000000 0x08340020 0 0x2>;
514 };
515
516 ptp-timer@8b95000 {
517 compatible = "fsl,dpaa2-ptp";
518 reg = <0x0 0x8b95000 0x0 0x100>;
519 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
520 QORIQ_CLK_PLL_DIV(2)>;
521 little-endian;
522 fsl,extts-fifo;
523 };
524
525 emdio1: mdio@8b96000 {
526 compatible = "fsl,fman-memac-mdio";
527 reg = <0x0 0x8b96000 0x0 0x1000>;
528 little-endian;
529 #address-cells = <1>;
530 #size-cells = <0>;
531 clock-frequency = <2500000>;
532 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
533 QORIQ_CLK_PLL_DIV(2)>;
534 status = "disabled";
535 };
536
537 emdio2: mdio@8b97000 {
538 compatible = "fsl,fman-memac-mdio";
539 reg = <0x0 0x8b97000 0x0 0x1000>;
540 little-endian;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 clock-frequency = <2500000>;
544 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
545 QORIQ_CLK_PLL_DIV(2)>;
546 status = "disabled";
547 };
548
549 pcs_mdio1: mdio@8c07000 {
550 compatible = "fsl,fman-memac-mdio";
551 reg = <0x0 0x8c07000 0x0 0x1000>;
552 little-endian;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 status = "disabled";
556
557 pcs1: ethernet-phy@0 {
558 reg = <0>;
559 };
560 };
561
562 pcs_mdio2: mdio@8c0b000 {
563 compatible = "fsl,fman-memac-mdio";
564 reg = <0x0 0x8c0b000 0x0 0x1000>;
565 little-endian;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 status = "disabled";
569
570 pcs2: ethernet-phy@0 {
571 reg = <0>;
572 };
573 };
574
575 pcs_mdio3: mdio@8c0f000 {
576 compatible = "fsl,fman-memac-mdio";
577 reg = <0x0 0x8c0f000 0x0 0x1000>;
578 little-endian;
579 #address-cells = <1>;
580 #size-cells = <0>;
581 status = "disabled";
582
583 pcs3: ethernet-phy@0 {
584 reg = <0>;
585 };
586 };
587
588 pcs_mdio4: mdio@8c13000 {
589 compatible = "fsl,fman-memac-mdio";
590 reg = <0x0 0x8c13000 0x0 0x1000>;
591 little-endian;
592 #address-cells = <1>;
593 #size-cells = <0>;
594 status = "disabled";
595
596 pcs4: ethernet-phy@0 {
597 reg = <0>;
598 };
599 };
600
601 pcs_mdio5: mdio@8c17000 {
602 compatible = "fsl,fman-memac-mdio";
603 reg = <0x0 0x8c17000 0x0 0x1000>;
604 little-endian;
605 #address-cells = <1>;
606 #size-cells = <0>;
607 status = "disabled";
608
609 pcs5: ethernet-phy@0 {
610 reg = <0>;
611 };
612 };
613
614 pcs_mdio6: mdio@8c1b000 {
615 compatible = "fsl,fman-memac-mdio";
616 reg = <0x0 0x8c1b000 0x0 0x1000>;
617 little-endian;
618 #address-cells = <1>;
619 #size-cells = <0>;
620 status = "disabled";
621
622 pcs6: ethernet-phy@0 {
623 reg = <0>;
624 };
625 };
626
627 pcs_mdio7: mdio@8c1f000 {
628 compatible = "fsl,fman-memac-mdio";
629 reg = <0x0 0x8c1f000 0x0 0x1000>;
630 little-endian;
631 #address-cells = <1>;
632 #size-cells = <0>;
633 status = "disabled";
634
635 pcs7: ethernet-phy@0 {
636 reg = <0>;
637 };
638 };
639
640 pcs_mdio8: mdio@8c23000 {
641 compatible = "fsl,fman-memac-mdio";
642 reg = <0x0 0x8c23000 0x0 0x1000>;
643 little-endian;
644 #address-cells = <1>;
645 #size-cells = <0>;
646 status = "disabled";
647
648 pcs8: ethernet-phy@0 {
649 reg = <0>;
650 };
651 };
652
653 pcs_mdio9: mdio@8c27000 {
654 compatible = "fsl,fman-memac-mdio";
655 reg = <0x0 0x8c27000 0x0 0x1000>;
656 little-endian;
657 #address-cells = <1>;
658 #size-cells = <0>;
659 status = "disabled";
660
661 pcs9: ethernet-phy@0 {
662 reg = <0>;
663 };
664 };
665
666 pcs_mdio10: mdio@8c2b000 {
667 compatible = "fsl,fman-memac-mdio";
668 reg = <0x0 0x8c2b000 0x0 0x1000>;
669 little-endian;
670 #address-cells = <1>;
671 #size-cells = <0>;
672 status = "disabled";
673
674 pcs10: ethernet-phy@0 {
675 reg = <0>;
676 };
677 };
678
679 pcs_mdio11: mdio@8c2f000 {
680 compatible = "fsl,fman-memac-mdio";
681 reg = <0x0 0x8c2f000 0x0 0x1000>;
682 little-endian;
683 #address-cells = <1>;
684 #size-cells = <0>;
685 status = "disabled";
686
687 pcs11: ethernet-phy@0 {
688 reg = <0>;
689 };
690 };
691
692 pcs_mdio12: mdio@8c33000 {
693 compatible = "fsl,fman-memac-mdio";
694 reg = <0x0 0x8c33000 0x0 0x1000>;
695 little-endian;
696 #address-cells = <1>;
697 #size-cells = <0>;
698 status = "disabled";
699
700 pcs12: ethernet-phy@0 {
701 reg = <0>;
702 };
703 };
704
705 pcs_mdio13: mdio@8c37000 {
706 compatible = "fsl,fman-memac-mdio";
707 reg = <0x0 0x8c37000 0x0 0x1000>;
708 little-endian;
709 #address-cells = <1>;
710 #size-cells = <0>;
711 status = "disabled";
712
713 pcs13: ethernet-phy@0 {
714 reg = <0>;
715 };
716 };
717
718 pcs_mdio14: mdio@8c3b000 {
719 compatible = "fsl,fman-memac-mdio";
720 reg = <0x0 0x8c3b000 0x0 0x1000>;
721 little-endian;
722 #address-cells = <1>;
723 #size-cells = <0>;
724 status = "disabled";
725
726 pcs14: ethernet-phy@0 {
727 reg = <0>;
728 };
729 };
730
731 pcs_mdio15: mdio@8c3f000 {
732 compatible = "fsl,fman-memac-mdio";
733 reg = <0x0 0x8c3f000 0x0 0x1000>;
734 little-endian;
735 #address-cells = <1>;
736 #size-cells = <0>;
737 status = "disabled";
738
739 pcs15: ethernet-phy@0 {
740 reg = <0>;
741 };
742 };
743
744 pcs_mdio16: mdio@8c43000 {
745 compatible = "fsl,fman-memac-mdio";
746 reg = <0x0 0x8c43000 0x0 0x1000>;
747 little-endian;
748 #address-cells = <1>;
749 #size-cells = <0>;
750 status = "disabled";
751
752 pcs16: ethernet-phy@0 {
753 reg = <0>;
754 };
755 };
756
757 fsl_mc: fsl-mc@80c000000 {
758 compatible = "fsl,qoriq-mc";
759 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
760 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
761 msi-parent = <&its>;
762 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
763 dma-coherent;
764 #address-cells = <3>;
765 #size-cells = <1>;
766
767 /*
768 * Region type 0x0 - MC portals
769 * Region type 0x1 - QBMAN portals
770 */
771 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
772 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
773
774 /*
775 * Define the maximum number of MACs present on the SoC.
776 */
777 dpmacs {
778 #address-cells = <1>;
779 #size-cells = <0>;
780
781 dpmac1: ethernet@1 {
782 compatible = "fsl,qoriq-mc-dpmac";
783 reg = <0x1>;
784 pcs-handle = <&pcs1>;
785 };
786
787 dpmac2: ethernet@2 {
788 compatible = "fsl,qoriq-mc-dpmac";
789 reg = <0x2>;
790 pcs-handle = <&pcs2>;
791 };
792
793 dpmac3: ethernet@3 {
794 compatible = "fsl,qoriq-mc-dpmac";
795 reg = <0x3>;
796 pcs-handle = <&pcs3>;
797 };
798
799 dpmac4: ethernet@4 {
800 compatible = "fsl,qoriq-mc-dpmac";
801 reg = <0x4>;
802 pcs-handle = <&pcs4>;
803 };
804
805 dpmac5: ethernet@5 {
806 compatible = "fsl,qoriq-mc-dpmac";
807 reg = <0x5>;
808 pcs-handle = <&pcs5>;
809 };
810
811 dpmac6: ethernet@6 {
812 compatible = "fsl,qoriq-mc-dpmac";
813 reg = <0x6>;
814 pcs-handle = <&pcs6>;
815 };
816
817 dpmac7: ethernet@7 {
818 compatible = "fsl,qoriq-mc-dpmac";
819 reg = <0x7>;
820 pcs-handle = <&pcs7>;
821 };
822
823 dpmac8: ethernet@8 {
824 compatible = "fsl,qoriq-mc-dpmac";
825 reg = <0x8>;
826 pcs-handle = <&pcs8>;
827 };
828
829 dpmac9: ethernet@9 {
830 compatible = "fsl,qoriq-mc-dpmac";
831 reg = <0x9>;
832 pcs-handle = <&pcs9>;
833 };
834
835 dpmac10: ethernet@a {
836 compatible = "fsl,qoriq-mc-dpmac";
837 reg = <0xa>;
838 pcs-handle = <&pcs10>;
839 };
840
841 dpmac11: ethernet@b {
842 compatible = "fsl,qoriq-mc-dpmac";
843 reg = <0xb>;
844 pcs-handle = <&pcs11>;
845 };
846
847 dpmac12: ethernet@c {
848 compatible = "fsl,qoriq-mc-dpmac";
849 reg = <0xc>;
850 pcs-handle = <&pcs12>;
851 };
852
853 dpmac13: ethernet@d {
854 compatible = "fsl,qoriq-mc-dpmac";
855 reg = <0xd>;
856 pcs-handle = <&pcs13>;
857 };
858
859 dpmac14: ethernet@e {
860 compatible = "fsl,qoriq-mc-dpmac";
861 reg = <0xe>;
862 pcs-handle = <&pcs14>;
863 };
864
865 dpmac15: ethernet@f {
866 compatible = "fsl,qoriq-mc-dpmac";
867 reg = <0xf>;
868 pcs-handle = <&pcs15>;
869 };
870
871 dpmac16: ethernet@10 {
872 compatible = "fsl,qoriq-mc-dpmac";
873 reg = <0x10>;
874 pcs-handle = <&pcs16>;
875 };
876 };
877 };
878
879 smmu: iommu@5000000 {
880 compatible = "arm,mmu-500";
881 reg = <0 0x5000000 0 0x800000>;
882 #global-interrupts = <12>;
883 #iommu-cells = <1>;
884 stream-match-mask = <0x7C00>;
885 dma-coherent;
886 interrupts = <0 13 4>, /* global secure fault */
887 <0 14 4>, /* combined secure interrupt */
888 <0 15 4>, /* global non-secure fault */
889 <0 16 4>, /* combined non-secure interrupt */
890 /* performance counter interrupts 0-7 */
891 <0 211 4>, <0 212 4>,
892 <0 213 4>, <0 214 4>,
893 <0 215 4>, <0 216 4>,
894 <0 217 4>, <0 218 4>,
895 /* per context interrupt, 64 interrupts */
896 <0 146 4>, <0 147 4>,
897 <0 148 4>, <0 149 4>,
898 <0 150 4>, <0 151 4>,
899 <0 152 4>, <0 153 4>,
900 <0 154 4>, <0 155 4>,
901 <0 156 4>, <0 157 4>,
902 <0 158 4>, <0 159 4>,
903 <0 160 4>, <0 161 4>,
904 <0 162 4>, <0 163 4>,
905 <0 164 4>, <0 165 4>,
906 <0 166 4>, <0 167 4>,
907 <0 168 4>, <0 169 4>,
908 <0 170 4>, <0 171 4>,
909 <0 172 4>, <0 173 4>,
910 <0 174 4>, <0 175 4>,
911 <0 176 4>, <0 177 4>,
912 <0 178 4>, <0 179 4>,
913 <0 180 4>, <0 181 4>,
914 <0 182 4>, <0 183 4>,
915 <0 184 4>, <0 185 4>,
916 <0 186 4>, <0 187 4>,
917 <0 188 4>, <0 189 4>,
918 <0 190 4>, <0 191 4>,
919 <0 192 4>, <0 193 4>,
920 <0 194 4>, <0 195 4>,
921 <0 196 4>, <0 197 4>,
922 <0 198 4>, <0 199 4>,
923 <0 200 4>, <0 201 4>,
924 <0 202 4>, <0 203 4>,
925 <0 204 4>, <0 205 4>,
926 <0 206 4>, <0 207 4>,
927 <0 208 4>, <0 209 4>;
928 };
929
930 dspi: spi@2100000 {
931 status = "disabled";
932 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
933 #address-cells = <1>;
934 #size-cells = <0>;
935 reg = <0x0 0x2100000 0x0 0x10000>;
936 interrupts = <0 26 0x4>; /* Level high type */
937 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
938 QORIQ_CLK_PLL_DIV(4)>;
939 clock-names = "dspi";
940 spi-num-chipselects = <5>;
941 };
942
943 esdhc: esdhc@2140000 {
944 status = "disabled";
945 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
946 reg = <0x0 0x2140000 0x0 0x10000>;
947 interrupts = <0 28 0x4>; /* Level high type */
948 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
949 QORIQ_CLK_PLL_DIV(2)>;
950 voltage-ranges = <1800 1800 3300 3300>;
951 sdhci,auto-cmd12;
952 little-endian;
953 bus-width = <4>;
954 };
955
956 gpio0: gpio@2300000 {
957 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
958 reg = <0x0 0x2300000 0x0 0x10000>;
959 interrupts = <0 36 0x4>; /* Level high type */
960 gpio-controller;
961 little-endian;
962 #gpio-cells = <2>;
963 interrupt-controller;
964 #interrupt-cells = <2>;
965 };
966
967 gpio1: gpio@2310000 {
968 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
969 reg = <0x0 0x2310000 0x0 0x10000>;
970 interrupts = <0 36 0x4>; /* Level high type */
971 gpio-controller;
972 little-endian;
973 #gpio-cells = <2>;
974 interrupt-controller;
975 #interrupt-cells = <2>;
976 };
977
978 gpio2: gpio@2320000 {
979 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
980 reg = <0x0 0x2320000 0x0 0x10000>;
981 interrupts = <0 37 0x4>; /* Level high type */
982 gpio-controller;
983 little-endian;
984 #gpio-cells = <2>;
985 interrupt-controller;
986 #interrupt-cells = <2>;
987 };
988
989 gpio3: gpio@2330000 {
990 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
991 reg = <0x0 0x2330000 0x0 0x10000>;
992 interrupts = <0 37 0x4>; /* Level high type */
993 gpio-controller;
994 little-endian;
995 #gpio-cells = <2>;
996 interrupt-controller;
997 #interrupt-cells = <2>;
998 };
999
1000 i2c0: i2c@2000000 {
1001 status = "disabled";
1002 compatible = "fsl,vf610-i2c";
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 reg = <0x0 0x2000000 0x0 0x10000>;
1006 interrupts = <0 34 0x4>; /* Level high type */
1007 clock-names = "i2c";
1008 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1009 QORIQ_CLK_PLL_DIV(4)>;
1010 };
1011
1012 i2c1: i2c@2010000 {
1013 status = "disabled";
1014 compatible = "fsl,vf610-i2c";
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 reg = <0x0 0x2010000 0x0 0x10000>;
1018 interrupts = <0 34 0x4>; /* Level high type */
1019 clock-names = "i2c";
1020 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1021 QORIQ_CLK_PLL_DIV(4)>;
1022 };
1023
1024 i2c2: i2c@2020000 {
1025 status = "disabled";
1026 compatible = "fsl,vf610-i2c";
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1029 reg = <0x0 0x2020000 0x0 0x10000>;
1030 interrupts = <0 35 0x4>; /* Level high type */
1031 clock-names = "i2c";
1032 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1033 QORIQ_CLK_PLL_DIV(4)>;
1034 };
1035
1036 i2c3: i2c@2030000 {
1037 status = "disabled";
1038 compatible = "fsl,vf610-i2c";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1041 reg = <0x0 0x2030000 0x0 0x10000>;
1042 interrupts = <0 35 0x4>; /* Level high type */
1043 clock-names = "i2c";
1044 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1045 QORIQ_CLK_PLL_DIV(4)>;
1046 };
1047
1048 ifc: memory-controller@2240000 {
1049 compatible = "fsl,ifc";
1050 reg = <0x0 0x2240000 0x0 0x20000>;
1051 interrupts = <0 21 0x4>; /* Level high type */
1052 little-endian;
1053 #address-cells = <2>;
1054 #size-cells = <1>;
1055
1056 ranges = <0 0 0x5 0x80000000 0x08000000
1057 2 0 0x5 0x30000000 0x00010000
1058 3 0 0x5 0x20000000 0x00010000>;
1059 };
1060
1061 qspi: spi@20c0000 {
1062 compatible = "fsl,ls2080a-qspi";
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 reg = <0x0 0x20c0000 0x0 0x10000>,
1066 <0x0 0x20000000 0x0 0x10000000>;
1067 reg-names = "QuadSPI", "QuadSPI-memory";
1068 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1070 QORIQ_CLK_PLL_DIV(4)>,
1071 <&clockgen QORIQ_CLK_PLATFORM_PLL
1072 QORIQ_CLK_PLL_DIV(4)>;
1073 clock-names = "qspi_en", "qspi";
1074 status = "disabled";
1075 };
1076
1077 pcie1: pcie@3400000 {
1078 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1079 reg-names = "regs", "config";
1080 interrupts = <0 108 0x4>; /* Level high type */
1081 interrupt-names = "intr";
1082 #address-cells = <3>;
1083 #size-cells = <2>;
1084 device_type = "pci";
1085 dma-coherent;
1086 num-viewport = <6>;
1087 bus-range = <0x0 0xff>;
1088 msi-parent = <&its>;
1089 #interrupt-cells = <1>;
1090 interrupt-map-mask = <0 0 0 7>;
1091 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1092 <0000 0 0 2 &gic 0 0 0 110 4>,
1093 <0000 0 0 3 &gic 0 0 0 111 4>,
1094 <0000 0 0 4 &gic 0 0 0 112 4>;
1095 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1096 status = "disabled";
1097 };
1098
1099 pcie2: pcie@3500000 {
1100 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1101 reg-names = "regs", "config";
1102 interrupts = <0 113 0x4>; /* Level high type */
1103 interrupt-names = "intr";
1104 #address-cells = <3>;
1105 #size-cells = <2>;
1106 device_type = "pci";
1107 dma-coherent;
1108 num-viewport = <6>;
1109 bus-range = <0x0 0xff>;
1110 msi-parent = <&its>;
1111 #interrupt-cells = <1>;
1112 interrupt-map-mask = <0 0 0 7>;
1113 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1114 <0000 0 0 2 &gic 0 0 0 115 4>,
1115 <0000 0 0 3 &gic 0 0 0 116 4>,
1116 <0000 0 0 4 &gic 0 0 0 117 4>;
1117 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1118 status = "disabled";
1119 };
1120
1121 pcie3: pcie@3600000 {
1122 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1123 reg-names = "regs", "config";
1124 interrupts = <0 118 0x4>; /* Level high type */
1125 interrupt-names = "intr";
1126 #address-cells = <3>;
1127 #size-cells = <2>;
1128 device_type = "pci";
1129 dma-coherent;
1130 num-viewport = <256>;
1131 bus-range = <0x0 0xff>;
1132 msi-parent = <&its>;
1133 #interrupt-cells = <1>;
1134 interrupt-map-mask = <0 0 0 7>;
1135 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1136 <0000 0 0 2 &gic 0 0 0 120 4>,
1137 <0000 0 0 3 &gic 0 0 0 121 4>,
1138 <0000 0 0 4 &gic 0 0 0 122 4>;
1139 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1140 status = "disabled";
1141 };
1142
1143 pcie4: pcie@3700000 {
1144 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1145 reg-names = "regs", "config";
1146 interrupts = <0 123 0x4>; /* Level high type */
1147 interrupt-names = "intr";
1148 #address-cells = <3>;
1149 #size-cells = <2>;
1150 device_type = "pci";
1151 dma-coherent;
1152 num-viewport = <6>;
1153 bus-range = <0x0 0xff>;
1154 msi-parent = <&its>;
1155 #interrupt-cells = <1>;
1156 interrupt-map-mask = <0 0 0 7>;
1157 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1158 <0000 0 0 2 &gic 0 0 0 125 4>,
1159 <0000 0 0 3 &gic 0 0 0 126 4>,
1160 <0000 0 0 4 &gic 0 0 0 127 4>;
1161 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1162 status = "disabled";
1163 };
1164
1165 sata0: sata@3200000 {
1166 status = "disabled";
1167 compatible = "fsl,ls2080a-ahci";
1168 reg = <0x0 0x3200000 0x0 0x10000>;
1169 interrupts = <0 133 0x4>; /* Level high type */
1170 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1171 QORIQ_CLK_PLL_DIV(4)>;
1172 dma-coherent;
1173 };
1174
1175 sata1: sata@3210000 {
1176 status = "disabled";
1177 compatible = "fsl,ls2080a-ahci";
1178 reg = <0x0 0x3210000 0x0 0x10000>;
1179 interrupts = <0 136 0x4>; /* Level high type */
1180 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1181 QORIQ_CLK_PLL_DIV(4)>;
1182 dma-coherent;
1183 };
1184
1185 bus: bus {
1186 #address-cells = <2>;
1187 #size-cells = <2>;
1188 compatible = "simple-bus";
1189 ranges;
1190 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
1191
1192 usb0: usb@3100000 {
1193 compatible = "snps,dwc3";
1194 reg = <0x0 0x3100000 0x0 0x10000>;
1195 interrupts = <0 80 0x4>; /* Level high type */
1196 dr_mode = "host";
1197 snps,quirk-frame-length-adjustment = <0x20>;
1198 snps,dis_rxdet_inp3_quirk;
1199 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1200 status = "disabled";
1201 };
1202
1203 usb1: usb@3110000 {
1204 compatible = "snps,dwc3";
1205 reg = <0x0 0x3110000 0x0 0x10000>;
1206 interrupts = <0 81 0x4>; /* Level high type */
1207 dr_mode = "host";
1208 snps,quirk-frame-length-adjustment = <0x20>;
1209 snps,dis_rxdet_inp3_quirk;
1210 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1211 status = "disabled";
1212 };
1213 };
1214
1215 ccn@4000000 {
1216 compatible = "arm,ccn-504";
1217 reg = <0x0 0x04000000 0x0 0x01000000>;
1218 interrupts = <0 12 4>;
1219 };
1220
1221 rcpm: power-controller@1e34040 {
1222 compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1223 reg = <0x0 0x1e34040 0x0 0x18>;
1224 #fsl,rcpm-wakeup-cells = <6>;
1225 little-endian;
1226 };
1227
1228 ftm_alarm0: timer@2800000 {
1229 compatible = "fsl,ls208xa-ftm-alarm";
1230 reg = <0x0 0x2800000 0x0 0x10000>;
1231 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1232 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1233 };
1234 };
1235
1236 ddr1: memory-controller@1080000 {
1237 compatible = "fsl,qoriq-memory-controller";
1238 reg = <0x0 0x1080000 0x0 0x1000>;
1239 interrupts = <0 17 0x4>;
1240 little-endian;
1241 };
1242
1243 ddr2: memory-controller@1090000 {
1244 compatible = "fsl,qoriq-memory-controller";
1245 reg = <0x0 0x1090000 0x0 0x1000>;
1246 interrupts = <0 18 0x4>;
1247 little-endian;
1248 };
1249
1250 firmware {
1251 optee {
1252 compatible = "linaro,optee-tz";
1253 method = "smc";
1254 };
1255 };
1256};