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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm64 / freescale / fsl-ls208xa.dtsi
blob: 717288bbdb8b633f5ee286acdd2fc34fcabe3d50 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017-2020 NXP
7 *
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 *
10 */
11
12#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13#include <dt-bindings/thermal/thermal.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16/ {
17 compatible = "fsl,ls2080a";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 crypto = &crypto;
24 rtc1 = &ftm_alarm0;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 serial2 = &serial2;
28 serial3 = &serial3;
29 };
30
31 cpu: cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 };
35
36 memory@80000000 {
37 device_type = "memory";
38 reg = <0x00000000 0x80000000 0 0x80000000>;
39 /* DRAM space - 1, size : 2 GB DRAM */
40 };
41
42 sysclk: sysclk {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <100000000>;
46 clock-output-names = "sysclk";
47 };
48
49 gic: interrupt-controller@6000000 {
50 compatible = "arm,gic-v3";
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
56 #interrupt-cells = <3>;
57 #address-cells = <2>;
58 #size-cells = <2>;
59 ranges;
60 interrupt-controller;
61 interrupts = <1 9 0x4>;
62
63 its: msi-controller@6020000 {
64 compatible = "arm,gic-v3-its";
65 msi-controller;
66 reg = <0x0 0x6020000 0 0x20000>;
67 };
68 };
69
70 rstcr: syscon@1e60000 {
71 compatible = "fsl,ls2080a-rstcr", "syscon";
72 reg = <0x0 0x1e60000 0x0 0x4>;
73 };
74
75 reboot {
76 compatible = "syscon-reboot";
77 regmap = <&rstcr>;
78 offset = <0x0>;
79 mask = <0x2>;
80 };
81
82 thermal-zones {
83 ddr-controller1 {
84 polling-delay-passive = <1000>;
85 polling-delay = <5000>;
86 thermal-sensors = <&tmu 1>;
87
88 trips {
89 ddr-ctrler1-crit {
90 temperature = <95000>;
91 hysteresis = <2000>;
92 type = "critical";
93 };
94 };
95 };
96
97 ddr-controller2 {
98 polling-delay-passive = <1000>;
99 polling-delay = <5000>;
100 thermal-sensors = <&tmu 2>;
101
102 trips {
103 ddr-ctrler2-crit {
104 temperature = <95000>;
105 hysteresis = <2000>;
106 type = "critical";
107 };
108 };
109 };
110
111 ddr-controller3 {
112 polling-delay-passive = <1000>;
113 polling-delay = <5000>;
114 thermal-sensors = <&tmu 3>;
115
116 trips {
117 ddr-ctrler3-crit {
118 temperature = <95000>;
119 hysteresis = <2000>;
120 type = "critical";
121 };
122 };
123 };
124
125 core-cluster1 {
126 polling-delay-passive = <1000>;
127 polling-delay = <5000>;
128 thermal-sensors = <&tmu 4>;
129
130 trips {
131 core_cluster1_alert: core-cluster1-alert {
132 temperature = <85000>;
133 hysteresis = <2000>;
134 type = "passive";
135 };
136
137 core-cluster1-crit {
138 temperature = <95000>;
139 hysteresis = <2000>;
140 type = "critical";
141 };
142 };
143
144 cooling-maps {
145 map0 {
146 trip = <&core_cluster1_alert>;
147 cooling-device =
148 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
149 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
150 };
151 };
152 };
153
154 core-cluster2 {
155 polling-delay-passive = <1000>;
156 polling-delay = <5000>;
157 thermal-sensors = <&tmu 5>;
158
159 trips {
160 core_cluster2_alert: core-cluster2-alert {
161 temperature = <85000>;
162 hysteresis = <2000>;
163 type = "passive";
164 };
165
166 core-cluster2-crit {
167 temperature = <95000>;
168 hysteresis = <2000>;
169 type = "critical";
170 };
171 };
172
173 cooling-maps {
174 map0 {
175 trip = <&core_cluster2_alert>;
176 cooling-device =
177 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
179 };
180 };
181 };
182
183 core-cluster3 {
184 polling-delay-passive = <1000>;
185 polling-delay = <5000>;
186 thermal-sensors = <&tmu 6>;
187
188 trips {
189 core_cluster3_alert: core-cluster3-alert {
190 temperature = <85000>;
191 hysteresis = <2000>;
192 type = "passive";
193 };
194
195 core-cluster3-crit {
196 temperature = <95000>;
197 hysteresis = <2000>;
198 type = "critical";
199 };
200 };
201
202 cooling-maps {
203 map0 {
204 trip = <&core_cluster3_alert>;
205 cooling-device =
206 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
208 };
209 };
210 };
211
212 core-cluster4 {
213 polling-delay-passive = <1000>;
214 polling-delay = <5000>;
215 thermal-sensors = <&tmu 7>;
216
217 trips {
218 core_cluster4_alert: core-cluster4-alert {
219 temperature = <85000>;
220 hysteresis = <2000>;
221 type = "passive";
222 };
223
224 core-cluster4-crit {
225 temperature = <95000>;
226 hysteresis = <2000>;
227 type = "critical";
228 };
229 };
230
231 cooling-maps {
232 map0 {
233 trip = <&core_cluster4_alert>;
234 cooling-device =
235 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
236 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
237 };
238 };
239 };
240 };
241
242 timer: timer {
243 compatible = "arm,armv8-timer";
244 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
245 <1 14 4>, /* Physical Non-Secure PPI, active-low */
246 <1 11 4>, /* Virtual PPI, active-low */
247 <1 10 4>; /* Hypervisor PPI, active-low */
248 };
249
250 pmu {
251 compatible = "arm,armv8-pmuv3";
252 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
253 };
254
255 psci {
256 compatible = "arm,psci-0.2";
257 method = "smc";
258 };
259
260 soc {
261 compatible = "simple-bus";
262 #address-cells = <2>;
263 #size-cells = <2>;
264 ranges;
265 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
266
267 clockgen: clocking@1300000 {
268 compatible = "fsl,ls2080a-clockgen";
269 reg = <0 0x1300000 0 0xa0000>;
270 #clock-cells = <2>;
271 clocks = <&sysclk>;
272 };
273
274 dcfg: dcfg@1e00000 {
275 compatible = "fsl,ls2080a-dcfg", "syscon";
276 reg = <0x0 0x1e00000 0x0 0x10000>;
277 little-endian;
278 };
279
280 sfp: efuse@1e80000 {
281 compatible = "fsl,ls1028a-sfp";
282 reg = <0x0 0x1e80000 0x0 0x10000>;
283 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
284 QORIQ_CLK_PLL_DIV(4)>;
285 clock-names = "sfp";
286 };
287
288 isc: syscon@1f70000 {
289 compatible = "fsl,ls2080a-isc", "syscon";
290 reg = <0x0 0x1f70000 0x0 0x10000>;
291 little-endian;
292 #address-cells = <1>;
293 #size-cells = <1>;
294 ranges = <0x0 0x0 0x1f70000 0x10000>;
295
296 extirq: interrupt-controller@14 {
297 compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
298 #interrupt-cells = <2>;
299 #address-cells = <0>;
300 interrupt-controller;
301 reg = <0x14 4>;
302 interrupt-map =
303 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
304 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
305 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
306 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
307 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
308 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
309 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
310 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
311 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
312 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
313 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
314 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
315 interrupt-map-mask = <0xf 0x0>;
316 };
317 };
318
319 tmu: tmu@1f80000 {
320 compatible = "fsl,qoriq-tmu";
321 reg = <0x0 0x1f80000 0x0 0x10000>;
322 interrupts = <0 23 0x4>;
323 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
324 fsl,tmu-calibration = <0x00000000 0x00000026
325 0x00000001 0x0000002d
326 0x00000002 0x00000032
327 0x00000003 0x00000039
328 0x00000004 0x0000003f
329 0x00000005 0x00000046
330 0x00000006 0x0000004d
331 0x00000007 0x00000054
332 0x00000008 0x0000005a
333 0x00000009 0x00000061
334 0x0000000a 0x0000006a
335 0x0000000b 0x00000071
336
337 0x00010000 0x00000025
338 0x00010001 0x0000002c
339 0x00010002 0x00000035
340 0x00010003 0x0000003d
341 0x00010004 0x00000045
342 0x00010005 0x0000004e
343 0x00010006 0x00000057
344 0x00010007 0x00000061
345 0x00010008 0x0000006b
346 0x00010009 0x00000076
347
348 0x00020000 0x00000029
349 0x00020001 0x00000033
350 0x00020002 0x0000003d
351 0x00020003 0x00000049
352 0x00020004 0x00000056
353 0x00020005 0x00000061
354 0x00020006 0x0000006d
355
356 0x00030000 0x00000021
357 0x00030001 0x0000002a
358 0x00030002 0x0000003c
359 0x00030003 0x0000004e>;
360 little-endian;
361 #thermal-sensor-cells = <1>;
362 };
363
364 serial0: serial@21c0500 {
365 compatible = "fsl,ns16550", "ns16550a";
366 reg = <0x0 0x21c0500 0x0 0x100>;
367 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
368 QORIQ_CLK_PLL_DIV(4)>;
369 interrupts = <0 32 0x4>; /* Level high type */
370 };
371
372 serial1: serial@21c0600 {
373 compatible = "fsl,ns16550", "ns16550a";
374 reg = <0x0 0x21c0600 0x0 0x100>;
375 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
376 QORIQ_CLK_PLL_DIV(4)>;
377 interrupts = <0 32 0x4>; /* Level high type */
378 };
379
380 serial2: serial@21d0500 {
381 compatible = "fsl,ns16550", "ns16550a";
382 reg = <0x0 0x21d0500 0x0 0x100>;
383 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
384 QORIQ_CLK_PLL_DIV(4)>;
385 interrupts = <0 33 0x4>; /* Level high type */
386 };
387
388 serial3: serial@21d0600 {
389 compatible = "fsl,ns16550", "ns16550a";
390 reg = <0x0 0x21d0600 0x0 0x100>;
391 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
392 QORIQ_CLK_PLL_DIV(4)>;
393 interrupts = <0 33 0x4>; /* Level high type */
394 };
395
396 cluster1_core0_watchdog: wdt@c000000 {
397 compatible = "arm,sp805", "arm,primecell";
398 reg = <0x0 0xc000000 0x0 0x1000>;
399 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
400 QORIQ_CLK_PLL_DIV(4)>,
401 <&clockgen QORIQ_CLK_PLATFORM_PLL
402 QORIQ_CLK_PLL_DIV(4)>;
403 clock-names = "wdog_clk", "apb_pclk";
404 };
405
406 cluster1_core1_watchdog: wdt@c010000 {
407 compatible = "arm,sp805", "arm,primecell";
408 reg = <0x0 0xc010000 0x0 0x1000>;
409 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
410 QORIQ_CLK_PLL_DIV(4)>,
411 <&clockgen QORIQ_CLK_PLATFORM_PLL
412 QORIQ_CLK_PLL_DIV(4)>;
413 clock-names = "wdog_clk", "apb_pclk";
414 };
415
416 cluster2_core0_watchdog: wdt@c100000 {
417 compatible = "arm,sp805", "arm,primecell";
418 reg = <0x0 0xc100000 0x0 0x1000>;
419 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
420 QORIQ_CLK_PLL_DIV(4)>,
421 <&clockgen QORIQ_CLK_PLATFORM_PLL
422 QORIQ_CLK_PLL_DIV(4)>;
423 clock-names = "wdog_clk", "apb_pclk";
424 };
425
426 cluster2_core1_watchdog: wdt@c110000 {
427 compatible = "arm,sp805", "arm,primecell";
428 reg = <0x0 0xc110000 0x0 0x1000>;
429 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
430 QORIQ_CLK_PLL_DIV(4)>,
431 <&clockgen QORIQ_CLK_PLATFORM_PLL
432 QORIQ_CLK_PLL_DIV(4)>;
433 clock-names = "wdog_clk", "apb_pclk";
434 };
435
436 cluster3_core0_watchdog: wdt@c200000 {
437 compatible = "arm,sp805", "arm,primecell";
438 reg = <0x0 0xc200000 0x0 0x1000>;
439 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
440 QORIQ_CLK_PLL_DIV(4)>,
441 <&clockgen QORIQ_CLK_PLATFORM_PLL
442 QORIQ_CLK_PLL_DIV(4)>;
443 clock-names = "wdog_clk", "apb_pclk";
444 };
445
446 cluster3_core1_watchdog: wdt@c210000 {
447 compatible = "arm,sp805", "arm,primecell";
448 reg = <0x0 0xc210000 0x0 0x1000>;
449 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
450 QORIQ_CLK_PLL_DIV(4)>,
451 <&clockgen QORIQ_CLK_PLATFORM_PLL
452 QORIQ_CLK_PLL_DIV(4)>;
453 clock-names = "wdog_clk", "apb_pclk";
454 };
455
456 cluster4_core0_watchdog: wdt@c300000 {
457 compatible = "arm,sp805", "arm,primecell";
458 reg = <0x0 0xc300000 0x0 0x1000>;
459 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
460 QORIQ_CLK_PLL_DIV(4)>,
461 <&clockgen QORIQ_CLK_PLATFORM_PLL
462 QORIQ_CLK_PLL_DIV(4)>;
463 clock-names = "wdog_clk", "apb_pclk";
464 };
465
466 cluster4_core1_watchdog: wdt@c310000 {
467 compatible = "arm,sp805", "arm,primecell";
468 reg = <0x0 0xc310000 0x0 0x1000>;
469 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
470 QORIQ_CLK_PLL_DIV(4)>,
471 <&clockgen QORIQ_CLK_PLATFORM_PLL
472 QORIQ_CLK_PLL_DIV(4)>;
473 clock-names = "wdog_clk", "apb_pclk";
474 };
475
476 crypto: crypto@8000000 {
477 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
478 fsl,sec-era = <8>;
479 #address-cells = <1>;
480 #size-cells = <1>;
481 ranges = <0x0 0x00 0x8000000 0x100000>;
482 reg = <0x00 0x8000000 0x0 0x100000>;
483 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
484 dma-coherent;
485
486 sec_jr0: jr@10000 {
487 compatible = "fsl,sec-v5.0-job-ring",
488 "fsl,sec-v4.0-job-ring";
489 reg = <0x10000 0x10000>;
490 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
491 };
492
493 sec_jr1: jr@20000 {
494 compatible = "fsl,sec-v5.0-job-ring",
495 "fsl,sec-v4.0-job-ring";
496 reg = <0x20000 0x10000>;
497 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
498 };
499
500 sec_jr2: jr@30000 {
501 compatible = "fsl,sec-v5.0-job-ring",
502 "fsl,sec-v4.0-job-ring";
503 reg = <0x30000 0x10000>;
504 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
505 };
506
507 sec_jr3: jr@40000 {
508 compatible = "fsl,sec-v5.0-job-ring",
509 "fsl,sec-v4.0-job-ring";
510 reg = <0x40000 0x10000>;
511 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
512 };
513 };
514
515 console@8340020 {
516 compatible = "fsl,dpaa2-console";
517 reg = <0x00000000 0x08340020 0 0x2>;
518 };
519
520 ptp-timer@8b95000 {
521 compatible = "fsl,dpaa2-ptp";
522 reg = <0x0 0x8b95000 0x0 0x100>;
523 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
524 QORIQ_CLK_PLL_DIV(2)>;
525 little-endian;
526 fsl,extts-fifo;
527 };
528
529 emdio1: mdio@8b96000 {
530 compatible = "fsl,fman-memac-mdio";
531 reg = <0x0 0x8b96000 0x0 0x1000>;
532 little-endian;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 clock-frequency = <2500000>;
536 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
537 QORIQ_CLK_PLL_DIV(2)>;
538 status = "disabled";
539 };
540
541 emdio2: mdio@8b97000 {
542 compatible = "fsl,fman-memac-mdio";
543 reg = <0x0 0x8b97000 0x0 0x1000>;
544 little-endian;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 clock-frequency = <2500000>;
548 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
549 QORIQ_CLK_PLL_DIV(2)>;
550 status = "disabled";
551 };
552
553 pcs_mdio1: mdio@8c07000 {
554 compatible = "fsl,fman-memac-mdio";
555 reg = <0x0 0x8c07000 0x0 0x1000>;
556 little-endian;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 status = "disabled";
560
561 pcs1: ethernet-phy@0 {
562 reg = <0>;
563 };
564 };
565
566 pcs_mdio2: mdio@8c0b000 {
567 compatible = "fsl,fman-memac-mdio";
568 reg = <0x0 0x8c0b000 0x0 0x1000>;
569 little-endian;
570 #address-cells = <1>;
571 #size-cells = <0>;
572 status = "disabled";
573
574 pcs2: ethernet-phy@0 {
575 reg = <0>;
576 };
577 };
578
579 pcs_mdio3: mdio@8c0f000 {
580 compatible = "fsl,fman-memac-mdio";
581 reg = <0x0 0x8c0f000 0x0 0x1000>;
582 little-endian;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 status = "disabled";
586
587 pcs3: ethernet-phy@0 {
588 reg = <0>;
589 };
590 };
591
592 pcs_mdio4: mdio@8c13000 {
593 compatible = "fsl,fman-memac-mdio";
594 reg = <0x0 0x8c13000 0x0 0x1000>;
595 little-endian;
596 #address-cells = <1>;
597 #size-cells = <0>;
598 status = "disabled";
599
600 pcs4: ethernet-phy@0 {
601 reg = <0>;
602 };
603 };
604
605 pcs_mdio5: mdio@8c17000 {
606 compatible = "fsl,fman-memac-mdio";
607 reg = <0x0 0x8c17000 0x0 0x1000>;
608 little-endian;
609 #address-cells = <1>;
610 #size-cells = <0>;
611 status = "disabled";
612
613 pcs5: ethernet-phy@0 {
614 reg = <0>;
615 };
616 };
617
618 pcs_mdio6: mdio@8c1b000 {
619 compatible = "fsl,fman-memac-mdio";
620 reg = <0x0 0x8c1b000 0x0 0x1000>;
621 little-endian;
622 #address-cells = <1>;
623 #size-cells = <0>;
624 status = "disabled";
625
626 pcs6: ethernet-phy@0 {
627 reg = <0>;
628 };
629 };
630
631 pcs_mdio7: mdio@8c1f000 {
632 compatible = "fsl,fman-memac-mdio";
633 reg = <0x0 0x8c1f000 0x0 0x1000>;
634 little-endian;
635 #address-cells = <1>;
636 #size-cells = <0>;
637 status = "disabled";
638
639 pcs7: ethernet-phy@0 {
640 reg = <0>;
641 };
642 };
643
644 pcs_mdio8: mdio@8c23000 {
645 compatible = "fsl,fman-memac-mdio";
646 reg = <0x0 0x8c23000 0x0 0x1000>;
647 little-endian;
648 #address-cells = <1>;
649 #size-cells = <0>;
650 status = "disabled";
651
652 pcs8: ethernet-phy@0 {
653 reg = <0>;
654 };
655 };
656
657 pcs_mdio9: mdio@8c27000 {
658 compatible = "fsl,fman-memac-mdio";
659 reg = <0x0 0x8c27000 0x0 0x1000>;
660 little-endian;
661 #address-cells = <1>;
662 #size-cells = <0>;
663 status = "disabled";
664
665 pcs9: ethernet-phy@0 {
666 reg = <0>;
667 };
668 };
669
670 pcs_mdio10: mdio@8c2b000 {
671 compatible = "fsl,fman-memac-mdio";
672 reg = <0x0 0x8c2b000 0x0 0x1000>;
673 little-endian;
674 #address-cells = <1>;
675 #size-cells = <0>;
676 status = "disabled";
677
678 pcs10: ethernet-phy@0 {
679 reg = <0>;
680 };
681 };
682
683 pcs_mdio11: mdio@8c2f000 {
684 compatible = "fsl,fman-memac-mdio";
685 reg = <0x0 0x8c2f000 0x0 0x1000>;
686 little-endian;
687 #address-cells = <1>;
688 #size-cells = <0>;
689 status = "disabled";
690
691 pcs11: ethernet-phy@0 {
692 reg = <0>;
693 };
694 };
695
696 pcs_mdio12: mdio@8c33000 {
697 compatible = "fsl,fman-memac-mdio";
698 reg = <0x0 0x8c33000 0x0 0x1000>;
699 little-endian;
700 #address-cells = <1>;
701 #size-cells = <0>;
702 status = "disabled";
703
704 pcs12: ethernet-phy@0 {
705 reg = <0>;
706 };
707 };
708
709 pcs_mdio13: mdio@8c37000 {
710 compatible = "fsl,fman-memac-mdio";
711 reg = <0x0 0x8c37000 0x0 0x1000>;
712 little-endian;
713 #address-cells = <1>;
714 #size-cells = <0>;
715 status = "disabled";
716
717 pcs13: ethernet-phy@0 {
718 reg = <0>;
719 };
720 };
721
722 pcs_mdio14: mdio@8c3b000 {
723 compatible = "fsl,fman-memac-mdio";
724 reg = <0x0 0x8c3b000 0x0 0x1000>;
725 little-endian;
726 #address-cells = <1>;
727 #size-cells = <0>;
728 status = "disabled";
729
730 pcs14: ethernet-phy@0 {
731 reg = <0>;
732 };
733 };
734
735 pcs_mdio15: mdio@8c3f000 {
736 compatible = "fsl,fman-memac-mdio";
737 reg = <0x0 0x8c3f000 0x0 0x1000>;
738 little-endian;
739 #address-cells = <1>;
740 #size-cells = <0>;
741 status = "disabled";
742
743 pcs15: ethernet-phy@0 {
744 reg = <0>;
745 };
746 };
747
748 pcs_mdio16: mdio@8c43000 {
749 compatible = "fsl,fman-memac-mdio";
750 reg = <0x0 0x8c43000 0x0 0x1000>;
751 little-endian;
752 #address-cells = <1>;
753 #size-cells = <0>;
754 status = "disabled";
755
756 pcs16: ethernet-phy@0 {
757 reg = <0>;
758 };
759 };
760
761 fsl_mc: fsl-mc@80c000000 {
762 compatible = "fsl,qoriq-mc";
763 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
764 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
765 msi-parent = <&its>;
766 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
767 dma-coherent;
768 #address-cells = <3>;
769 #size-cells = <1>;
770
771 /*
772 * Region type 0x0 - MC portals
773 * Region type 0x1 - QBMAN portals
774 */
775 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
776 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
777
778 /*
779 * Define the maximum number of MACs present on the SoC.
780 */
781 dpmacs {
782 #address-cells = <1>;
783 #size-cells = <0>;
784
785 dpmac1: ethernet@1 {
786 compatible = "fsl,qoriq-mc-dpmac";
787 reg = <0x1>;
788 pcs-handle = <&pcs1>;
789 };
790
791 dpmac2: ethernet@2 {
792 compatible = "fsl,qoriq-mc-dpmac";
793 reg = <0x2>;
794 pcs-handle = <&pcs2>;
795 };
796
797 dpmac3: ethernet@3 {
798 compatible = "fsl,qoriq-mc-dpmac";
799 reg = <0x3>;
800 pcs-handle = <&pcs3>;
801 };
802
803 dpmac4: ethernet@4 {
804 compatible = "fsl,qoriq-mc-dpmac";
805 reg = <0x4>;
806 pcs-handle = <&pcs4>;
807 };
808
809 dpmac5: ethernet@5 {
810 compatible = "fsl,qoriq-mc-dpmac";
811 reg = <0x5>;
812 pcs-handle = <&pcs5>;
813 };
814
815 dpmac6: ethernet@6 {
816 compatible = "fsl,qoriq-mc-dpmac";
817 reg = <0x6>;
818 pcs-handle = <&pcs6>;
819 };
820
821 dpmac7: ethernet@7 {
822 compatible = "fsl,qoriq-mc-dpmac";
823 reg = <0x7>;
824 pcs-handle = <&pcs7>;
825 };
826
827 dpmac8: ethernet@8 {
828 compatible = "fsl,qoriq-mc-dpmac";
829 reg = <0x8>;
830 pcs-handle = <&pcs8>;
831 };
832
833 dpmac9: ethernet@9 {
834 compatible = "fsl,qoriq-mc-dpmac";
835 reg = <0x9>;
836 pcs-handle = <&pcs9>;
837 };
838
839 dpmac10: ethernet@a {
840 compatible = "fsl,qoriq-mc-dpmac";
841 reg = <0xa>;
842 pcs-handle = <&pcs10>;
843 };
844
845 dpmac11: ethernet@b {
846 compatible = "fsl,qoriq-mc-dpmac";
847 reg = <0xb>;
848 pcs-handle = <&pcs11>;
849 };
850
851 dpmac12: ethernet@c {
852 compatible = "fsl,qoriq-mc-dpmac";
853 reg = <0xc>;
854 pcs-handle = <&pcs12>;
855 };
856
857 dpmac13: ethernet@d {
858 compatible = "fsl,qoriq-mc-dpmac";
859 reg = <0xd>;
860 pcs-handle = <&pcs13>;
861 };
862
863 dpmac14: ethernet@e {
864 compatible = "fsl,qoriq-mc-dpmac";
865 reg = <0xe>;
866 pcs-handle = <&pcs14>;
867 };
868
869 dpmac15: ethernet@f {
870 compatible = "fsl,qoriq-mc-dpmac";
871 reg = <0xf>;
872 pcs-handle = <&pcs15>;
873 };
874
875 dpmac16: ethernet@10 {
876 compatible = "fsl,qoriq-mc-dpmac";
877 reg = <0x10>;
878 pcs-handle = <&pcs16>;
879 };
880 };
881 };
882
883 smmu: iommu@5000000 {
884 compatible = "arm,mmu-500";
885 reg = <0 0x5000000 0 0x800000>;
886 #global-interrupts = <12>;
887 #iommu-cells = <1>;
888 stream-match-mask = <0x7C00>;
889 dma-coherent;
890 interrupts = <0 13 4>, /* global secure fault */
891 <0 14 4>, /* combined secure interrupt */
892 <0 15 4>, /* global non-secure fault */
893 <0 16 4>, /* combined non-secure interrupt */
894 /* performance counter interrupts 0-7 */
895 <0 211 4>, <0 212 4>,
896 <0 213 4>, <0 214 4>,
897 <0 215 4>, <0 216 4>,
898 <0 217 4>, <0 218 4>,
899 /* per context interrupt, 64 interrupts */
900 <0 146 4>, <0 147 4>,
901 <0 148 4>, <0 149 4>,
902 <0 150 4>, <0 151 4>,
903 <0 152 4>, <0 153 4>,
904 <0 154 4>, <0 155 4>,
905 <0 156 4>, <0 157 4>,
906 <0 158 4>, <0 159 4>,
907 <0 160 4>, <0 161 4>,
908 <0 162 4>, <0 163 4>,
909 <0 164 4>, <0 165 4>,
910 <0 166 4>, <0 167 4>,
911 <0 168 4>, <0 169 4>,
912 <0 170 4>, <0 171 4>,
913 <0 172 4>, <0 173 4>,
914 <0 174 4>, <0 175 4>,
915 <0 176 4>, <0 177 4>,
916 <0 178 4>, <0 179 4>,
917 <0 180 4>, <0 181 4>,
918 <0 182 4>, <0 183 4>,
919 <0 184 4>, <0 185 4>,
920 <0 186 4>, <0 187 4>,
921 <0 188 4>, <0 189 4>,
922 <0 190 4>, <0 191 4>,
923 <0 192 4>, <0 193 4>,
924 <0 194 4>, <0 195 4>,
925 <0 196 4>, <0 197 4>,
926 <0 198 4>, <0 199 4>,
927 <0 200 4>, <0 201 4>,
928 <0 202 4>, <0 203 4>,
929 <0 204 4>, <0 205 4>,
930 <0 206 4>, <0 207 4>,
931 <0 208 4>, <0 209 4>;
932 };
933
934 dspi: spi@2100000 {
935 status = "disabled";
936 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
937 #address-cells = <1>;
938 #size-cells = <0>;
939 reg = <0x0 0x2100000 0x0 0x10000>;
940 interrupts = <0 26 0x4>; /* Level high type */
941 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
942 QORIQ_CLK_PLL_DIV(4)>;
943 clock-names = "dspi";
944 spi-num-chipselects = <5>;
945 };
946
947 esdhc: esdhc@2140000 {
948 status = "disabled";
949 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
950 reg = <0x0 0x2140000 0x0 0x10000>;
951 interrupts = <0 28 0x4>; /* Level high type */
952 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
953 QORIQ_CLK_PLL_DIV(2)>;
954 voltage-ranges = <1800 1800 3300 3300>;
955 sdhci,auto-cmd12;
956 little-endian;
957 bus-width = <4>;
958 };
959
960 gpio0: gpio@2300000 {
961 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
962 reg = <0x0 0x2300000 0x0 0x10000>;
963 interrupts = <0 36 0x4>; /* Level high type */
964 gpio-controller;
965 little-endian;
966 #gpio-cells = <2>;
967 interrupt-controller;
968 #interrupt-cells = <2>;
969 };
970
971 gpio1: gpio@2310000 {
972 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
973 reg = <0x0 0x2310000 0x0 0x10000>;
974 interrupts = <0 36 0x4>; /* Level high type */
975 gpio-controller;
976 little-endian;
977 #gpio-cells = <2>;
978 interrupt-controller;
979 #interrupt-cells = <2>;
980 };
981
982 gpio2: gpio@2320000 {
983 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
984 reg = <0x0 0x2320000 0x0 0x10000>;
985 interrupts = <0 37 0x4>; /* Level high type */
986 gpio-controller;
987 little-endian;
988 #gpio-cells = <2>;
989 interrupt-controller;
990 #interrupt-cells = <2>;
991 };
992
993 gpio3: gpio@2330000 {
994 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
995 reg = <0x0 0x2330000 0x0 0x10000>;
996 interrupts = <0 37 0x4>; /* Level high type */
997 gpio-controller;
998 little-endian;
999 #gpio-cells = <2>;
1000 interrupt-controller;
1001 #interrupt-cells = <2>;
1002 };
1003
1004 i2c0: i2c@2000000 {
1005 status = "disabled";
1006 compatible = "fsl,vf610-i2c";
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1009 reg = <0x0 0x2000000 0x0 0x10000>;
1010 interrupts = <0 34 0x4>; /* Level high type */
1011 clock-names = "i2c";
1012 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1013 QORIQ_CLK_PLL_DIV(4)>;
1014 };
1015
1016 i2c1: i2c@2010000 {
1017 status = "disabled";
1018 compatible = "fsl,vf610-i2c";
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 reg = <0x0 0x2010000 0x0 0x10000>;
1022 interrupts = <0 34 0x4>; /* Level high type */
1023 clock-names = "i2c";
1024 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1025 QORIQ_CLK_PLL_DIV(4)>;
1026 };
1027
1028 i2c2: i2c@2020000 {
1029 status = "disabled";
1030 compatible = "fsl,vf610-i2c";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1033 reg = <0x0 0x2020000 0x0 0x10000>;
1034 interrupts = <0 35 0x4>; /* Level high type */
1035 clock-names = "i2c";
1036 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1037 QORIQ_CLK_PLL_DIV(4)>;
1038 };
1039
1040 i2c3: i2c@2030000 {
1041 status = "disabled";
1042 compatible = "fsl,vf610-i2c";
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 reg = <0x0 0x2030000 0x0 0x10000>;
1046 interrupts = <0 35 0x4>; /* Level high type */
1047 clock-names = "i2c";
1048 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1049 QORIQ_CLK_PLL_DIV(4)>;
1050 };
1051
1052 ifc: memory-controller@2240000 {
1053 compatible = "fsl,ifc";
1054 reg = <0x0 0x2240000 0x0 0x20000>;
1055 interrupts = <0 21 0x4>; /* Level high type */
1056 little-endian;
1057 #address-cells = <2>;
1058 #size-cells = <1>;
1059
1060 ranges = <0 0 0x5 0x80000000 0x08000000
1061 2 0 0x5 0x30000000 0x00010000
1062 3 0 0x5 0x20000000 0x00010000>;
1063 };
1064
1065 qspi: spi@20c0000 {
1066 compatible = "fsl,ls2080a-qspi";
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1069 reg = <0x0 0x20c0000 0x0 0x10000>,
1070 <0x0 0x20000000 0x0 0x10000000>;
1071 reg-names = "QuadSPI", "QuadSPI-memory";
1072 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1074 QORIQ_CLK_PLL_DIV(4)>,
1075 <&clockgen QORIQ_CLK_PLATFORM_PLL
1076 QORIQ_CLK_PLL_DIV(4)>;
1077 clock-names = "qspi_en", "qspi";
1078 status = "disabled";
1079 };
1080
1081 pcie1: pcie@3400000 {
1082 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1083 reg-names = "regs", "config";
1084 interrupts = <0 108 0x4>; /* Level high type */
1085 interrupt-names = "intr";
1086 #address-cells = <3>;
1087 #size-cells = <2>;
1088 device_type = "pci";
1089 dma-coherent;
1090 num-viewport = <6>;
1091 bus-range = <0x0 0xff>;
1092 msi-parent = <&its>;
1093 #interrupt-cells = <1>;
1094 interrupt-map-mask = <0 0 0 7>;
1095 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1096 <0000 0 0 2 &gic 0 0 0 110 4>,
1097 <0000 0 0 3 &gic 0 0 0 111 4>,
1098 <0000 0 0 4 &gic 0 0 0 112 4>;
1099 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1100 status = "disabled";
1101 };
1102
1103 pcie2: pcie@3500000 {
1104 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1105 reg-names = "regs", "config";
1106 interrupts = <0 113 0x4>; /* Level high type */
1107 interrupt-names = "intr";
1108 #address-cells = <3>;
1109 #size-cells = <2>;
1110 device_type = "pci";
1111 dma-coherent;
1112 num-viewport = <6>;
1113 bus-range = <0x0 0xff>;
1114 msi-parent = <&its>;
1115 #interrupt-cells = <1>;
1116 interrupt-map-mask = <0 0 0 7>;
1117 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1118 <0000 0 0 2 &gic 0 0 0 115 4>,
1119 <0000 0 0 3 &gic 0 0 0 116 4>,
1120 <0000 0 0 4 &gic 0 0 0 117 4>;
1121 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1122 status = "disabled";
1123 };
1124
1125 pcie3: pcie@3600000 {
1126 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1127 reg-names = "regs", "config";
1128 interrupts = <0 118 0x4>; /* Level high type */
1129 interrupt-names = "intr";
1130 #address-cells = <3>;
1131 #size-cells = <2>;
1132 device_type = "pci";
1133 dma-coherent;
1134 num-viewport = <256>;
1135 bus-range = <0x0 0xff>;
1136 msi-parent = <&its>;
1137 #interrupt-cells = <1>;
1138 interrupt-map-mask = <0 0 0 7>;
1139 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1140 <0000 0 0 2 &gic 0 0 0 120 4>,
1141 <0000 0 0 3 &gic 0 0 0 121 4>,
1142 <0000 0 0 4 &gic 0 0 0 122 4>;
1143 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1144 status = "disabled";
1145 };
1146
1147 pcie4: pcie@3700000 {
1148 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1149 reg-names = "regs", "config";
1150 interrupts = <0 123 0x4>; /* Level high type */
1151 interrupt-names = "intr";
1152 #address-cells = <3>;
1153 #size-cells = <2>;
1154 device_type = "pci";
1155 dma-coherent;
1156 num-viewport = <6>;
1157 bus-range = <0x0 0xff>;
1158 msi-parent = <&its>;
1159 #interrupt-cells = <1>;
1160 interrupt-map-mask = <0 0 0 7>;
1161 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1162 <0000 0 0 2 &gic 0 0 0 125 4>,
1163 <0000 0 0 3 &gic 0 0 0 126 4>,
1164 <0000 0 0 4 &gic 0 0 0 127 4>;
1165 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1166 status = "disabled";
1167 };
1168
1169 sata0: sata@3200000 {
1170 status = "disabled";
1171 compatible = "fsl,ls2080a-ahci";
1172 reg = <0x0 0x3200000 0x0 0x10000>;
1173 interrupts = <0 133 0x4>; /* Level high type */
1174 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1175 QORIQ_CLK_PLL_DIV(4)>;
1176 dma-coherent;
1177 };
1178
1179 sata1: sata@3210000 {
1180 status = "disabled";
1181 compatible = "fsl,ls2080a-ahci";
1182 reg = <0x0 0x3210000 0x0 0x10000>;
1183 interrupts = <0 136 0x4>; /* Level high type */
1184 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1185 QORIQ_CLK_PLL_DIV(4)>;
1186 dma-coherent;
1187 };
1188
1189 bus: bus {
1190 #address-cells = <2>;
1191 #size-cells = <2>;
1192 compatible = "simple-bus";
1193 ranges;
1194 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
1195
1196 usb0: usb@3100000 {
1197 compatible = "snps,dwc3";
1198 reg = <0x0 0x3100000 0x0 0x10000>;
1199 interrupts = <0 80 0x4>; /* Level high type */
1200 dr_mode = "host";
1201 snps,quirk-frame-length-adjustment = <0x20>;
1202 snps,dis_rxdet_inp3_quirk;
1203 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1204 status = "disabled";
1205 };
1206
1207 usb1: usb@3110000 {
1208 compatible = "snps,dwc3";
1209 reg = <0x0 0x3110000 0x0 0x10000>;
1210 interrupts = <0 81 0x4>; /* Level high type */
1211 dr_mode = "host";
1212 snps,quirk-frame-length-adjustment = <0x20>;
1213 snps,dis_rxdet_inp3_quirk;
1214 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1215 status = "disabled";
1216 };
1217 };
1218
1219 ccn@4000000 {
1220 compatible = "arm,ccn-504";
1221 reg = <0x0 0x04000000 0x0 0x01000000>;
1222 interrupts = <0 12 4>;
1223 };
1224
1225 rcpm: power-controller@1e34040 {
1226 compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1227 reg = <0x0 0x1e34040 0x0 0x18>;
1228 #fsl,rcpm-wakeup-cells = <6>;
1229 little-endian;
1230 };
1231
1232 ftm_alarm0: timer@2800000 {
1233 compatible = "fsl,ls208xa-ftm-alarm";
1234 reg = <0x0 0x2800000 0x0 0x10000>;
1235 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1236 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1237 };
1238 };
1239
1240 ddr1: memory-controller@1080000 {
1241 compatible = "fsl,qoriq-memory-controller";
1242 reg = <0x0 0x1080000 0x0 0x1000>;
1243 interrupts = <0 17 0x4>;
1244 little-endian;
1245 };
1246
1247 ddr2: memory-controller@1090000 {
1248 compatible = "fsl,qoriq-memory-controller";
1249 reg = <0x0 0x1090000 0x0 0x1000>;
1250 interrupts = <0 18 0x4>;
1251 little-endian;
1252 };
1253
1254 firmware {
1255 optee {
1256 compatible = "linaro,optee-tz";
1257 method = "smc";
1258 };
1259 };
1260};