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git01.mediatek.com / filogic / uboot / 762f85bb2e36762ee4d7395002b8181905aec690 / . / src / arm / nxp / imx / imx6dl-yapp4-common.dtsi
blob: c32ea040fecdda4a78dd13795c0a3186620ea1f5 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (C) 2015-2018 Y Soft Corporation, a.s.
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/leds/common.h>
9#include <dt-bindings/pwm/pwm.h>
10
11/ {
12 aliases: aliases {
13 ethernet1 = &eth1;
14 ethernet2 = &eth2;
15 mmc0 = &usdhc3;
16 mmc1 = &usdhc4;
17 };
18
19 backlight: backlight {
20 compatible = "pwm-backlight";
21 pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
22 brightness-levels = <0 32 64 128 255>;
23 default-brightness-level = <32>;
24 num-interpolated-steps = <8>;
25 power-supply = <&sw2_reg>;
26 status = "disabled";
27 };
28
29 lcd_display: display {
30 compatible = "fsl,imx-parallel-display";
31 #address-cells = <1>;
32 #size-cells = <0>;
33 interface-pix-fmt = "rgb24";
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_ipu1>;
36 status = "disabled";
37
38 port@0 {
39 reg = <0>;
40
41 lcd_display_in: endpoint {
42 remote-endpoint = <&ipu1_di0_disp0>;
43 };
44 };
45
46 port@1 {
47 reg = <1>;
48
49 lcd_display_out: endpoint {
50 remote-endpoint = <&lcd_panel_in>;
51 };
52 };
53 };
54
55 panel: panel {
56 compatible = "dataimage,scf0700c48ggu18";
57 power-supply = <&sw2_reg>;
58 backlight = <&backlight>;
59 status = "disabled";
60
61 port {
62 lcd_panel_in: endpoint {
63 remote-endpoint = <&lcd_display_out>;
64 };
65 };
66 };
67
68 reg_pcie: regulator-pcie {
69 compatible = "regulator-fixed";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_pcie_reg>;
72 regulator-name = "MPCIE_3V3";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
76 enable-active-high;
77 status = "disabled";
78 };
79
80 reg_usb_h1_vbus: regulator-usb-h1-vbus {
81 compatible = "regulator-fixed";
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_usbh1_vbus>;
84 regulator-name = "usb_h1_vbus";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
87 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
88 enable-active-high;
89 status = "disabled";
90 };
91
92 reg_usb_otg_vbus: regulator-usb-otg-vbus {
93 compatible = "regulator-fixed";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_usbotg_vbus>;
96 regulator-name = "usb_otg_vbus";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
99 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
100 enable-active-high;
101 };
102};
103
104&fec {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_enet>;
107 phy-mode = "rgmii-id";
108 phy-supply = <&sw2_reg>;
109 status = "okay";
110
111 fixed-link {
112 speed = <1000>;
113 full-duplex;
114 };
115
116 mdio {
117 #address-cells = <1>;
118 #size-cells = <0>;
119
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]120 switch@10 {
121 compatible = "qca,qca8334";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]122 reg = <0x10>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]123 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
124
125 switch_ports: ports {
126 #address-cells = <1>;
127 #size-cells = <0>;
128
129 ethphy0: port@0 {
130 reg = <0>;
131 label = "cpu";
132 phy-mode = "rgmii-id";
133 ethernet = <&fec>;
134
135 fixed-link {
136 speed = <1000>;
137 full-duplex;
138 };
139 };
140
141 eth2: port@2 {
142 reg = <2>;
143 label = "eth2";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]144 phy-mode = "internal";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]145 phy-handle = <&phy_port2>;
146 };
147
148 eth1: port@3 {
149 reg = <3>;
150 label = "eth1";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]151 phy-mode = "internal";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]152 phy-handle = <&phy_port3>;
153 };
154 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]155
156 mdio {
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 phy_port2: ethernet-phy@1 {
161 reg = <1>;
162 };
163
164 phy_port3: ethernet-phy@2 {
165 reg = <2>;
166 };
167 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]168 };
169 };
170};
171
172&hdmi {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_hdmi_cec>;
175 ddc-i2c-bus = <&i2c2>;
176 status = "disabled";
177};
178
179&i2c2 {
180 clock-frequency = <100000>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_i2c2>;
183 status = "okay";
184
185 pmic@8 {
186 compatible = "fsl,pfuze200";
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_pmic>;
189 reg = <0x8>;
190
191 regulators {
192 sw1a_reg: sw1ab {
193 regulator-min-microvolt = <300000>;
194 regulator-max-microvolt = <1875000>;
195 regulator-boot-on;
196 regulator-always-on;
197 regulator-ramp-delay = <6250>;
198 };
199
200 sw2_reg: sw2 {
201 regulator-min-microvolt = <800000>;
202 regulator-max-microvolt = <3300000>;
203 regulator-boot-on;
204 regulator-always-on;
205 };
206
207 sw3a_reg: sw3a {
208 regulator-min-microvolt = <400000>;
209 regulator-max-microvolt = <1975000>;
210 regulator-boot-on;
211 regulator-always-on;
212 };
213
214 sw3b_reg: sw3b {
215 regulator-min-microvolt = <400000>;
216 regulator-max-microvolt = <1975000>;
217 regulator-boot-on;
218 regulator-always-on;
219 };
220
221 swbst_reg: swbst {
222 regulator-min-microvolt = <5000000>;
223 regulator-max-microvolt = <5150000>;
224 };
225
226 vgen1_reg: vgen1 {
227 regulator-min-microvolt = <800000>;
228 regulator-max-microvolt = <1550000>;
229 };
230
231 vgen2_reg: vgen2 {
232 regulator-min-microvolt = <800000>;
233 regulator-max-microvolt = <1550000>;
234 };
235
236 vgen3_reg: vgen3 {
237 regulator-min-microvolt = <1800000>;
238 regulator-max-microvolt = <3300000>;
239 regulator-always-on;
240 };
241
242 vgen4_reg: vgen4 {
243 regulator-min-microvolt = <1800000>;
244 regulator-max-microvolt = <3300000>;
245 regulator-always-on;
246 };
247
248 vgen5_reg: vgen5 {
249 regulator-min-microvolt = <1800000>;
250 regulator-max-microvolt = <3300000>;
251 regulator-always-on;
252 };
253
254 vgen6_reg: vgen6 {
255 regulator-min-microvolt = <1800000>;
256 regulator-max-microvolt = <3300000>;
257 regulator-always-on;
258 };
259
260 vref_reg: vrefddr {
261 regulator-boot-on;
262 regulator-always-on;
263 };
264
265 vsnvs_reg: vsnvs {
266 regulator-min-microvolt = <1000000>;
267 regulator-max-microvolt = <3000000>;
268 regulator-boot-on;
269 regulator-always-on;
270 };
271 };
272 };
273
274 leds: led-controller@30 {
275 compatible = "ti,lp5562";
276 reg = <0x30>;
277 clock-mode = /bits/ 8 <1>;
278 #address-cells = <1>;
279 #size-cells = <0>;
280 status = "disabled";
281
282 led@0 {
283 chan-name = "R";
284 led-cur = /bits/ 8 <0x20>;
285 max-cur = /bits/ 8 <0x60>;
286 reg = <0>;
287 color = <LED_COLOR_ID_RED>;
288 };
289
290 led@1 {
291 chan-name = "G";
292 led-cur = /bits/ 8 <0x20>;
293 max-cur = /bits/ 8 <0x60>;
294 reg = <1>;
295 color = <LED_COLOR_ID_GREEN>;
296 };
297
298 led@2 {
299 chan-name = "B";
300 led-cur = /bits/ 8 <0x20>;
301 max-cur = /bits/ 8 <0x60>;
302 reg = <2>;
303 color = <LED_COLOR_ID_BLUE>;
304 };
305 };
306
307 eeprom@57 {
308 compatible = "atmel,24c128";
309 reg = <0x57>;
310 pagesize = <64>;
311 };
312
313 touchscreen: touchscreen@5c {
314 compatible = "pixcir,pixcir_tangoc";
315 reg = <0x5c>;
316 pinctrl-0 = <&pinctrl_touch>;
317 interrupt-parent = <&gpio4>;
318 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
319 attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
320 reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
321 touchscreen-size-x = <800>;
322 touchscreen-size-y = <480>;
323 status = "disabled";
324 };
325};
326
327&i2c3 {
328 clock-frequency = <100000>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c3>;
331 status = "okay";
332
333 oled_1309: oled@3c {
334 compatible = "solomon,ssd1309fb-i2c";
335 reg = <0x3c>;
336 solomon,height = <64>;
337 solomon,width = <128>;
338 solomon,page-offset = <0>;
339 solomon,segment-no-remap;
340 solomon,prechargep2 = <15>;
341 reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
342 vbat-supply = <&sw2_reg>;
343 status = "disabled";
344 };
345
346 oled_1305: oled@3d {
347 compatible = "solomon,ssd1305fb-i2c";
348 reg = <0x3d>;
349 solomon,height = <64>;
350 solomon,width = <128>;
351 solomon,page-offset = <0>;
352 solomon,col-offset = <4>;
353 solomon,prechargep2 = <15>;
354 reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
355 vbat-supply = <&sw2_reg>;
356 status = "disabled";
357 };
358
359 gpio_oled: gpio@41 {
360 compatible = "nxp,pca9536";
361 gpio-controller;
362 #gpio-cells = <2>;
363 reg = <0x41>;
364 vcc-supply = <&sw2_reg>;
365 status = "disabled";
366 };
367
368 touchkeys: keys@5a {
369 compatible = "fsl,mpr121-touchkey";
370 reg = <0x5a>;
371 vdd-supply = <&sw2_reg>;
372 autorepeat;
373 linux,keycodes = <KEY_1>, <KEY_2>, <KEY_3>, <KEY_4>, <KEY_5>,
374 <KEY_6>, <KEY_7>, <KEY_8>, <KEY_9>,
375 <KEY_BACKSPACE>, <KEY_0>, <KEY_ENTER>;
376 poll-interval = <50>;
377 status = "disabled";
378 };
379};
380
381&iomuxc {
382 pinctrl_enet: enetgrp {
383 fsl,pins = <
384 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020
385 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020
386 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020
387 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020
388 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020
389 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020
390 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020
391 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020
392 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020
393 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020
394 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020
395 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020
396 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020
397 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020
398 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010
399 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010
400 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098
401 >;
402 };
403
404 pinctrl_hdmi_cec: hdmicecgrp {
405 fsl,pins = <
406 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898
407 >;
408 };
409
410 pinctrl_i2c2: i2c2grp {
411 fsl,pins = <
412 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
413 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
414 >;
415 };
416
417 pinctrl_i2c3: i2c3grp {
418 fsl,pins = <
419 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899
420 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
421 >;
422 };
423
424 pinctrl_ipu1: ipu1grp {
425 fsl,pins = <
426 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
427 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
428 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
429 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
430 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
431 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
432 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
433 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
434 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
435 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
436 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
437 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
438 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
439 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
440 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
441 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
442 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
443 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
444 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
445 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
446 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
447 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
448 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
449 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
450 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
451 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
452 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
453 >;
454 };
455
456 pinctrl_pcie: pciegrp {
457 fsl,pins = <
458 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098
459 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098
460 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098
461 >;
462 };
463
464 pinctrl_pcie_reg: pciereggrp {
465 fsl,pins = <
466 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098
467 >;
468 };
469
470 pinctrl_pmic: pmicgrp {
471 fsl,pins = <
472 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098
473 >;
474 };
475
476 pinctrl_pwm1: pwm1grp {
477 fsl,pins = <
478 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8
479 >;
480 };
481
482 pinctrl_touch: touchgrp {
483 fsl,pins = <
484 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098
485 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098
486 >;
487 };
488
489 pinctrl_uart1: uart1grp {
490 fsl,pins = <
491 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8
492 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8
493 >;
494 };
495
496 pinctrl_uart2: uart2grp {
497 fsl,pins = <
498 MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098
499 MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098
500 >;
501 };
502
503 pinctrl_usbh1: usbh1grp {
504 fsl,pins = <
505 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098
506 >;
507 };
508
509 pinctrl_usbh1_vbus: usbh1-vbus {
510 fsl,pins = <
511 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98
512 >;
513 };
514
515 pinctrl_usbotg: usbotggrp {
516 fsl,pins = <
517 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098
518 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098
519 >;
520 };
521
522 pinctrl_usbotg_vbus: usbotg-vbus {
523 fsl,pins = <
524 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98
525 >;
526 };
527
528 pinctrl_usdhc3: usdhc3grp {
529 fsl,pins = <
530 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018
531 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018
532 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
533 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
534 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
535 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
536 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
537 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
538 >;
539 };
540
541 pinctrl_usdhc4: usdhc4grp {
542 fsl,pins = <
543 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069
544 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069
545 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069
546 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069
547 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069
548 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069
549 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069
550 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069
551 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069
552 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069
553 >;
554 };
555
556 pinctrl_wdog: wdoggrp {
557 fsl,pins = <
558 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
559 >;
560 };
561};
562
563&ipu1_di0_disp0 {
564 remote-endpoint = <&lcd_display_in>;
565};
566
567&pcie {
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_pcie>;
570 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
571 vpcie-supply = <&reg_pcie>;
572 status = "disabled";
573};
574
575&pwm1 {
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_pwm1>;
578 status = "disabled";
579};
580
581&uart1 {
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_uart1>;
584 status = "okay";
585};
586
587&uart2 {
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_uart2>;
590 status = "okay";
591};
592
593&usbh1 {
594 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_usbh1>;
596 vbus-supply = <&reg_usb_h1_vbus>;
597 over-current-active-low;
598 status = "disabled";
599};
600
601&usbotg {
602 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_usbotg>;
604 vbus-supply = <&reg_usb_otg_vbus>;
605 over-current-active-low;
606 srp-disable;
607 hnp-disable;
608 adp-disable;
609 status = "okay";
610};
611
612&usbphy1 {
613 fsl,tx-d-cal = <106>;
614 status = "okay";
615};
616
617&usbphy2 {
618 fsl,tx-d-cal = <109>;
619 status = "disabled";
620};
621
622&usdhc3 {
623 pinctrl-names = "default";
624 pinctrl-0 = <&pinctrl_usdhc3>;
625 bus-width = <4>;
626 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
627 wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
628 no-1-8-v;
629 keep-power-in-suspend;
630 wakeup-source;
631 vmmc-supply = <&sw2_reg>;
632 status = "disabled";
633};
634
635&usdhc4 {
636 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_usdhc4>;
638 bus-width = <8>;
639 non-removable;
640 no-1-8-v;
641 keep-power-in-suspend;
642 vmmc-supply = <&sw2_reg>;
643 status = "okay";
644};
645
646&wdog1 {
647 status = "disabled";
648};
649
650&wdog2 {
651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_wdog>;
653 fsl,ext-reset-output;
654 status = "okay";
655};