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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / src / arm / nxp / imx / imx6dl-yapp4-common.dtsi
blob: 3be38a3c4bb11c1eaa458ef30f033ef1cd67a529 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (C) 2015-2018 Y Soft Corporation, a.s.
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/leds/common.h>
9#include <dt-bindings/pwm/pwm.h>
10
11/ {
12 aliases: aliases {
13 ethernet1 = &eth1;
14 ethernet2 = &eth2;
15 mmc0 = &usdhc3;
16 mmc1 = &usdhc4;
17 };
18
19 backlight: backlight {
20 compatible = "pwm-backlight";
21 pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
22 brightness-levels = <0 32 64 128 255>;
23 default-brightness-level = <32>;
24 num-interpolated-steps = <8>;
25 power-supply = <&sw2_reg>;
26 status = "disabled";
27 };
28
29 lcd_display: display {
30 compatible = "fsl,imx-parallel-display";
31 #address-cells = <1>;
32 #size-cells = <0>;
33 interface-pix-fmt = "rgb24";
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_ipu1>;
36 status = "disabled";
37
38 port@0 {
39 reg = <0>;
40
41 lcd_display_in: endpoint {
42 remote-endpoint = <&ipu1_di0_disp0>;
43 };
44 };
45
46 port@1 {
47 reg = <1>;
48
49 lcd_display_out: endpoint {
50 remote-endpoint = <&lcd_panel_in>;
51 };
52 };
53 };
54
55 panel: panel {
56 compatible = "dataimage,scf0700c48ggu18";
57 power-supply = <&sw2_reg>;
58 backlight = <&backlight>;
59 status = "disabled";
60
61 port {
62 lcd_panel_in: endpoint {
63 remote-endpoint = <&lcd_display_out>;
64 };
65 };
66 };
67
68 reg_pcie: regulator-pcie {
69 compatible = "regulator-fixed";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_pcie_reg>;
72 regulator-name = "MPCIE_3V3";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
76 enable-active-high;
77 status = "disabled";
78 };
79
80 reg_usb_h1_vbus: regulator-usb-h1-vbus {
81 compatible = "regulator-fixed";
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_usbh1_vbus>;
84 regulator-name = "usb_h1_vbus";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
87 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
88 enable-active-high;
89 status = "disabled";
90 };
91
92 reg_usb_otg_vbus: regulator-usb-otg-vbus {
93 compatible = "regulator-fixed";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_usbotg_vbus>;
96 regulator-name = "usb_otg_vbus";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
99 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
100 enable-active-high;
101 };
102};
103
104&fec {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_enet>;
107 phy-mode = "rgmii-id";
108 phy-supply = <&sw2_reg>;
109 status = "okay";
110
111 fixed-link {
112 speed = <1000>;
113 full-duplex;
114 };
115
116 mdio {
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 phy_port2: phy@1 {
121 reg = <1>;
122 };
123
124 phy_port3: phy@2 {
125 reg = <2>;
126 };
127
128 switch@10 {
129 compatible = "qca,qca8334";
130 reg = <10>;
131 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
132
133 switch_ports: ports {
134 #address-cells = <1>;
135 #size-cells = <0>;
136
137 ethphy0: port@0 {
138 reg = <0>;
139 label = "cpu";
140 phy-mode = "rgmii-id";
141 ethernet = <&fec>;
142
143 fixed-link {
144 speed = <1000>;
145 full-duplex;
146 };
147 };
148
149 eth2: port@2 {
150 reg = <2>;
151 label = "eth2";
152 phy-handle = <&phy_port2>;
153 };
154
155 eth1: port@3 {
156 reg = <3>;
157 label = "eth1";
158 phy-handle = <&phy_port3>;
159 };
160 };
161 };
162 };
163};
164
165&hdmi {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_hdmi_cec>;
168 ddc-i2c-bus = <&i2c2>;
169 status = "disabled";
170};
171
172&i2c2 {
173 clock-frequency = <100000>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c2>;
176 status = "okay";
177
178 pmic@8 {
179 compatible = "fsl,pfuze200";
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_pmic>;
182 reg = <0x8>;
183
184 regulators {
185 sw1a_reg: sw1ab {
186 regulator-min-microvolt = <300000>;
187 regulator-max-microvolt = <1875000>;
188 regulator-boot-on;
189 regulator-always-on;
190 regulator-ramp-delay = <6250>;
191 };
192
193 sw2_reg: sw2 {
194 regulator-min-microvolt = <800000>;
195 regulator-max-microvolt = <3300000>;
196 regulator-boot-on;
197 regulator-always-on;
198 };
199
200 sw3a_reg: sw3a {
201 regulator-min-microvolt = <400000>;
202 regulator-max-microvolt = <1975000>;
203 regulator-boot-on;
204 regulator-always-on;
205 };
206
207 sw3b_reg: sw3b {
208 regulator-min-microvolt = <400000>;
209 regulator-max-microvolt = <1975000>;
210 regulator-boot-on;
211 regulator-always-on;
212 };
213
214 swbst_reg: swbst {
215 regulator-min-microvolt = <5000000>;
216 regulator-max-microvolt = <5150000>;
217 };
218
219 vgen1_reg: vgen1 {
220 regulator-min-microvolt = <800000>;
221 regulator-max-microvolt = <1550000>;
222 };
223
224 vgen2_reg: vgen2 {
225 regulator-min-microvolt = <800000>;
226 regulator-max-microvolt = <1550000>;
227 };
228
229 vgen3_reg: vgen3 {
230 regulator-min-microvolt = <1800000>;
231 regulator-max-microvolt = <3300000>;
232 regulator-always-on;
233 };
234
235 vgen4_reg: vgen4 {
236 regulator-min-microvolt = <1800000>;
237 regulator-max-microvolt = <3300000>;
238 regulator-always-on;
239 };
240
241 vgen5_reg: vgen5 {
242 regulator-min-microvolt = <1800000>;
243 regulator-max-microvolt = <3300000>;
244 regulator-always-on;
245 };
246
247 vgen6_reg: vgen6 {
248 regulator-min-microvolt = <1800000>;
249 regulator-max-microvolt = <3300000>;
250 regulator-always-on;
251 };
252
253 vref_reg: vrefddr {
254 regulator-boot-on;
255 regulator-always-on;
256 };
257
258 vsnvs_reg: vsnvs {
259 regulator-min-microvolt = <1000000>;
260 regulator-max-microvolt = <3000000>;
261 regulator-boot-on;
262 regulator-always-on;
263 };
264 };
265 };
266
267 leds: led-controller@30 {
268 compatible = "ti,lp5562";
269 reg = <0x30>;
270 clock-mode = /bits/ 8 <1>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 status = "disabled";
274
275 led@0 {
276 chan-name = "R";
277 led-cur = /bits/ 8 <0x20>;
278 max-cur = /bits/ 8 <0x60>;
279 reg = <0>;
280 color = <LED_COLOR_ID_RED>;
281 };
282
283 led@1 {
284 chan-name = "G";
285 led-cur = /bits/ 8 <0x20>;
286 max-cur = /bits/ 8 <0x60>;
287 reg = <1>;
288 color = <LED_COLOR_ID_GREEN>;
289 };
290
291 led@2 {
292 chan-name = "B";
293 led-cur = /bits/ 8 <0x20>;
294 max-cur = /bits/ 8 <0x60>;
295 reg = <2>;
296 color = <LED_COLOR_ID_BLUE>;
297 };
298 };
299
300 eeprom@57 {
301 compatible = "atmel,24c128";
302 reg = <0x57>;
303 pagesize = <64>;
304 };
305
306 touchscreen: touchscreen@5c {
307 compatible = "pixcir,pixcir_tangoc";
308 reg = <0x5c>;
309 pinctrl-0 = <&pinctrl_touch>;
310 interrupt-parent = <&gpio4>;
311 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
312 attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
313 reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
314 touchscreen-size-x = <800>;
315 touchscreen-size-y = <480>;
316 status = "disabled";
317 };
318};
319
320&i2c3 {
321 clock-frequency = <100000>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_i2c3>;
324 status = "okay";
325
326 oled_1309: oled@3c {
327 compatible = "solomon,ssd1309fb-i2c";
328 reg = <0x3c>;
329 solomon,height = <64>;
330 solomon,width = <128>;
331 solomon,page-offset = <0>;
332 solomon,segment-no-remap;
333 solomon,prechargep2 = <15>;
334 reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
335 vbat-supply = <&sw2_reg>;
336 status = "disabled";
337 };
338
339 oled_1305: oled@3d {
340 compatible = "solomon,ssd1305fb-i2c";
341 reg = <0x3d>;
342 solomon,height = <64>;
343 solomon,width = <128>;
344 solomon,page-offset = <0>;
345 solomon,col-offset = <4>;
346 solomon,prechargep2 = <15>;
347 reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
348 vbat-supply = <&sw2_reg>;
349 status = "disabled";
350 };
351
352 gpio_oled: gpio@41 {
353 compatible = "nxp,pca9536";
354 gpio-controller;
355 #gpio-cells = <2>;
356 reg = <0x41>;
357 vcc-supply = <&sw2_reg>;
358 status = "disabled";
359 };
360
361 touchkeys: keys@5a {
362 compatible = "fsl,mpr121-touchkey";
363 reg = <0x5a>;
364 vdd-supply = <&sw2_reg>;
365 autorepeat;
366 linux,keycodes = <KEY_1>, <KEY_2>, <KEY_3>, <KEY_4>, <KEY_5>,
367 <KEY_6>, <KEY_7>, <KEY_8>, <KEY_9>,
368 <KEY_BACKSPACE>, <KEY_0>, <KEY_ENTER>;
369 poll-interval = <50>;
370 status = "disabled";
371 };
372};
373
374&iomuxc {
375 pinctrl_enet: enetgrp {
376 fsl,pins = <
377 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020
378 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020
379 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020
380 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020
381 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020
382 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020
383 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020
384 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020
385 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020
386 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020
387 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020
388 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020
389 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020
390 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020
391 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010
392 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010
393 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098
394 >;
395 };
396
397 pinctrl_hdmi_cec: hdmicecgrp {
398 fsl,pins = <
399 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898
400 >;
401 };
402
403 pinctrl_i2c2: i2c2grp {
404 fsl,pins = <
405 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
406 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
407 >;
408 };
409
410 pinctrl_i2c3: i2c3grp {
411 fsl,pins = <
412 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899
413 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
414 >;
415 };
416
417 pinctrl_ipu1: ipu1grp {
418 fsl,pins = <
419 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
420 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
421 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
422 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
423 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
424 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
425 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
426 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
427 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
428 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
429 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
430 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
431 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
432 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
433 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
434 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
435 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
436 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
437 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
438 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
439 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
440 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
441 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
442 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
443 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
444 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
445 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
446 >;
447 };
448
449 pinctrl_pcie: pciegrp {
450 fsl,pins = <
451 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098
452 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098
453 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098
454 >;
455 };
456
457 pinctrl_pcie_reg: pciereggrp {
458 fsl,pins = <
459 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098
460 >;
461 };
462
463 pinctrl_pmic: pmicgrp {
464 fsl,pins = <
465 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098
466 >;
467 };
468
469 pinctrl_pwm1: pwm1grp {
470 fsl,pins = <
471 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8
472 >;
473 };
474
475 pinctrl_touch: touchgrp {
476 fsl,pins = <
477 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098
478 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098
479 >;
480 };
481
482 pinctrl_uart1: uart1grp {
483 fsl,pins = <
484 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8
485 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8
486 >;
487 };
488
489 pinctrl_uart2: uart2grp {
490 fsl,pins = <
491 MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098
492 MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098
493 >;
494 };
495
496 pinctrl_usbh1: usbh1grp {
497 fsl,pins = <
498 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098
499 >;
500 };
501
502 pinctrl_usbh1_vbus: usbh1-vbus {
503 fsl,pins = <
504 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98
505 >;
506 };
507
508 pinctrl_usbotg: usbotggrp {
509 fsl,pins = <
510 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098
511 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098
512 >;
513 };
514
515 pinctrl_usbotg_vbus: usbotg-vbus {
516 fsl,pins = <
517 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98
518 >;
519 };
520
521 pinctrl_usdhc3: usdhc3grp {
522 fsl,pins = <
523 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018
524 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018
525 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
526 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
527 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
528 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
529 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
530 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
531 >;
532 };
533
534 pinctrl_usdhc4: usdhc4grp {
535 fsl,pins = <
536 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069
537 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069
538 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069
539 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069
540 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069
541 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069
542 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069
543 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069
544 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069
545 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069
546 >;
547 };
548
549 pinctrl_wdog: wdoggrp {
550 fsl,pins = <
551 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
552 >;
553 };
554};
555
556&ipu1_di0_disp0 {
557 remote-endpoint = <&lcd_display_in>;
558};
559
560&pcie {
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_pcie>;
563 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
564 vpcie-supply = <&reg_pcie>;
565 status = "disabled";
566};
567
568&pwm1 {
569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_pwm1>;
571 status = "disabled";
572};
573
574&uart1 {
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_uart1>;
577 status = "okay";
578};
579
580&uart2 {
581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_uart2>;
583 status = "okay";
584};
585
586&usbh1 {
587 pinctrl-names = "default";
588 pinctrl-0 = <&pinctrl_usbh1>;
589 vbus-supply = <&reg_usb_h1_vbus>;
590 over-current-active-low;
591 status = "disabled";
592};
593
594&usbotg {
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_usbotg>;
597 vbus-supply = <&reg_usb_otg_vbus>;
598 over-current-active-low;
599 srp-disable;
600 hnp-disable;
601 adp-disable;
602 status = "okay";
603};
604
605&usbphy1 {
606 fsl,tx-d-cal = <106>;
607 status = "okay";
608};
609
610&usbphy2 {
611 fsl,tx-d-cal = <109>;
612 status = "disabled";
613};
614
615&usdhc3 {
616 pinctrl-names = "default";
617 pinctrl-0 = <&pinctrl_usdhc3>;
618 bus-width = <4>;
619 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
620 wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
621 no-1-8-v;
622 keep-power-in-suspend;
623 wakeup-source;
624 vmmc-supply = <&sw2_reg>;
625 status = "disabled";
626};
627
628&usdhc4 {
629 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_usdhc4>;
631 bus-width = <8>;
632 non-removable;
633 no-1-8-v;
634 keep-power-in-suspend;
635 vmmc-supply = <&sw2_reg>;
636 status = "okay";
637};
638
639&wdog1 {
640 status = "disabled";
641};
642
643&wdog2 {
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_wdog>;
646 fsl,ext-reset-output;
647 status = "okay";
648};