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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Lei Wen142c8f92011-06-28 21:50:06 +00002/*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
Lei Wen142c8f92011-06-28 21:50:06 +00006 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9#ifndef __SDHCI_HW_H
10#define __SDHCI_HW_H
11
Simon Glass4dcacfc2020-05-10 11:40:13 -060012#include <linux/bitops.h>
Masahiro Yamada32d12132020-02-14 16:40:22 +090013#include <linux/types.h>
Lei Wen142c8f92011-06-28 21:50:06 +000014#include <asm/io.h>
Lei Wen5a1108e2011-10-08 04:14:56 +000015#include <mmc.h>
Simon Glassa30d4ba2015-01-05 20:05:38 -070016#include <asm/gpio.h>
Lei Wen5a1108e2011-10-08 04:14:56 +000017
Lei Wen142c8f92011-06-28 21:50:06 +000018/*
19 * Controller registers
20 */
21
22#define SDHCI_DMA_ADDRESS 0x00
23
24#define SDHCI_BLOCK_SIZE 0x04
25#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
26
27#define SDHCI_BLOCK_COUNT 0x06
28
29#define SDHCI_ARGUMENT 0x08
30
31#define SDHCI_TRANSFER_MODE 0x0C
Jaehoon Chung07d012c2016-12-30 15:30:19 +090032#define SDHCI_TRNS_DMA BIT(0)
33#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
34#define SDHCI_TRNS_ACMD12 BIT(2)
35#define SDHCI_TRNS_READ BIT(4)
36#define SDHCI_TRNS_MULTI BIT(5)
Lei Wen142c8f92011-06-28 21:50:06 +000037
38#define SDHCI_COMMAND 0x0E
39#define SDHCI_CMD_RESP_MASK 0x03
40#define SDHCI_CMD_CRC 0x08
41#define SDHCI_CMD_INDEX 0x10
42#define SDHCI_CMD_DATA 0x20
43#define SDHCI_CMD_ABORTCMD 0xC0
44
45#define SDHCI_CMD_RESP_NONE 0x00
46#define SDHCI_CMD_RESP_LONG 0x01
47#define SDHCI_CMD_RESP_SHORT 0x02
48#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
49
50#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
51#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
52
53#define SDHCI_RESPONSE 0x10
54
55#define SDHCI_BUFFER 0x20
56
57#define SDHCI_PRESENT_STATE 0x24
Jaehoon Chung07d012c2016-12-30 15:30:19 +090058#define SDHCI_CMD_INHIBIT BIT(0)
59#define SDHCI_DATA_INHIBIT BIT(1)
60#define SDHCI_DOING_WRITE BIT(8)
61#define SDHCI_DOING_READ BIT(9)
62#define SDHCI_SPACE_AVAILABLE BIT(10)
63#define SDHCI_DATA_AVAILABLE BIT(11)
64#define SDHCI_CARD_PRESENT BIT(16)
65#define SDHCI_CARD_STATE_STABLE BIT(17)
66#define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
67#define SDHCI_WRITE_PROTECT BIT(19)
Lei Wen142c8f92011-06-28 21:50:06 +000068
69#define SDHCI_HOST_CONTROL 0x28
Jaehoon Chung07d012c2016-12-30 15:30:19 +090070#define SDHCI_CTRL_LED BIT(0)
71#define SDHCI_CTRL_4BITBUS BIT(1)
72#define SDHCI_CTRL_HISPD BIT(2)
Lei Wen142c8f92011-06-28 21:50:06 +000073#define SDHCI_CTRL_DMA_MASK 0x18
74#define SDHCI_CTRL_SDMA 0x00
75#define SDHCI_CTRL_ADMA1 0x08
76#define SDHCI_CTRL_ADMA32 0x10
77#define SDHCI_CTRL_ADMA64 0x18
Jaehoon Chung07d012c2016-12-30 15:30:19 +090078#define SDHCI_CTRL_8BITBUS BIT(5)
79#define SDHCI_CTRL_CD_TEST_INS BIT(6)
80#define SDHCI_CTRL_CD_TEST BIT(7)
Lei Wen142c8f92011-06-28 21:50:06 +000081
82#define SDHCI_POWER_CONTROL 0x29
83#define SDHCI_POWER_ON 0x01
84#define SDHCI_POWER_180 0x0A
85#define SDHCI_POWER_300 0x0C
86#define SDHCI_POWER_330 0x0E
87
88#define SDHCI_BLOCK_GAP_CONTROL 0x2A
89
90#define SDHCI_WAKE_UP_CONTROL 0x2B
Jaehoon Chung07d012c2016-12-30 15:30:19 +090091#define SDHCI_WAKE_ON_INT BIT(0)
92#define SDHCI_WAKE_ON_INSERT BIT(1)
93#define SDHCI_WAKE_ON_REMOVE BIT(2)
Lei Wen142c8f92011-06-28 21:50:06 +000094
95#define SDHCI_CLOCK_CONTROL 0x2C
96#define SDHCI_DIVIDER_SHIFT 8
97#define SDHCI_DIVIDER_HI_SHIFT 6
98#define SDHCI_DIV_MASK 0xFF
99#define SDHCI_DIV_MASK_LEN 8
100#define SDHCI_DIV_HI_MASK 0x300
Jaehoon Chung07d012c2016-12-30 15:30:19 +0900101#define SDHCI_PROG_CLOCK_MODE BIT(5)
102#define SDHCI_CLOCK_CARD_EN BIT(2)
103#define SDHCI_CLOCK_INT_STABLE BIT(1)
104#define SDHCI_CLOCK_INT_EN BIT(0)
Lei Wen142c8f92011-06-28 21:50:06 +0000105
106#define SDHCI_TIMEOUT_CONTROL 0x2E
107
108#define SDHCI_SOFTWARE_RESET 0x2F
109#define SDHCI_RESET_ALL 0x01
110#define SDHCI_RESET_CMD 0x02
111#define SDHCI_RESET_DATA 0x04
112
113#define SDHCI_INT_STATUS 0x30
114#define SDHCI_INT_ENABLE 0x34
115#define SDHCI_SIGNAL_ENABLE 0x38
Jaehoon Chung07d012c2016-12-30 15:30:19 +0900116#define SDHCI_INT_RESPONSE BIT(0)
117#define SDHCI_INT_DATA_END BIT(1)
118#define SDHCI_INT_DMA_END BIT(3)
119#define SDHCI_INT_SPACE_AVAIL BIT(4)
120#define SDHCI_INT_DATA_AVAIL BIT(5)
121#define SDHCI_INT_CARD_INSERT BIT(6)
122#define SDHCI_INT_CARD_REMOVE BIT(7)
123#define SDHCI_INT_CARD_INT BIT(8)
124#define SDHCI_INT_ERROR BIT(15)
125#define SDHCI_INT_TIMEOUT BIT(16)
126#define SDHCI_INT_CRC BIT(17)
127#define SDHCI_INT_END_BIT BIT(18)
128#define SDHCI_INT_INDEX BIT(19)
129#define SDHCI_INT_DATA_TIMEOUT BIT(20)
130#define SDHCI_INT_DATA_CRC BIT(21)
131#define SDHCI_INT_DATA_END_BIT BIT(22)
132#define SDHCI_INT_BUS_POWER BIT(23)
133#define SDHCI_INT_ACMD12ERR BIT(24)
134#define SDHCI_INT_ADMA_ERROR BIT(25)
Lei Wen142c8f92011-06-28 21:50:06 +0000135
136#define SDHCI_INT_NORMAL_MASK 0x00007FFF
137#define SDHCI_INT_ERROR_MASK 0xFFFF8000
138
139#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
140 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
141#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
142 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
143 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
144 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
145#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
146
147#define SDHCI_ACMD12_ERR 0x3C
148
Faiz Abbas2eddc002019-06-11 00:43:40 +0530149#define SDHCI_HOST_CONTROL2 0x3E
150#define SDHCI_CTRL_UHS_MASK 0x0007
151#define SDHCI_CTRL_UHS_SDR12 0x0000
152#define SDHCI_CTRL_UHS_SDR25 0x0001
153#define SDHCI_CTRL_UHS_SDR50 0x0002
154#define SDHCI_CTRL_UHS_SDR104 0x0003
155#define SDHCI_CTRL_UHS_DDR50 0x0004
156#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
157#define SDHCI_CTRL_VDD_180 0x0008
158#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
159#define SDHCI_CTRL_DRV_TYPE_B 0x0000
160#define SDHCI_CTRL_DRV_TYPE_A 0x0010
161#define SDHCI_CTRL_DRV_TYPE_C 0x0020
162#define SDHCI_CTRL_DRV_TYPE_D 0x0030
163#define SDHCI_CTRL_EXEC_TUNING 0x0040
164#define SDHCI_CTRL_TUNED_CLK 0x0080
165#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
Lei Wen142c8f92011-06-28 21:50:06 +0000166
167#define SDHCI_CAPABILITIES 0x40
168#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
169#define SDHCI_TIMEOUT_CLK_SHIFT 0
170#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
171#define SDHCI_CLOCK_BASE_MASK 0x00003F00
172#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
173#define SDHCI_CLOCK_BASE_SHIFT 8
174#define SDHCI_MAX_BLOCK_MASK 0x00030000
175#define SDHCI_MAX_BLOCK_SHIFT 16
Jaehoon Chung07d012c2016-12-30 15:30:19 +0900176#define SDHCI_CAN_DO_8BIT BIT(18)
177#define SDHCI_CAN_DO_ADMA2 BIT(19)
178#define SDHCI_CAN_DO_ADMA1 BIT(20)
179#define SDHCI_CAN_DO_HISPD BIT(21)
180#define SDHCI_CAN_DO_SDMA BIT(22)
181#define SDHCI_CAN_VDD_330 BIT(24)
182#define SDHCI_CAN_VDD_300 BIT(25)
183#define SDHCI_CAN_VDD_180 BIT(26)
184#define SDHCI_CAN_64BIT BIT(28)
Lei Wen142c8f92011-06-28 21:50:06 +0000185
186#define SDHCI_CAPABILITIES_1 0x44
Siva Durga Prasad Paladuguc0290b42018-04-19 12:37:08 +0530187#define SDHCI_SUPPORT_SDR50 0x00000001
188#define SDHCI_SUPPORT_SDR104 0x00000002
189#define SDHCI_SUPPORT_DDR50 0x00000004
190#define SDHCI_USE_SDR50_TUNING 0x00002000
191
Wenyou Yang83e88a42016-08-10 10:51:05 +0800192#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
193#define SDHCI_CLOCK_MUL_SHIFT 16
Lei Wen142c8f92011-06-28 21:50:06 +0000194
195#define SDHCI_MAX_CURRENT 0x48
196
197/* 4C-4F reserved for more max current */
198
199#define SDHCI_SET_ACMD12_ERROR 0x50
200#define SDHCI_SET_INT_ERROR 0x52
201
202#define SDHCI_ADMA_ERROR 0x54
203
204/* 55-57 reserved */
205
206#define SDHCI_ADMA_ADDRESS 0x58
Faiz Abbas4c082a62019-04-16 23:06:58 +0530207#define SDHCI_ADMA_ADDRESS_HI 0x5c
Lei Wen142c8f92011-06-28 21:50:06 +0000208
209/* 60-FB reserved */
210
211#define SDHCI_SLOT_INT_STATUS 0xFC
212
213#define SDHCI_HOST_VERSION 0xFE
214#define SDHCI_VENDOR_VER_MASK 0xFF00
215#define SDHCI_VENDOR_VER_SHIFT 8
216#define SDHCI_SPEC_VER_MASK 0x00FF
217#define SDHCI_SPEC_VER_SHIFT 0
218#define SDHCI_SPEC_100 0
219#define SDHCI_SPEC_200 1
220#define SDHCI_SPEC_300 2
221
Jaehoon Chung46e627c2013-07-19 17:44:49 +0900222#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
223
Lei Wen142c8f92011-06-28 21:50:06 +0000224/*
225 * End of controller registers.
226 */
227
228#define SDHCI_MAX_DIV_SPEC_200 256
229#define SDHCI_MAX_DIV_SPEC_300 2046
230
231/*
232 * quirks
233 */
234#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
Ajay Bhargavdab5d4d2011-11-13 23:43:12 +0000235#define SDHCI_QUIRK_REG32_RW (1 << 1)
Jaehoon Chung89237a82012-04-23 02:36:25 +0000236#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000237#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
238#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
Hannes Schmelzer576a0182018-03-07 08:00:56 +0100239/*
240 * SDHCI_QUIRK_BROKEN_HISPD_MODE
241 * the hardware cannot operate correctly in high-speed mode,
242 * this quirk forces the sdhci host-controller to non high-speed mode
243 */
244#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
Tushar Behera0fba4c22012-09-20 20:31:57 +0000245#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
Jaehoon Chung46e627c2013-07-19 17:44:49 +0900246#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
Lei Wen142c8f92011-06-28 21:50:06 +0000247
Lei Wendd1298c2011-10-08 04:14:55 +0000248/* to make gcc happy */
249struct sdhci_host;
250
Lei Wen142c8f92011-06-28 21:50:06 +0000251/*
252 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
253 */
254#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
255#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
256struct sdhci_ops {
257#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
Jaehoon Chung46d3c032016-12-30 15:30:18 +0900258 u32 (*read_l)(struct sdhci_host *host, int reg);
259 u16 (*read_w)(struct sdhci_host *host, int reg);
260 u8 (*read_b)(struct sdhci_host *host, int reg);
261 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
262 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
263 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
Lei Wen142c8f92011-06-28 21:50:06 +0000264#endif
Jaehoon Chung46d3c032016-12-30 15:30:18 +0900265 int (*get_cd)(struct sdhci_host *host);
266 void (*set_control_reg)(struct sdhci_host *host);
Faiz Abbas375acf82019-06-11 00:43:37 +0530267 int (*set_ios_post)(struct sdhci_host *host);
Jaehoon Chung46d3c032016-12-30 15:30:18 +0900268 void (*set_clock)(struct sdhci_host *host, u32 div);
Siva Durga Prasad Paladugu9f044d42018-04-19 12:37:06 +0530269 int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
270 void (*set_delay)(struct sdhci_host *host);
Faiz Abbasd2229212020-02-26 13:44:31 +0530271 int (*deferred_probe)(struct sdhci_host *host);
Lei Wen142c8f92011-06-28 21:50:06 +0000272};
273
Faiz Abbas4c082a62019-04-16 23:06:58 +0530274#define ADMA_MAX_LEN 65532
275#ifdef CONFIG_DMA_ADDR_T_64BIT
276#define ADMA_DESC_LEN 16
277#else
278#define ADMA_DESC_LEN 8
279#endif
280#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
281 MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
282
283#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
284
285/* Decriptor table defines */
286#define ADMA_DESC_ATTR_VALID BIT(0)
287#define ADMA_DESC_ATTR_END BIT(1)
288#define ADMA_DESC_ATTR_INT BIT(2)
289#define ADMA_DESC_ATTR_ACT1 BIT(4)
290#define ADMA_DESC_ATTR_ACT2 BIT(5)
291
292#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
293#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
294
295struct sdhci_adma_desc {
296 u8 attr;
297 u8 reserved;
298 u16 len;
299 u32 addr_lo;
300#ifdef CONFIG_DMA_ADDR_T_64BIT
301 u32 addr_hi;
302#endif
303} __packed;
Michael Walle02016c62020-09-23 12:42:51 +0200304
Lei Wen142c8f92011-06-28 21:50:06 +0000305struct sdhci_host {
Masahiro Yamadaa4405612016-04-22 20:59:31 +0900306 const char *name;
Lei Wen142c8f92011-06-28 21:50:06 +0000307 void *ioaddr;
308 unsigned int quirks;
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000309 unsigned int host_caps;
Lei Wen142c8f92011-06-28 21:50:06 +0000310 unsigned int version;
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100311 unsigned int max_clk; /* Maximum Base Clock frequency */
Wenyou Yang3d734042016-09-18 09:01:22 +0800312 unsigned int clk_mul; /* Clock Multiplier value */
Lei Wen142c8f92011-06-28 21:50:06 +0000313 unsigned int clock;
Lei Wen5a1108e2011-10-08 04:14:56 +0000314 struct mmc *mmc;
Lei Wen142c8f92011-06-28 21:50:06 +0000315 const struct sdhci_ops *ops;
Jaehoon Chungb1929ea2012-08-30 16:24:11 +0000316 int index;
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000317
Piotr Wilczek12cf19e2014-03-07 14:59:41 +0100318 int bus_width;
Simon Glassa30d4ba2015-01-05 20:05:38 -0700319 struct gpio_desc pwr_gpio; /* Power GPIO */
320 struct gpio_desc cd_gpio; /* Card Detect GPIO */
Piotr Wilczek12cf19e2014-03-07 14:59:41 +0100321
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000322 uint voltages;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200323
324 struct mmc_config cfg;
Masahiro Yamadac3a17af2020-02-14 16:40:21 +0900325 void *align_buffer;
Masahiro Yamada32d12132020-02-14 16:40:22 +0900326 bool force_align_buffer;
Faiz Abbas87102502019-04-16 23:06:57 +0530327 dma_addr_t start_addr;
328 int flags;
329#define USE_SDMA (0x1 << 0)
Faiz Abbas4c082a62019-04-16 23:06:58 +0530330#define USE_ADMA (0x1 << 1)
331#define USE_ADMA64 (0x1 << 2)
332#define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64)
333 dma_addr_t adma_addr;
334#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
335 struct sdhci_adma_desc *adma_desc_table;
Faiz Abbas4c082a62019-04-16 23:06:58 +0530336#endif
Lei Wen142c8f92011-06-28 21:50:06 +0000337};
338
339#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
340
341static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
342{
343 if (unlikely(host->ops->write_l))
344 host->ops->write_l(host, val, reg);
345 else
346 writel(val, host->ioaddr + reg);
347}
348
349static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
350{
351 if (unlikely(host->ops->write_w))
352 host->ops->write_w(host, val, reg);
353 else
354 writew(val, host->ioaddr + reg);
355}
356
357static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
358{
359 if (unlikely(host->ops->write_b))
360 host->ops->write_b(host, val, reg);
361 else
362 writeb(val, host->ioaddr + reg);
363}
364
365static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
366{
367 if (unlikely(host->ops->read_l))
368 return host->ops->read_l(host, reg);
369 else
370 return readl(host->ioaddr + reg);
371}
372
373static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
374{
375 if (unlikely(host->ops->read_w))
376 return host->ops->read_w(host, reg);
377 else
378 return readw(host->ioaddr + reg);
379}
380
381static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
382{
383 if (unlikely(host->ops->read_b))
384 return host->ops->read_b(host, reg);
385 else
386 return readb(host->ioaddr + reg);
387}
388
389#else
390
391static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
392{
393 writel(val, host->ioaddr + reg);
394}
395
396static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
397{
398 writew(val, host->ioaddr + reg);
399}
400
401static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
402{
403 writeb(val, host->ioaddr + reg);
404}
405static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
406{
407 return readl(host->ioaddr + reg);
408}
409
410static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
411{
412 return readw(host->ioaddr + reg);
413}
414
415static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
416{
417 return readb(host->ioaddr + reg);
418}
419#endif
420
Simon Glassb97f0fa2016-06-12 23:30:28 -0600421#ifdef CONFIG_BLK
422/**
423 * sdhci_setup_cfg() - Set up the configuration for DWMMC
424 *
425 * This is used to set up an SDHCI device when you are using CONFIG_BLK.
426 *
427 * This should be called from your MMC driver's probe() method once you have
428 * the information required.
429 *
430 * Generally your driver will have a platform data structure which holds both
431 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
432 * For example:
433 *
434 * struct msm_sdhc_plat {
435 * struct mmc_config cfg;
436 * struct mmc mmc;
437 * };
438 *
439 * ...
440 *
441 * Inside U_BOOT_DRIVER():
442 * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
443 *
444 * To access platform data:
445 * struct msm_sdhc_plat *plat = dev_get_platdata(dev);
446 *
447 * See msm_sdhci.c for an example.
448 *
449 * @cfg: Configuration structure to fill in (generally &plat->mmc)
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900450 * @host: SDHCI host structure
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100451 * @f_max: Maximum supported clock frequency in HZ (0 for default)
452 * @f_min: Minimum supported clock frequency in HZ (0 for default)
Simon Glassb97f0fa2016-06-12 23:30:28 -0600453 */
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900454int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100455 u32 f_max, u32 f_min);
Simon Glassb97f0fa2016-06-12 23:30:28 -0600456
457/**
458 * sdhci_bind() - Set up a new MMC block device
459 *
460 * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
461 * It should be called from your driver's bind() method.
462 *
463 * See msm_sdhci.c for an example.
464 *
465 * @dev: Device to set up
466 * @mmc: Pointer to mmc structure (normally &plat->mmc)
467 * @cfg: Empty configuration structure (generally &plat->cfg). This is
468 * normally all zeroes at this point. The only purpose of passing
469 * this in is to set mmc->cfg to it.
470 * @return 0 if OK, -ve if the block device could not be created
471 */
472int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
473#else
474
475/**
476 * add_sdhci() - Add a new SDHCI interface
477 *
478 * This is used when you are not using CONFIG_BLK. Convert your driver over!
479 *
480 * @host: SDHCI host structure
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100481 * @f_max: Maximum supported clock frequency in HZ (0 for default)
482 * @f_min: Minimum supported clock frequency in HZ (0 for default)
Simon Glassb97f0fa2016-06-12 23:30:28 -0600483 * @return 0 if OK, -ve on error
484 */
Stefan Herbrechtsmeierbc47e0e2017-01-17 15:58:48 +0100485int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
Simon Glassb97f0fa2016-06-12 23:30:28 -0600486#endif /* !CONFIG_BLK */
487
Faiz Abbas2eddc002019-06-11 00:43:40 +0530488void sdhci_set_uhs_timing(struct sdhci_host *host);
Simon Glasseba48f92017-07-29 11:35:31 -0600489#ifdef CONFIG_DM_MMC
Simon Glassb97f0fa2016-06-12 23:30:28 -0600490/* Export the operations to drivers */
491int sdhci_probe(struct udevice *dev);
Faiz Abbasab619662019-06-11 00:43:35 +0530492int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
Simon Glassb97f0fa2016-06-12 23:30:28 -0600493extern const struct dm_mmc_ops sdhci_ops;
494#else
495#endif
496
Michael Walle02016c62020-09-23 12:42:51 +0200497struct sdhci_adma_desc *sdhci_adma_init(void);
498void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
499 struct mmc_data *data, dma_addr_t addr);
500
Lei Wen142c8f92011-06-28 21:50:06 +0000501#endif /* __SDHCI_HW_H */