Samuel Holland | f7d4954 | 2021-09-12 09:47:25 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) Samuel Holland <samuel@sholland.org> |
| 4 | */ |
| 5 | |
| 6 | #include <clk-uclass.h> |
| 7 | #include <dm.h> |
| 8 | #include <clk/sunxi.h> |
| 9 | #include <dt-bindings/clock/sun50i-h6-r-ccu.h> |
| 10 | #include <dt-bindings/reset/sun50i-h6-r-ccu.h> |
| 11 | #include <linux/bitops.h> |
| 12 | |
| 13 | static struct ccu_clk_gate h6_r_gates[] = { |
Andre Przywara | 2d1864f | 2022-05-05 01:25:43 +0100 | [diff] [blame] | 14 | [CLK_R_APB1] = GATE_DUMMY, |
| 15 | |
Samuel Holland | f7d4954 | 2021-09-12 09:47:25 -0500 | [diff] [blame] | 16 | [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)), |
| 17 | [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)), |
| 18 | [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)), |
| 19 | [CLK_R_APB2_UART] = GATE(0x18c, BIT(0)), |
| 20 | [CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)), |
| 21 | [CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)), |
| 22 | [CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)), |
| 23 | [CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)), |
| 24 | }; |
| 25 | |
| 26 | static struct ccu_reset h6_r_resets[] = { |
| 27 | [RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)), |
| 28 | [RST_R_APB1_TWD] = RESET(0x12c, BIT(16)), |
| 29 | [RST_R_APB1_PWM] = RESET(0x13c, BIT(16)), |
| 30 | [RST_R_APB2_UART] = RESET(0x18c, BIT(16)), |
| 31 | [RST_R_APB2_I2C] = RESET(0x19c, BIT(16)), |
| 32 | [RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)), |
| 33 | [RST_R_APB1_IR] = RESET(0x1cc, BIT(16)), |
| 34 | [RST_R_APB1_W1] = RESET(0x1ec, BIT(16)), |
| 35 | }; |
| 36 | |
Samuel Holland | 751c6c6 | 2022-05-09 00:29:34 -0500 | [diff] [blame^] | 37 | const struct ccu_desc h6_r_ccu_desc = { |
Samuel Holland | f7d4954 | 2021-09-12 09:47:25 -0500 | [diff] [blame] | 38 | .gates = h6_r_gates, |
| 39 | .resets = h6_r_resets, |
Samuel Holland | 8443650 | 2022-05-09 00:29:31 -0500 | [diff] [blame] | 40 | .num_gates = ARRAY_SIZE(h6_r_gates), |
| 41 | .num_resets = ARRAY_SIZE(h6_r_resets), |
Samuel Holland | f7d4954 | 2021-09-12 09:47:25 -0500 | [diff] [blame] | 42 | }; |