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git01.mediatek.com / filogic / uboot / 7357a35f985e05ac89458665cbe1fcd7b0aff2c0 / . / test / dm / clk.c
blob: 003b78934f35d75fb64d01b40c4c0e221f88c20d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]2/*
3 * Copyright (C) 2015 Google, Inc
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]4 */
5
6#include <common.h>
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]7#include <clk.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]8#include <dm.h>
Simon Glass9bc15642020-02-03 07:36:16 -0700[diff] [blame]9#include <malloc.h>
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]10#include <asm/clk.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]11#include <dm/test.h>
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]12#include <dm/device-internal.h>
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]13#include <linux/err.h>
14#include <test/ut.h>
15
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]16/* Base test of the clk uclass */
17static int dm_test_clk_base(struct unit_test_state *uts)
18{
19 struct udevice *dev;
20 struct clk clk_method1;
21 struct clk clk_method2;
22
23 /* Get the device using the clk device */
24 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &dev));
25
26 /* Get the same clk port in 2 different ways and compare */
27 ut_assertok(clk_get_by_index(dev, 1, &clk_method1));
28 ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2));
Sekhar Noricf3119d2019-08-01 19:12:55 +0530[diff] [blame]29 ut_asserteq(clk_is_match(&clk_method1, &clk_method2), true);
Jagan Tekiab127ba2019-03-05 19:42:44 +0530[diff] [blame]30 ut_asserteq(clk_method1.id, clk_method2.id);
31
32 return 0;
33}
34
35DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_FDT);
36
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]37static int dm_test_clk(struct unit_test_state *uts)
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]38{
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]39 struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test;
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]40 ulong rate;
41
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]42 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed",
43 &dev_fixed));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]44
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]45 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed-factor",
46 &dev_fixed_factor));
47
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]48 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
49 &dev_clk));
50 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
51 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
52 ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
53 ut_asserteq(0, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]54
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]55 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
56 &dev_test));
57 ut_assertok(sandbox_clk_test_get(dev_test));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]58 ut_assertok(sandbox_clk_test_devm_get(dev_test));
Fabrice Gasnier11192712018-07-24 16:31:28 +0200[diff] [blame]59 ut_assertok(sandbox_clk_test_valid(dev_test));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]60
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]61 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
62 SANDBOX_CLK_TEST_ID_DEVM_NULL));
63 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
64 SANDBOX_CLK_TEST_ID_DEVM_NULL,
65 0));
66 ut_asserteq(0, sandbox_clk_test_enable(dev_test,
67 SANDBOX_CLK_TEST_ID_DEVM_NULL));
68 ut_asserteq(0, sandbox_clk_test_disable(dev_test,
69 SANDBOX_CLK_TEST_ID_DEVM_NULL));
70
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]71 ut_asserteq(1234,
72 sandbox_clk_test_get_rate(dev_test,
73 SANDBOX_CLK_TEST_ID_FIXED));
74 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
75 SANDBOX_CLK_TEST_ID_SPI));
76 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
77 SANDBOX_CLK_TEST_ID_I2C));
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200[diff] [blame]78 ut_asserteq(321, sandbox_clk_test_get_rate(dev_test,
79 SANDBOX_CLK_TEST_ID_DEVM1));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]80 ut_asserteq(0, sandbox_clk_test_get_rate(dev_test,
81 SANDBOX_CLK_TEST_ID_DEVM2));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]82
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]83 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED,
84 12345);
85 ut_assert(IS_ERR_VALUE(rate));
86 rate = sandbox_clk_test_get_rate(dev_test, SANDBOX_CLK_TEST_ID_FIXED);
87 ut_asserteq(1234, rate);
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]88
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]89 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
90 SANDBOX_CLK_TEST_ID_SPI,
91 1000));
92 ut_asserteq(0, sandbox_clk_test_set_rate(dev_test,
93 SANDBOX_CLK_TEST_ID_I2C,
94 2000));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]95
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]96 ut_asserteq(1000, sandbox_clk_test_get_rate(dev_test,
97 SANDBOX_CLK_TEST_ID_SPI));
98 ut_asserteq(2000, sandbox_clk_test_get_rate(dev_test,
99 SANDBOX_CLK_TEST_ID_I2C));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]100
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]101 ut_asserteq(1000, sandbox_clk_test_set_rate(dev_test,
102 SANDBOX_CLK_TEST_ID_SPI,
103 10000));
104 ut_asserteq(2000, sandbox_clk_test_set_rate(dev_test,
105 SANDBOX_CLK_TEST_ID_I2C,
106 20000));
107
108 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_SPI, 0);
109 ut_assert(IS_ERR_VALUE(rate));
110 rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_I2C, 0);
111 ut_assert(IS_ERR_VALUE(rate));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]112
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]113 ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
114 SANDBOX_CLK_TEST_ID_SPI));
115 ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
116 SANDBOX_CLK_TEST_ID_I2C));
117
118 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
119 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
120 ut_asserteq(10000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_SPI));
121 ut_asserteq(20000, sandbox_clk_query_rate(dev_clk, SANDBOX_CLK_ID_I2C));
122
123 ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_SPI));
124 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
125 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
126
127 ut_assertok(sandbox_clk_test_enable(dev_test, SANDBOX_CLK_TEST_ID_I2C));
128 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
129 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
130
131 ut_assertok(sandbox_clk_test_disable(dev_test,
132 SANDBOX_CLK_TEST_ID_SPI));
133 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
134 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
135
136 ut_assertok(sandbox_clk_test_disable(dev_test,
137 SANDBOX_CLK_TEST_ID_I2C));
138 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
139 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
140
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]141 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
142 SANDBOX_CLK_ID_SPI));
143 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
144 SANDBOX_CLK_ID_I2C));
145 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
146 SANDBOX_CLK_ID_UART2));
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]147 ut_assertok(sandbox_clk_test_free(dev_test));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]148 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
149 SANDBOX_CLK_ID_SPI));
150 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
151 SANDBOX_CLK_ID_I2C));
152 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
153 SANDBOX_CLK_ID_UART2));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]154
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]155 ut_asserteq(1, sandbox_clk_query_requested(dev_clk,
156 SANDBOX_CLK_ID_UART1));
157 ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
158 ut_asserteq(0, sandbox_clk_query_requested(dev_clk,
159 SANDBOX_CLK_ID_UART1));
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]160 return 0;
161}
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]162DM_TEST(dm_test_clk, DM_TESTF_SCAN_FDT);
Neil Armstrong567a38b2018-04-03 11:44:19 +0200[diff] [blame]163
164static int dm_test_clk_bulk(struct unit_test_state *uts)
165{
166 struct udevice *dev_clk, *dev_test;
167
168 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
169 &dev_clk));
170 ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test",
171 &dev_test));
172 ut_assertok(sandbox_clk_test_get_bulk(dev_test));
173
174 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
175 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
176
177 /* Fixed clock does not support enable, thus should not fail */
178 ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
179 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
180 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
181
182 /* Fixed clock does not support disable, thus should not fail */
183 ut_assertok(sandbox_clk_test_disable_bulk(dev_test));
184 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
185 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
186
187 /* Fixed clock does not support enable, thus should not fail */
188 ut_assertok(sandbox_clk_test_enable_bulk(dev_test));
189 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
190 ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
191
192 /* Fixed clock does not support disable, thus should not fail */
193 ut_assertok(sandbox_clk_test_release_bulk(dev_test));
194 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
195 ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C));
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]196 ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
Neil Armstrong567a38b2018-04-03 11:44:19 +0200[diff] [blame]197
198 return 0;
199}
200DM_TEST(dm_test_clk_bulk, DM_TESTF_SCAN_FDT);