blob: e6b562e3309de1df804969d99cdba07c3c0411a1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek04b7e622015-01-15 10:01:51 +01002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
Michal Simeka8c94362023-07-10 14:35:49 +02004 * Michal Simek <michal.simek@amd.com>
Michal Simek04b7e622015-01-15 10:01:51 +01005 */
6
7#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06008#include <command.h>
Simon Glass370382c2019-11-14 12:57:35 -07009#include <cpu_func.h>
Michal Simek09a7d7d2020-01-07 09:02:52 +010010#include <debug_uart.h>
Michal Simekcfb37602021-07-27 16:19:18 +020011#include <dfu.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060012#include <env.h>
Michal Simek8d4a8d42020-07-30 13:37:49 +020013#include <env_internal.h>
Simon Glassa7b51302019-11-14 12:57:46 -070014#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060015#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -060016#include <net.h>
Michal Simekd54b1af2015-09-30 17:26:55 +020017#include <sata.h>
Michal Simekb216cc12015-07-23 13:27:40 +020018#include <ahci.h>
19#include <scsi.h>
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +020020#include <soc.h>
Venkatesh Yadav Abbarapuad11fa42024-02-07 14:03:28 +053021#include <spl.h>
Michal Simekecfb6dc2016-04-22 14:28:54 +020022#include <malloc.h>
Michal Simekcfb37602021-07-27 16:19:18 +020023#include <memalign.h>
Michal Simekbf0f9ca2018-04-19 15:43:38 +020024#include <wdt.h>
Michal Simekc23d3f82015-11-05 08:34:35 +010025#include <asm/arch/clk.h>
Michal Simek04b7e622015-01-15 10:01:51 +010026#include <asm/arch/hardware.h>
27#include <asm/arch/sys_proto.h>
Michal Simekf2f08642018-01-10 09:36:09 +010028#include <asm/arch/psu_init_gpl.h>
Simon Glass274e0b02020-05-10 11:39:56 -060029#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060030#include <asm/global_data.h>
Michal Simek04b7e622015-01-15 10:01:51 +010031#include <asm/io.h>
Simon Glass6b9f0102020-05-10 11:40:06 -060032#include <asm/ptrace.h>
Michal Simekf183a982018-04-25 11:20:43 +020033#include <dm/device.h>
Michal Simekbf0f9ca2018-04-19 15:43:38 +020034#include <dm/uclass.h>
Siva Durga Prasad Paladuguba1f68e2015-08-04 13:03:26 +053035#include <usb.h>
36#include <dwc3-uboot.h>
Michal Simek8111aff2016-02-01 15:05:58 +010037#include <zynqmppl.h>
Ibai Erkiagac8a3efa2019-09-27 11:37:01 +010038#include <zynqmp_firmware.h>
Michal Simek76d0a772016-09-01 11:16:40 +020039#include <g_dnl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060040#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060041#include <linux/delay.h>
42#include <linux/sizes.h>
Michal Simek705d44a2020-03-31 12:39:37 +020043#include "../common/board.h"
Michal Simek04b7e622015-01-15 10:01:51 +010044
Luca Ceresoli23e65002019-05-21 18:06:43 +020045#include "pm_cfg_obj.h"
46
Michal Simek04b7e622015-01-15 10:01:51 +010047DECLARE_GLOBAL_DATA_PTR;
48
Michal Simek1aab1142020-09-09 14:41:56 +020049#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
Oleksandr Suvorovdae95a42022-07-22 17:16:04 +030050static xilinx_desc zynqmppl = {
51 xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, NULL,
52 ZYNQMP_FPGA_FLAGS
53};
Michal Simek8111aff2016-02-01 15:05:58 +010054#endif
55
Michal Simeke5710e32022-02-17 14:28:42 +010056int __maybe_unused psu_uboot_init(void)
Michal Simek8b353302017-02-07 14:32:26 +010057{
Michal Simek09a7d7d2020-01-07 09:02:52 +010058 int ret;
59
Michal Simekc8785f22018-01-10 11:48:48 +010060 ret = psu_init();
Michal Simek09a7d7d2020-01-07 09:02:52 +010061 if (ret)
62 return ret;
Michal Simek1f55e572020-03-20 08:59:02 +010063
Adrian Fiergolski8e87ecf2021-06-08 12:37:23 +020064 /*
65 * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
66 * supply sense channel to SysMon supply registers inside the IP.
67 * This register must be programmed to complete SysMon IP
68 * configuration. The default register configuration after
69 * power-up is incorrect. Hence, fix this by writing the
70 * correct value - 0x3210.
71 */
72 writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
73 ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
74
Michal Simek1f55e572020-03-20 08:59:02 +010075 /* Delay is required for clocks to be propagated */
76 udelay(1000000);
Michal Simeke5710e32022-02-17 14:28:42 +010077
78 return 0;
79}
Michal Simeke0f36102017-07-12 13:08:41 +020080
Michal Simeke5710e32022-02-17 14:28:42 +010081#if !defined(CONFIG_SPL_BUILD)
82# if defined(CONFIG_DEBUG_UART_BOARD_INIT)
83void board_debug_uart_init(void)
84{
85# if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
86 psu_uboot_init();
87# endif
88}
89# endif
Michal Simek09a7d7d2020-01-07 09:02:52 +010090
Michal Simeke5710e32022-02-17 14:28:42 +010091# if defined(CONFIG_BOARD_EARLY_INIT_F)
92int board_early_init_f(void)
93{
94 int ret = 0;
95# if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) && !defined(CONFIG_DEBUG_UART_BOARD_INIT)
96 ret = psu_uboot_init();
97# endif
98 return ret;
Michal Simek8b353302017-02-07 14:32:26 +010099}
Michal Simeke5710e32022-02-17 14:28:42 +0100100# endif
Michal Simekba6fb832022-02-17 14:28:40 +0100101#endif
Michal Simek8b353302017-02-07 14:32:26 +0100102
Michal Simek46900462020-02-11 12:43:14 +0100103static int multi_boot(void)
104{
Michal Simek6aca2832021-07-27 16:17:31 +0200105 u32 multiboot = 0;
106 int ret;
Michal Simek46900462020-02-11 12:43:14 +0100107
Michal Simek6aca2832021-07-27 16:17:31 +0200108 ret = zynqmp_mmio_read((ulong)&csu_base->multi_boot, &multiboot);
109 if (ret)
110 return -EINVAL;
Michal Simek46900462020-02-11 12:43:14 +0100111
Michal Simek21e5c322021-07-27 14:05:27 +0200112 return multiboot;
Michal Simek46900462020-02-11 12:43:14 +0100113}
114
Jorge Ramirez-Ortiz34deca52021-10-13 15:48:00 +0200115#if defined(CONFIG_SPL_BUILD)
116static void restore_jtag(void)
117{
118 if (current_el() != 3)
119 return;
120
121 writel(CSU_JTAG_SEC_GATE_DISABLE, &csu_base->jtag_sec);
122 writel(CSU_JTAG_DAP_ENABLE_DEBUG, &csu_base->jtag_dap_cfg);
123 writel(CSU_JTAG_CHAIN_WR_SETUP, &csu_base->jtag_chain_status_wr);
124 writel(CRLAPB_DBG_LPD_CTRL_SETUP_CLK, &crlapb_base->dbg_lpd_ctrl);
125 writel(CRLAPB_RST_LPD_DBG_RESET, &crlapb_base->rst_lpd_dbg);
126 writel(CSU_PCAP_PROG_RELEASE_PL, &csu_base->pcap_prog);
127}
128#endif
129
Jorge Ramirez-Ortizb0e388a2021-10-13 19:04:47 +0200130static void print_secure_boot(void)
131{
132 u32 status = 0;
133
134 if (zynqmp_mmio_read((ulong)&csu_base->status, &status))
135 return;
136
137 printf("Secure Boot:\t%sauthenticated, %sencrypted\n",
138 status & ZYNQMP_CSU_STATUS_AUTHENTICATED ? "" : "not ",
139 status & ZYNQMP_CSU_STATUS_ENCRYPTED ? "" : "not ");
140}
141
Michal Simek04b7e622015-01-15 10:01:51 +0100142int board_init(void)
143{
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200144#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
145 struct udevice *soc;
146 char name[SOC_MAX_STR_SIZE];
147 int ret;
148#endif
Michal Simek3d49c952022-10-05 11:39:27 +0200149
150#if defined(CONFIG_SPL_BUILD)
151 /* Check *at build time* if the filename is an non-empty string */
152 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
153 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
154 zynqmp_pm_cfg_obj_size);
155#endif
156
Michal Simek826d7eca2020-03-04 08:48:16 +0100157#if defined(CONFIG_ZYNQMP_FIRMWARE)
Ibai Erkiaga2d9b95b2019-09-27 11:37:04 +0100158 struct udevice *dev;
159
Michal Simek6f665992024-01-05 10:55:51 +0100160 uclass_get_device_by_name(UCLASS_FIRMWARE, "power-management", &dev);
161 if (!dev) {
162 uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
163 if (!dev)
164 panic("PMU Firmware device not found - Enable it");
165 }
Michal Simek826d7eca2020-03-04 08:48:16 +0100166#endif
Ibai Erkiaga2d9b95b2019-09-27 11:37:04 +0100167
Luca Ceresoli23e65002019-05-21 18:06:43 +0200168#if defined(CONFIG_SPL_BUILD)
Michal Simekae9dc112021-02-02 16:34:48 +0100169 printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
Jorge Ramirez-Ortiz34deca52021-10-13 15:48:00 +0200170
171 /* the CSU disables the JTAG interface when secure boot is enabled */
Ricardo Salveti5b774f02021-11-04 16:28:02 -0300172 if (CONFIG_IS_ENABLED(ZYNQMP_RESTORE_JTAG))
Jorge Ramirez-Ortiz34deca52021-10-13 15:48:00 +0200173 restore_jtag();
Michal Simek394ee242020-08-03 13:01:45 +0200174#else
175 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
176 xilinx_read_eeprom();
Luca Ceresoli23e65002019-05-21 18:06:43 +0200177#endif
178
Michal Simekfb7242d2015-06-22 14:31:06 +0200179 printf("EL Level:\tEL%d\n", current_el());
180
Michal Simek1aab1142020-09-09 14:41:56 +0200181#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
Stefan Herbrechtsmeier3ff3bd42022-06-20 18:36:43 +0200182 ret = soc_get(&soc);
183 if (!ret) {
184 ret = soc_get_machine(soc, name, sizeof(name));
185 if (ret >= 0) {
186 zynqmppl.name = strdup(name);
187 fpga_init();
188 fpga_add(fpga_xilinx, &zynqmppl);
189 }
190 }
Michal Simekbf0f9ca2018-04-19 15:43:38 +0200191#endif
192
Jorge Ramirez-Ortizb0e388a2021-10-13 19:04:47 +0200193 /* display secure boot information */
194 print_secure_boot();
Michal Simek46900462020-02-11 12:43:14 +0100195 if (current_el() == 3)
Michal Simek21e5c322021-07-27 14:05:27 +0200196 printf("Multiboot:\t%d\n", multi_boot());
Michal Simek46900462020-02-11 12:43:14 +0100197
Michal Simek04b7e622015-01-15 10:01:51 +0100198 return 0;
199}
200
201int board_early_init_r(void)
202{
203 u32 val;
204
Siva Durga Prasad Paladugu64d90002017-12-07 15:05:30 +0530205 if (current_el() != 3)
206 return 0;
207
Michal Simek245d5282017-07-12 10:32:18 +0200208 val = readl(&crlapb_base->timestamp_ref_ctrl);
209 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
210
Siva Durga Prasad Paladugu64d90002017-12-07 15:05:30 +0530211 if (!val) {
Michal Simekc23d3f82015-11-05 08:34:35 +0100212 val = readl(&crlapb_base->timestamp_ref_ctrl);
213 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
214 writel(val, &crlapb_base->timestamp_ref_ctrl);
Michal Simek04b7e622015-01-15 10:01:51 +0100215
Michal Simekc23d3f82015-11-05 08:34:35 +0100216 /* Program freq register in System counter */
217 writel(zynqmp_get_system_timer_freq(),
218 &iou_scntr_secure->base_frequency_id_register);
219 /* And enable system counter */
220 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
221 &iou_scntr_secure->counter_control_register);
222 }
Michal Simek04b7e622015-01-15 10:01:51 +0100223 return 0;
224}
225
Nitin Jainb2eb59b2018-02-16 12:56:17 +0530226unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
Simon Glassed38aef2020-05-10 11:40:03 -0600227 char *const argv[])
Nitin Jainb2eb59b2018-02-16 12:56:17 +0530228{
229 int ret = 0;
230
231 if (current_el() > 1) {
232 smp_kick_all_cpus();
233 dcache_disable();
234 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
235 ES_TO_AARCH64);
236 } else {
237 printf("FAIL: current EL is not above EL1\n");
238 ret = EINVAL;
239 }
240 return ret;
241}
242
Tom Rinibb4dd962022-11-16 13:10:37 -0500243#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
Simon Glass2f949c32017-03-31 08:40:32 -0600244int dram_init_banksize(void)
Michal Simek8faa66a2016-02-08 09:34:53 +0100245{
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530246 int ret;
247
248 ret = fdtdec_setup_memory_banksize();
249 if (ret)
250 return ret;
251
252 mem_map_fill();
253
254 return 0;
Tom Riniedcfdbd2016-12-09 07:56:54 -0500255}
Michal Simek8faa66a2016-02-08 09:34:53 +0100256
Tom Riniedcfdbd2016-12-09 07:56:54 -0500257int dram_init(void)
258{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +0530259 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rossiac04bfa2016-12-19 00:03:34 +1000260 return -EINVAL;
Tom Riniedcfdbd2016-12-09 07:56:54 -0500261
262 return 0;
Michal Simek8faa66a2016-02-08 09:34:53 +0100263}
Michal Simek97ab9612021-05-31 11:03:19 +0200264
Michal Simek8faa66a2016-02-08 09:34:53 +0100265#else
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530266int dram_init_banksize(void)
267{
Tom Rinibb4dd962022-11-16 13:10:37 -0500268 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530269 gd->bd->bi_dram[0].size = get_effective_memsize();
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530270
271 mem_map_fill();
272
273 return 0;
274}
275
Michal Simek04b7e622015-01-15 10:01:51 +0100276int dram_init(void)
277{
Tom Rinibb4dd962022-11-16 13:10:37 -0500278 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
279 CFG_SYS_SDRAM_SIZE);
Michal Simek04b7e622015-01-15 10:01:51 +0100280
281 return 0;
282}
Michal Simek8faa66a2016-02-08 09:34:53 +0100283#endif
Michal Simek04b7e622015-01-15 10:01:51 +0100284
Michal Simek2a220332021-07-13 16:39:26 +0200285#if !CONFIG_IS_ENABLED(SYSRESET)
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100286void reset_cpu(void)
Michal Simek04b7e622015-01-15 10:01:51 +0100287{
288}
Michal Simek2a220332021-07-13 16:39:26 +0200289#endif
Michal Simek04b7e622015-01-15 10:01:51 +0100290
Michal Simek8ec30042020-08-20 10:54:45 +0200291static u8 __maybe_unused zynqmp_get_bootmode(void)
292{
293 u8 bootmode;
294 u32 reg = 0;
295 int ret;
296
297 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
298 if (ret)
299 return -EINVAL;
300
Michal Simek58cc08c2021-07-28 12:25:49 +0200301 debug("HW boot mode: %x\n", reg & BOOT_MODES_MASK);
302 debug("ALT boot mode: %x\n", reg >> BOOT_MODE_ALT_SHIFT);
303
Michal Simek8ec30042020-08-20 10:54:45 +0200304 if (reg >> BOOT_MODE_ALT_SHIFT)
305 reg >>= BOOT_MODE_ALT_SHIFT;
306
307 bootmode = reg & BOOT_MODES_MASK;
308
309 return bootmode;
310}
311
Michal Simek342edfe2018-12-20 09:33:38 +0100312#if defined(CONFIG_BOARD_LATE_INIT)
Michal Simek29b9b712018-05-17 14:06:06 +0200313static const struct {
314 u32 bit;
315 const char *name;
316} reset_reasons[] = {
317 { RESET_REASON_DEBUG_SYS, "DEBUG" },
318 { RESET_REASON_SOFT, "SOFT" },
319 { RESET_REASON_SRST, "SRST" },
320 { RESET_REASON_PSONLY, "PS-ONLY" },
321 { RESET_REASON_PMU, "PMU" },
322 { RESET_REASON_INTERNAL, "INTERNAL" },
323 { RESET_REASON_EXTERNAL, "EXTERNAL" },
324 {}
325};
326
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530327static int reset_reason(void)
Michal Simek29b9b712018-05-17 14:06:06 +0200328{
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530329 u32 reg;
330 int i, ret;
Michal Simek29b9b712018-05-17 14:06:06 +0200331 const char *reason = NULL;
332
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530333 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
334 if (ret)
335 return -EINVAL;
Michal Simek29b9b712018-05-17 14:06:06 +0200336
337 puts("Reset reason:\t");
338
339 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530340 if (reg & reset_reasons[i].bit) {
Michal Simek29b9b712018-05-17 14:06:06 +0200341 reason = reset_reasons[i].name;
342 printf("%s ", reset_reasons[i].name);
343 break;
344 }
345 }
346
347 puts("\n");
348
349 env_set("reset_reason", reason);
350
Michal Simek0954c8c2021-02-09 08:50:22 +0100351 return 0;
Michal Simek29b9b712018-05-17 14:06:06 +0200352}
353
Michal Simek1ca66d72019-02-14 13:14:30 +0100354static int set_fdtfile(void)
355{
356 char *compatible, *fdtfile;
357 const char *suffix = ".dtb";
358 const char *vendor = "xilinx/";
Igor Lantsmane167bac2020-06-24 14:33:46 +0200359 int fdt_compat_len;
Michal Simek1ca66d72019-02-14 13:14:30 +0100360
361 if (env_get("fdtfile"))
362 return 0;
363
Igor Lantsmane167bac2020-06-24 14:33:46 +0200364 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
365 &fdt_compat_len);
366 if (compatible && fdt_compat_len) {
367 char *name;
368
Michal Simek1ca66d72019-02-14 13:14:30 +0100369 debug("Compatible: %s\n", compatible);
370
Igor Lantsmane167bac2020-06-24 14:33:46 +0200371 name = strchr(compatible, ',');
372 if (!name)
373 return -EINVAL;
Michal Simek1ca66d72019-02-14 13:14:30 +0100374
Igor Lantsmane167bac2020-06-24 14:33:46 +0200375 name++;
376
377 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
Michal Simek1ca66d72019-02-14 13:14:30 +0100378 strlen(suffix) + 1);
379 if (!fdtfile)
380 return -ENOMEM;
381
Igor Lantsmane167bac2020-06-24 14:33:46 +0200382 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
Michal Simek1ca66d72019-02-14 13:14:30 +0100383
384 env_set("fdtfile", fdtfile);
385 free(fdtfile);
386 }
387
388 return 0;
389}
390
Michal Simekb1634762023-09-05 13:30:07 +0200391static int boot_targets_setup(void)
Michal Simek9c91e612020-04-08 11:04:41 +0200392{
Michal Simek04b7e622015-01-15 10:01:51 +0100393 u8 bootmode;
Michal Simekf183a982018-04-25 11:20:43 +0200394 struct udevice *dev;
395 int bootseq = -1;
396 int bootseq_len = 0;
Michal Simek7410b142018-04-25 11:10:34 +0200397 int env_targets_len = 0;
Venkatesh Yadav Abbarapu6555dcc2023-09-04 08:50:35 +0530398 const char *mode = NULL;
Michal Simekecfb6dc2016-04-22 14:28:54 +0200399 char *new_targets;
Siva Durga Prasad Paladugu245c5562017-12-20 16:35:06 +0530400 char *env_targets;
Michal Simek7cb4cca2021-10-25 10:10:52 +0200401
Michal Simek9c91e612020-04-08 11:04:41 +0200402 bootmode = zynqmp_get_bootmode();
Michal Simek04b7e622015-01-15 10:01:51 +0100403
Michal Simekc5d95232015-09-20 17:20:42 +0200404 puts("Bootmode: ");
Michal Simek04b7e622015-01-15 10:01:51 +0100405 switch (bootmode) {
Michal Simek12398ea2016-08-19 14:14:52 +0200406 case USB_MODE:
407 puts("USB_MODE\n");
T Karthik Reddy9eee8e32021-03-24 23:37:57 -0600408 mode = "usb_dfu0 usb_dfu1";
Michal Simek43380352017-12-01 15:18:24 +0100409 env_set("modeboot", "usb_dfu_spl");
Michal Simek12398ea2016-08-19 14:14:52 +0200410 break;
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +0530411 case JTAG_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200412 puts("JTAG_MODE\n");
Siva Durga Prasad Paladugu9c441702019-06-25 17:41:09 +0530413 mode = "jtag pxe dhcp";
Michal Simek43380352017-12-01 15:18:24 +0100414 env_set("modeboot", "jtagboot");
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +0530415 break;
416 case QSPI_MODE_24BIT:
417 case QSPI_MODE_32BIT:
Michal Simekecfb6dc2016-04-22 14:28:54 +0200418 mode = "qspi0";
Michal Simekc5d95232015-09-20 17:20:42 +0200419 puts("QSPI_MODE\n");
Michal Simek43380352017-12-01 15:18:24 +0100420 env_set("modeboot", "qspiboot");
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +0530421 break;
Michal Simek02d66cd2015-04-15 15:02:28 +0200422 case EMMC_MODE:
Michal Simekdf7ff0a2015-10-05 15:59:38 +0200423 puts("EMMC_MODE\n");
T Karthik Reddy19735c32019-12-17 06:41:42 -0700424 if (uclass_get_device_by_name(UCLASS_MMC,
425 "mmc@ff160000", &dev) &&
426 uclass_get_device_by_name(UCLASS_MMC,
427 "sdhci@ff160000", &dev)) {
Venkatesh Yadav Abbarapu6555dcc2023-09-04 08:50:35 +0530428 debug("SD0 driver for SD0 device is not present\n");
429 break;
T Karthik Reddy19735c32019-12-17 06:41:42 -0700430 }
Simon Glass75e534b2020-12-16 21:20:07 -0700431 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
T Karthik Reddy19735c32019-12-17 06:41:42 -0700432
433 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700434 bootseq = dev_seq(dev);
Ashok Reddy Somaa10be052021-09-15 08:52:17 +0200435 env_set("modeboot", "emmcboot");
Michal Simekdf7ff0a2015-10-05 15:59:38 +0200436 break;
437 case SD_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200438 puts("SD_MODE\n");
Michal Simekf183a982018-04-25 11:20:43 +0200439 if (uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugue91778d2019-01-03 15:44:24 +0530440 "mmc@ff160000", &dev) &&
441 uclass_get_device_by_name(UCLASS_MMC,
Michal Simekf183a982018-04-25 11:20:43 +0200442 "sdhci@ff160000", &dev)) {
Venkatesh Yadav Abbarapu6555dcc2023-09-04 08:50:35 +0530443 debug("SD0 driver for SD0 device is not present\n");
444 break;
Michal Simekf183a982018-04-25 11:20:43 +0200445 }
Simon Glass75e534b2020-12-16 21:20:07 -0700446 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
Michal Simekf183a982018-04-25 11:20:43 +0200447
448 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700449 bootseq = dev_seq(dev);
Michal Simek43380352017-12-01 15:18:24 +0100450 env_set("modeboot", "sdboot");
Michal Simek04b7e622015-01-15 10:01:51 +0100451 break;
Siva Durga Prasad Paladugu29a77d22016-09-21 11:45:05 +0530452 case SD1_LSHFT_MODE:
453 puts("LVL_SHFT_");
Michal Simek293f47b2021-10-18 13:30:04 +0200454 fallthrough;
Michal Simek108e1842015-10-05 10:51:12 +0200455 case SD_MODE1:
Michal Simekc5d95232015-09-20 17:20:42 +0200456 puts("SD_MODE1\n");
Michal Simekf183a982018-04-25 11:20:43 +0200457 if (uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugue91778d2019-01-03 15:44:24 +0530458 "mmc@ff170000", &dev) &&
459 uclass_get_device_by_name(UCLASS_MMC,
Michal Simekf183a982018-04-25 11:20:43 +0200460 "sdhci@ff170000", &dev)) {
Venkatesh Yadav Abbarapu6555dcc2023-09-04 08:50:35 +0530461 debug("SD1 driver for SD1 device is not present\n");
462 break;
Michal Simekf183a982018-04-25 11:20:43 +0200463 }
Simon Glass75e534b2020-12-16 21:20:07 -0700464 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
Michal Simekf183a982018-04-25 11:20:43 +0200465
466 mode = "mmc";
Simon Glass75e534b2020-12-16 21:20:07 -0700467 bootseq = dev_seq(dev);
Michal Simek43380352017-12-01 15:18:24 +0100468 env_set("modeboot", "sdboot");
Michal Simek108e1842015-10-05 10:51:12 +0200469 break;
470 case NAND_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200471 puts("NAND_MODE\n");
Michal Simekecfb6dc2016-04-22 14:28:54 +0200472 mode = "nand0";
Michal Simek43380352017-12-01 15:18:24 +0100473 env_set("modeboot", "nandboot");
Michal Simek108e1842015-10-05 10:51:12 +0200474 break;
Michal Simek04b7e622015-01-15 10:01:51 +0100475 default:
476 printf("Invalid Boot Mode:0x%x\n", bootmode);
477 break;
478 }
479
Venkatesh Yadav Abbarapu6555dcc2023-09-04 08:50:35 +0530480 if (mode) {
481 if (bootseq >= 0) {
482 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
483 debug("Bootseq len: %x\n", bootseq_len);
484 env_set_hex("bootseq", bootseq);
485 }
Michal Simekf183a982018-04-25 11:20:43 +0200486
Venkatesh Yadav Abbarapu6555dcc2023-09-04 08:50:35 +0530487 /*
488 * One terminating char + one byte for space between mode
489 * and default boot_targets
490 */
491 env_targets = env_get("boot_targets");
492 if (env_targets)
493 env_targets_len = strlen(env_targets);
Michal Simek7410b142018-04-25 11:10:34 +0200494
Venkatesh Yadav Abbarapu6555dcc2023-09-04 08:50:35 +0530495 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
496 bootseq_len);
497 if (!new_targets)
498 return -ENOMEM;
Michal Simek7410b142018-04-25 11:10:34 +0200499
Venkatesh Yadav Abbarapu6555dcc2023-09-04 08:50:35 +0530500 if (bootseq >= 0)
501 sprintf(new_targets, "%s%x %s", mode, bootseq,
502 env_targets ? env_targets : "");
503 else
504 sprintf(new_targets, "%s %s", mode,
505 env_targets ? env_targets : "");
Michal Simekecfb6dc2016-04-22 14:28:54 +0200506
Venkatesh Yadav Abbarapu6555dcc2023-09-04 08:50:35 +0530507 env_set("boot_targets", new_targets);
508 free(new_targets);
509 }
Michal Simekecfb6dc2016-04-22 14:28:54 +0200510
Michal Simekb1634762023-09-05 13:30:07 +0200511 return 0;
512}
513
514int board_late_init(void)
515{
516 int ret, multiboot;
517
518#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
519 usb_ether_init();
520#endif
521
522 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
523 debug("Saved variables - Skipping\n");
524 return 0;
525 }
526
527 if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
528 return 0;
529
530 ret = set_fdtfile();
531 if (ret)
532 return ret;
533
534 multiboot = multi_boot();
535 if (multiboot >= 0)
536 env_set_hex("multiboot", multiboot);
537
538 if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
539 ret = boot_targets_setup();
540 if (ret)
541 return ret;
542 }
543
Michal Simek29b9b712018-05-17 14:06:06 +0200544 reset_reason();
545
Michal Simek705d44a2020-03-31 12:39:37 +0200546 return board_late_init_xilinx();
Michal Simek04b7e622015-01-15 10:01:51 +0100547}
Michal Simek342edfe2018-12-20 09:33:38 +0100548#endif
Siva Durga Prasad Paladugu650e0a32015-08-04 13:01:05 +0530549
550int checkboard(void)
551{
Michal Simek47ce9362016-01-25 11:04:21 +0100552 puts("Board: Xilinx ZynqMP\n");
Siva Durga Prasad Paladugu650e0a32015-08-04 13:01:05 +0530553 return 0;
554}
Michal Simek8d4a8d42020-07-30 13:37:49 +0200555
Michal Simeke0026bf2021-05-19 15:16:19 +0200556int mmc_get_env_dev(void)
557{
558 struct udevice *dev;
559 int bootseq = 0;
560
561 switch (zynqmp_get_bootmode()) {
562 case EMMC_MODE:
563 case SD_MODE:
564 if (uclass_get_device_by_name(UCLASS_MMC,
565 "mmc@ff160000", &dev) &&
566 uclass_get_device_by_name(UCLASS_MMC,
567 "sdhci@ff160000", &dev)) {
568 return -1;
569 }
570 bootseq = dev_seq(dev);
571 break;
572 case SD1_LSHFT_MODE:
573 case SD_MODE1:
574 if (uclass_get_device_by_name(UCLASS_MMC,
575 "mmc@ff170000", &dev) &&
576 uclass_get_device_by_name(UCLASS_MMC,
577 "sdhci@ff170000", &dev)) {
578 return -1;
579 }
580 bootseq = dev_seq(dev);
581 break;
582 default:
583 break;
584 }
585
586 debug("bootseq %d\n", bootseq);
587
588 return bootseq;
589}
590
Michal Simekf3a541f2024-03-22 12:43:17 +0100591#if defined(CONFIG_ENV_IS_NOWHERE)
Michal Simek8d4a8d42020-07-30 13:37:49 +0200592enum env_location env_get_location(enum env_operation op, int prio)
593{
594 u32 bootmode = zynqmp_get_bootmode();
595
596 if (prio)
597 return ENVL_UNKNOWN;
598
599 switch (bootmode) {
600 case EMMC_MODE:
601 case SD_MODE:
602 case SD1_LSHFT_MODE:
603 case SD_MODE1:
604 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
605 return ENVL_FAT;
606 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
607 return ENVL_EXT4;
Mike Looijmans682cf082021-07-02 10:28:36 +0200608 return ENVL_NOWHERE;
Michal Simek8d4a8d42020-07-30 13:37:49 +0200609 case NAND_MODE:
610 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
611 return ENVL_NAND;
612 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
613 return ENVL_UBI;
Mike Looijmans682cf082021-07-02 10:28:36 +0200614 return ENVL_NOWHERE;
Michal Simek8d4a8d42020-07-30 13:37:49 +0200615 case QSPI_MODE_24BIT:
616 case QSPI_MODE_32BIT:
617 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
618 return ENVL_SPI_FLASH;
Mike Looijmans682cf082021-07-02 10:28:36 +0200619 return ENVL_NOWHERE;
Michal Simek8d4a8d42020-07-30 13:37:49 +0200620 case JTAG_MODE:
621 default:
622 return ENVL_NOWHERE;
623 }
624}
Michal Simekf3a541f2024-03-22 12:43:17 +0100625#endif
Michal Simekcfb37602021-07-27 16:19:18 +0200626
627#if defined(CONFIG_SET_DFU_ALT_INFO)
628
629#define DFU_ALT_BUF_LEN SZ_1K
630
631void set_dfu_alt_info(char *interface, char *devstr)
632{
Michal Simek9fced422022-12-02 14:06:15 +0100633 int multiboot, bootseq = 0, len = 0;
Michal Simekcfb37602021-07-27 16:19:18 +0200634
635 ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
636
Michal Simekf0d6f462022-08-09 16:32:52 +0200637 if (env_get("dfu_alt_info"))
Michal Simekcfb37602021-07-27 16:19:18 +0200638 return;
639
640 memset(buf, 0, sizeof(buf));
641
642 multiboot = multi_boot();
Michal Simek7cb4cca2021-10-25 10:10:52 +0200643 if (multiboot < 0)
644 multiboot = 0;
645
646 multiboot = env_get_hex("multiboot", multiboot);
Michal Simekcfb37602021-07-27 16:19:18 +0200647 debug("Multiboot: %d\n", multiboot);
648
649 switch (zynqmp_get_bootmode()) {
650 case EMMC_MODE:
651 case SD_MODE:
652 case SD1_LSHFT_MODE:
653 case SD_MODE1:
654 bootseq = mmc_get_env_dev();
Michal Simek9fced422022-12-02 14:06:15 +0100655
656 len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot",
657 bootseq);
658
659 if (multiboot)
660 len += snprintf(buf + len, DFU_ALT_BUF_LEN,
661 "%04d", multiboot);
662
663 len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1",
664 bootseq);
665#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
Michal Simek64962b62024-03-22 13:09:18 +0100666 if (strlen(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME))
667 len += snprintf(buf + len, DFU_ALT_BUF_LEN,
668 ";%s fat %d 1",
669 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
670 bootseq);
Michal Simek9fced422022-12-02 14:06:15 +0100671#endif
Michal Simekcfb37602021-07-27 16:19:18 +0200672 break;
673 case QSPI_MODE_24BIT:
674 case QSPI_MODE_32BIT:
Michal Simek9fced422022-12-02 14:06:15 +0100675 len += snprintf(buf + len, DFU_ALT_BUF_LEN,
676 "sf 0:0=boot.bin raw %x 0x1500000",
677 multiboot * SZ_32K);
678#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) && defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
Michal Simek64962b62024-03-22 13:09:18 +0100679 if (strlen(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME))
680 len += snprintf(buf + len, DFU_ALT_BUF_LEN,
681 ";%s raw 0x%x 0x500000",
682 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
683 multiboot * SZ_32K +
684 CONFIG_SYS_SPI_U_BOOT_OFFS);
Stefan Herbrechtsmeierfb027cd2022-06-20 18:36:46 +0200685#endif
Michal Simek9fced422022-12-02 14:06:15 +0100686 break;
Michal Simekcfb37602021-07-27 16:19:18 +0200687 default:
688 return;
689 }
690
691 env_set("dfu_alt_info", buf);
692 puts("DFU alt info setting: done\n");
693}
694#endif
Michal Simek55666ce2023-11-10 13:34:35 +0100695
696#if defined(CONFIG_SPL_SPI_LOAD)
697unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
698{
699 u32 offset;
700 int multiboot = multi_boot();
701
702 offset = multiboot * SZ_32K;
703 offset += CONFIG_SYS_SPI_U_BOOT_OFFS;
704
705 log_info("SPI offset:\t0x%x\n", offset);
706
707 return offset;
708}
709#endif