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git01.mediatek.com / filogic / uboot / 720cdc5433edfc0e7ac8578dd43c8c45b8860c56 / . / arch / arm / dts / fsl-imx8qxp-colibri-u-boot.dtsi
blob: 6ab6b1f9ee691234faddc98b823f6f6c840a24c7 [file] [log] [blame]
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 Toradex AG
4 */
5
6&{/imx8qx-pm} {
7
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]8 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]9};
10
11&mu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]13};
14
15&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]16 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]17};
18
19&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]21};
22
23&pd_lsio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]25};
26
27&pd_lsio_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]29};
30
31&pd_lsio_gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]33};
34
35&pd_lsio_gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]37};
38
39&pd_lsio_gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]41};
42
43&pd_lsio_gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]45};
46
47&pd_lsio_gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]49};
50
51&pd_lsio_gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]53};
54
55&pd_lsio_gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]57};
58
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]59&pd_dma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-some-ram;
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]61};
62
63&pd_dma_lpuart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-some-ram;
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]65};
66
67&pd_dma_lpuart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-some-ram;
Igor Opaniukc3d2a5f2020-03-27 12:28:16 +0200[diff] [blame]69};
70
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]71&pd_conn {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]73};
74
75&pd_conn_sdch0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]77};
78
79&pd_conn_sdch1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]81};
82
83&pd_conn_sdch2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]85};
86
Andrejs Cainikovs720cdc52023-12-20 11:38:11 +0100[diff] [blame^]87&gpio_expander_43 {
88 usb-bypass-n-hog {
89 gpio-hog;
90 gpios = <5 GPIO_ACTIVE_LOW>;
91 line-name = "usb-bypass-n";
92 output-high;
93 };
94 usb-reset-n-hog {
95 gpio-hog;
96 gpios = <4 GPIO_ACTIVE_LOW>;
97 line-name = "usb-reset-n";
98 output-low;
99 };
100};
101
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]102&gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]104};
105
106&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]108};
109
110&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]112};
113
114&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]116};
117
118&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]120};
121
122&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]124};
125
126&gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]128};
129
130&gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]131 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]132};
133
134&lpuart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]135 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]136};
137
138&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]139 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]140};
141
142&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]143 bootph-some-ram;
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]144};