Marek Vasut | 7f53256 | 2020-04-12 23:49:25 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 2 | /* |
| 3 | * rtl8139.c : U-Boot driver for the RealTek RTL8139 |
| 4 | * |
| 5 | * Masami Komiya (mkomiya@sonare.it) |
| 6 | * |
| 7 | * Most part is taken from rtl8139.c of etherboot |
| 8 | * |
| 9 | */ |
| 10 | |
| 11 | /* rtl8139.c - etherboot driver for the Realtek 8139 chipset |
Marek Vasut | 278734b | 2020-04-12 23:01:45 +0200 | [diff] [blame] | 12 | * |
| 13 | * ported from the linux driver written by Donald Becker |
| 14 | * by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 |
| 15 | * |
Marek Vasut | 278734b | 2020-04-12 23:01:45 +0200 | [diff] [blame] | 16 | * changes to the original driver: |
| 17 | * - removed support for interrupts, switching to polling mode (yuck!) |
| 18 | * - removed support for the 8129 chip (external MII) |
| 19 | */ |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 20 | |
| 21 | /*********************************************************************/ |
| 22 | /* Revision History */ |
| 23 | /*********************************************************************/ |
| 24 | |
| 25 | /* |
Marek Vasut | 278734b | 2020-04-12 23:01:45 +0200 | [diff] [blame] | 26 | * 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) |
| 27 | * Put in virt_to_bus calls to allow Etherboot relocation. |
| 28 | * |
| 29 | * 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) |
| 30 | * Following email from Hyun-Joon Cha, added a disable routine, otherwise |
| 31 | * NIC remains live and can crash the kernel later. |
| 32 | * |
| 33 | * 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) |
| 34 | * Shuffled things around, removed the leftovers from the 8129 support |
| 35 | * that was in the Linux driver and added a bit more 8139 definitions. |
| 36 | * Moved the 8K receive buffer to a fixed, available address outside the |
| 37 | * 0x98000-0x9ffff range. This is a bit of a hack, but currently the only |
| 38 | * way to make room for the Etherboot features that need substantial amounts |
| 39 | * of code like the ANSI console support. Currently the buffer is just below |
| 40 | * 0x10000, so this even conforms to the tagged boot image specification, |
| 41 | * which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My |
| 42 | * interpretation of this "reserved" is that Etherboot may do whatever it |
| 43 | * likes, as long as its environment is kept intact (like the BIOS |
| 44 | * variables). Hopefully fixed rtl8139_recv() once and for all. The symptoms |
| 45 | * were that if Etherboot was left at the boot menu for several minutes, the |
| 46 | * first eth_poll failed. Seems like I am the only person who does this. |
| 47 | * First of all I fixed the debugging code and then set out for a long bug |
| 48 | * hunting session. It took me about a week full time work - poking around |
| 49 | * various places in the driver, reading Don Becker's and Jeff Garzik's Linux |
| 50 | * driver and even the FreeBSD driver (what a piece of crap!) - and |
| 51 | * eventually spotted the nasty thing: the transmit routine was acknowledging |
| 52 | * each and every interrupt pending, including the RxOverrun and RxFIFIOver |
| 53 | * interrupts. This confused the RTL8139 thoroughly. It destroyed the |
| 54 | * Rx ring contents by dumping the 2K FIFO contents right where we wanted to |
| 55 | * get the next packet. Oh well, what fun. |
| 56 | * |
| 57 | * 18 Jan 2000 mdc@thinguin.org (Marty Connor) |
| 58 | * Drastically simplified error handling. Basically, if any error |
| 59 | * in transmission or reception occurs, the card is reset. |
| 60 | * Also, pointed all transmit descriptors to the same buffer to |
| 61 | * save buffer space. This should decrease driver size and avoid |
| 62 | * corruption because of exceeding 32K during runtime. |
| 63 | * |
| 64 | * 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) |
| 65 | * rtl8139_recv was quite broken: it used the RxOK interrupt flag instead |
| 66 | * of the RxBufferEmpty flag which often resulted in very bad |
| 67 | * transmission performace - below 1kBytes/s. |
| 68 | * |
| 69 | */ |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 70 | |
| 71 | #include <common.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 72 | #include <cpu_func.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 73 | #include <log.h> |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 74 | #include <malloc.h> |
| 75 | #include <net.h> |
Ben Warren | 65b8623 | 2008-08-31 21:41:08 -0700 | [diff] [blame] | 76 | #include <netdev.h> |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 77 | #include <asm/io.h> |
| 78 | #include <pci.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 79 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 80 | #include <linux/delay.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 81 | #include <linux/types.h> |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 82 | |
Shinya Kuribayashi | fad82ef | 2008-01-16 16:11:14 +0900 | [diff] [blame] | 83 | #define RTL_TIMEOUT 100000 |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 84 | |
Marek Vasut | 278734b | 2020-04-12 23:01:45 +0200 | [diff] [blame] | 85 | /* PCI Tuning Parameters */ |
| 86 | /* Threshold is bytes transferred to chip before transmission starts. */ |
wdenk | bc01dd5 | 2004-01-02 16:05:07 +0000 | [diff] [blame] | 87 | #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ |
| 88 | #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ |
| 89 | #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ |
| 90 | #define TX_DMA_BURST 4 /* Calculate as 16<<val. */ |
| 91 | #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */ |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 92 | #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */ |
| 93 | #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */ |
| 94 | #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX) |
| 95 | |
Wolfgang Denk | d7bffbc | 2011-11-05 05:13:03 +0000 | [diff] [blame] | 96 | #define DEBUG_TX 0 /* set to 1 to enable debug code */ |
| 97 | #define DEBUG_RX 0 /* set to 1 to enable debug code */ |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 98 | |
wdenk | bc01dd5 | 2004-01-02 16:05:07 +0000 | [diff] [blame] | 99 | #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) |
| 100 | #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 101 | |
| 102 | /* Symbolic offsets to registers. */ |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 103 | /* Ethernet hardware address. */ |
| 104 | #define RTL_REG_MAC0 0x00 |
| 105 | /* Multicast filter. */ |
| 106 | #define RTL_REG_MAR0 0x08 |
| 107 | /* Transmit status (four 32bit registers). */ |
| 108 | #define RTL_REG_TXSTATUS0 0x10 |
| 109 | /* Tx descriptors (also four 32bit). */ |
| 110 | #define RTL_REG_TXADDR0 0x20 |
| 111 | #define RTL_REG_RXBUF 0x30 |
| 112 | #define RTL_REG_RXEARLYCNT 0x34 |
| 113 | #define RTL_REG_RXEARLYSTATUS 0x36 |
| 114 | #define RTL_REG_CHIPCMD 0x37 |
| 115 | #define RTL_REG_CHIPCMD_CMDRESET BIT(4) |
| 116 | #define RTL_REG_CHIPCMD_CMDRXENB BIT(3) |
| 117 | #define RTL_REG_CHIPCMD_CMDTXENB BIT(2) |
| 118 | #define RTL_REG_CHIPCMD_RXBUFEMPTY BIT(0) |
| 119 | #define RTL_REG_RXBUFPTR 0x38 |
| 120 | #define RTL_REG_RXBUFADDR 0x3A |
| 121 | #define RTL_REG_INTRMASK 0x3C |
| 122 | #define RTL_REG_INTRSTATUS 0x3E |
| 123 | #define RTL_REG_INTRSTATUS_PCIERR BIT(15) |
| 124 | #define RTL_REG_INTRSTATUS_PCSTIMEOUT BIT(14) |
| 125 | #define RTL_REG_INTRSTATUS_CABLELENCHANGE BIT(13) |
| 126 | #define RTL_REG_INTRSTATUS_RXFIFOOVER BIT(6) |
| 127 | #define RTL_REG_INTRSTATUS_RXUNDERRUN BIT(5) |
| 128 | #define RTL_REG_INTRSTATUS_RXOVERFLOW BIT(4) |
| 129 | #define RTL_REG_INTRSTATUS_TXERR BIT(3) |
| 130 | #define RTL_REG_INTRSTATUS_TXOK BIT(2) |
| 131 | #define RTL_REG_INTRSTATUS_RXERR BIT(1) |
| 132 | #define RTL_REG_INTRSTATUS_RXOK BIT(0) |
| 133 | #define RTL_REG_TXCONFIG 0x40 |
| 134 | #define RTL_REG_RXCONFIG 0x44 |
| 135 | #define RTL_REG_RXCONFIG_RXCFGWRAP BIT(7) |
| 136 | #define RTL_REG_RXCONFIG_ACCEPTERR BIT(5) |
| 137 | #define RTL_REG_RXCONFIG_ACCEPTRUNT BIT(4) |
| 138 | #define RTL_REG_RXCONFIG_ACCEPTBROADCAST BIT(3) |
| 139 | #define RTL_REG_RXCONFIG_ACCEPTMULTICAST BIT(2) |
| 140 | #define RTL_REG_RXCONFIG_ACCEPTMYPHYS BIT(1) |
| 141 | #define RTL_REG_RXCONFIG_ACCEPTALLPHYS BIT(0) |
| 142 | /* general-purpose counter. */ |
| 143 | #define RTL_REG_TIMER 0x48 |
| 144 | /* 24 bits valid, write clears. */ |
| 145 | #define RTL_REG_RXMISSED 0x4C |
| 146 | #define RTL_REG_CFG9346 0x50 |
| 147 | #define RTL_REG_CONFIG0 0x51 |
| 148 | #define RTL_REG_CONFIG1 0x52 |
| 149 | /* intr if gp counter reaches this value */ |
| 150 | #define RTL_REG_TIMERINTRREG 0x54 |
| 151 | #define RTL_REG_MEDIASTATUS 0x58 |
| 152 | #define RTL_REG_MEDIASTATUS_MSRTXFLOWENABLE BIT(7) |
| 153 | #define RTL_REG_MEDIASTATUS_MSRRXFLOWENABLE BIT(6) |
| 154 | #define RTL_REG_MEDIASTATUS_MSRSPEED10 BIT(3) |
| 155 | #define RTL_REG_MEDIASTATUS_MSRLINKFAIL BIT(2) |
| 156 | #define RTL_REG_MEDIASTATUS_MSRRXPAUSEFLAG BIT(1) |
| 157 | #define RTL_REG_MEDIASTATUS_MSRTXPAUSEFLAG BIT(0) |
| 158 | #define RTL_REG_CONFIG3 0x59 |
| 159 | #define RTL_REG_MULTIINTR 0x5C |
| 160 | /* revision of the RTL8139 chip */ |
| 161 | #define RTL_REG_REVISIONID 0x5E |
| 162 | #define RTL_REG_TXSUMMARY 0x60 |
| 163 | #define RTL_REG_MII_BMCR 0x62 |
| 164 | #define RTL_REG_MII_BMSR 0x64 |
| 165 | #define RTL_REG_NWAYADVERT 0x66 |
| 166 | #define RTL_REG_NWAYLPAR 0x68 |
| 167 | #define RTL_REG_NWAYEXPANSION 0x6A |
| 168 | #define RTL_REG_DISCONNECTCNT 0x6C |
| 169 | #define RTL_REG_FALSECARRIERCNT 0x6E |
| 170 | #define RTL_REG_NWAYTESTREG 0x70 |
| 171 | /* packet received counter */ |
| 172 | #define RTL_REG_RXCNT 0x72 |
| 173 | /* chip status and configuration register */ |
| 174 | #define RTL_REG_CSCR 0x74 |
| 175 | #define RTL_REG_PHYPARM1 0x78 |
| 176 | #define RTL_REG_TWISTERPARM 0x7c |
| 177 | /* undocumented */ |
| 178 | #define RTL_REG_PHYPARM2 0x80 |
| 179 | /* |
| 180 | * from 0x84 onwards are a number of power management/wakeup frame |
| 181 | * definitions we will probably never need to know about. |
| 182 | */ |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 183 | |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 184 | #define RTL_STS_RXMULTICAST BIT(15) |
| 185 | #define RTL_STS_RXPHYSICAL BIT(14) |
| 186 | #define RTL_STS_RXBROADCAST BIT(13) |
| 187 | #define RTL_STS_RXBADSYMBOL BIT(5) |
| 188 | #define RTL_STS_RXRUNT BIT(4) |
| 189 | #define RTL_STS_RXTOOLONG BIT(3) |
| 190 | #define RTL_STS_RXCRCERR BIT(2) |
| 191 | #define RTL_STS_RXBADALIGN BIT(1) |
| 192 | #define RTL_STS_RXSTATUSOK BIT(0) |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 193 | |
Marek Vasut | 278734b | 2020-04-12 23:01:45 +0200 | [diff] [blame] | 194 | static unsigned int cur_rx, cur_tx; |
Marek Vasut | 5cf2585 | 2020-04-12 23:12:11 +0200 | [diff] [blame] | 195 | static int ioaddr; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 196 | |
| 197 | /* The RTL8139 can only transmit from a contiguous, aligned memory block. */ |
Marek Vasut | 278734b | 2020-04-12 23:01:45 +0200 | [diff] [blame] | 198 | static unsigned char tx_buffer[TX_BUF_SIZE] __aligned(4); |
| 199 | static unsigned char rx_ring[RX_BUF_LEN + 16] __aligned(4); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 200 | |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 201 | /* Serial EEPROM section. */ |
| 202 | |
| 203 | /* EEPROM_Ctrl bits. */ |
wdenk | bc01dd5 | 2004-01-02 16:05:07 +0000 | [diff] [blame] | 204 | #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ |
| 205 | #define EE_CS 0x08 /* EEPROM chip select. */ |
| 206 | #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ |
| 207 | #define EE_WRITE_0 0x00 |
| 208 | #define EE_WRITE_1 0x02 |
| 209 | #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 210 | #define EE_ENB (0x80 | EE_CS) |
| 211 | |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 212 | /* The EEPROM commands include the alway-set leading bit. */ |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 213 | #define EE_WRITE_CMD 5 |
| 214 | #define EE_READ_CMD 6 |
| 215 | #define EE_ERASE_CMD 7 |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 216 | |
Marek Vasut | 77676d5 | 2020-04-12 21:20:31 +0200 | [diff] [blame] | 217 | static void rtl8139_eeprom_delay(uintptr_t regbase) |
| 218 | { |
| 219 | /* |
| 220 | * Delay between EEPROM clock transitions. |
| 221 | * No extra delay is needed with 33MHz PCI, but 66MHz may change this. |
| 222 | */ |
| 223 | inl(regbase + RTL_REG_CFG9346); |
| 224 | } |
| 225 | |
Marek Vasut | 298b3de | 2020-04-12 21:28:30 +0200 | [diff] [blame] | 226 | static int rtl8139_read_eeprom(unsigned int location, unsigned int addr_len) |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 227 | { |
Marek Vasut | 298b3de | 2020-04-12 21:28:30 +0200 | [diff] [blame] | 228 | unsigned int read_cmd = location | (EE_READ_CMD << addr_len); |
| 229 | uintptr_t ee_addr = ioaddr + RTL_REG_CFG9346; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 230 | unsigned int retval = 0; |
Marek Vasut | 298b3de | 2020-04-12 21:28:30 +0200 | [diff] [blame] | 231 | u8 dataval; |
| 232 | int i; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 233 | |
| 234 | outb(EE_ENB & ~EE_CS, ee_addr); |
| 235 | outb(EE_ENB, ee_addr); |
Marek Vasut | 77676d5 | 2020-04-12 21:20:31 +0200 | [diff] [blame] | 236 | rtl8139_eeprom_delay(ioaddr); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 237 | |
| 238 | /* Shift the read command bits out. */ |
| 239 | for (i = 4 + addr_len; i >= 0; i--) { |
Marek Vasut | 298b3de | 2020-04-12 21:28:30 +0200 | [diff] [blame] | 240 | dataval = (read_cmd & BIT(i)) ? EE_DATA_WRITE : 0; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 241 | outb(EE_ENB | dataval, ee_addr); |
Marek Vasut | 77676d5 | 2020-04-12 21:20:31 +0200 | [diff] [blame] | 242 | rtl8139_eeprom_delay(ioaddr); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 243 | outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); |
Marek Vasut | 77676d5 | 2020-04-12 21:20:31 +0200 | [diff] [blame] | 244 | rtl8139_eeprom_delay(ioaddr); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 245 | } |
Marek Vasut | 298b3de | 2020-04-12 21:28:30 +0200 | [diff] [blame] | 246 | |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 247 | outb(EE_ENB, ee_addr); |
Marek Vasut | 77676d5 | 2020-04-12 21:20:31 +0200 | [diff] [blame] | 248 | rtl8139_eeprom_delay(ioaddr); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 249 | |
| 250 | for (i = 16; i > 0; i--) { |
| 251 | outb(EE_ENB | EE_SHIFT_CLK, ee_addr); |
Marek Vasut | 77676d5 | 2020-04-12 21:20:31 +0200 | [diff] [blame] | 252 | rtl8139_eeprom_delay(ioaddr); |
Marek Vasut | 298b3de | 2020-04-12 21:28:30 +0200 | [diff] [blame] | 253 | retval <<= 1; |
| 254 | retval |= inb(ee_addr) & EE_DATA_READ; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 255 | outb(EE_ENB, ee_addr); |
Marek Vasut | 77676d5 | 2020-04-12 21:20:31 +0200 | [diff] [blame] | 256 | rtl8139_eeprom_delay(ioaddr); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | /* Terminate the EEPROM access. */ |
| 260 | outb(~EE_CS, ee_addr); |
Marek Vasut | 77676d5 | 2020-04-12 21:20:31 +0200 | [diff] [blame] | 261 | rtl8139_eeprom_delay(ioaddr); |
Marek Vasut | 298b3de | 2020-04-12 21:28:30 +0200 | [diff] [blame] | 262 | |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 263 | return retval; |
| 264 | } |
| 265 | |
| 266 | static const unsigned int rtl8139_rx_config = |
| 267 | (RX_BUF_LEN_IDX << 11) | |
| 268 | (RX_FIFO_THRESH << 13) | |
| 269 | (RX_DMA_BURST << 8); |
| 270 | |
Marek Vasut | e07aa6d | 2020-04-12 21:35:12 +0200 | [diff] [blame] | 271 | static void rtl8139_set_rx_mode(struct eth_device *dev) |
| 272 | { |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 273 | /* !IFF_PROMISC */ |
Marek Vasut | e07aa6d | 2020-04-12 21:35:12 +0200 | [diff] [blame] | 274 | unsigned int rx_mode = RTL_REG_RXCONFIG_ACCEPTBROADCAST | |
| 275 | RTL_REG_RXCONFIG_ACCEPTMULTICAST | |
| 276 | RTL_REG_RXCONFIG_ACCEPTMYPHYS; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 277 | |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 278 | outl(rtl8139_rx_config | rx_mode, ioaddr + RTL_REG_RXCONFIG); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 279 | |
Marek Vasut | e07aa6d | 2020-04-12 21:35:12 +0200 | [diff] [blame] | 280 | outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 0); |
| 281 | outl(0xffffffff, ioaddr + RTL_REG_MAR0 + 4); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 282 | } |
| 283 | |
Marek Vasut | 0b9aab8 | 2020-04-12 22:58:27 +0200 | [diff] [blame] | 284 | static void rtl8139_hw_reset(struct eth_device *dev) |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 285 | { |
Marek Vasut | a51de2b | 2020-04-12 21:41:56 +0200 | [diff] [blame] | 286 | u8 reg; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 287 | int i; |
| 288 | |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 289 | outb(RTL_REG_CHIPCMD_CMDRESET, ioaddr + RTL_REG_CHIPCMD); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 290 | |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 291 | /* Give the chip 10ms to finish the reset. */ |
Marek Vasut | a51de2b | 2020-04-12 21:41:56 +0200 | [diff] [blame] | 292 | for (i = 0; i < 100; i++) { |
| 293 | reg = inb(ioaddr + RTL_REG_CHIPCMD); |
| 294 | if (!(reg & RTL_REG_CHIPCMD_CMDRESET)) |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 295 | break; |
Marek Vasut | a51de2b | 2020-04-12 21:41:56 +0200 | [diff] [blame] | 296 | |
| 297 | udelay(100); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 298 | } |
Marek Vasut | 0b9aab8 | 2020-04-12 22:58:27 +0200 | [diff] [blame] | 299 | } |
| 300 | |
| 301 | static void rtl8139_reset(struct eth_device *dev) |
| 302 | { |
| 303 | int i; |
| 304 | |
| 305 | cur_rx = 0; |
| 306 | cur_tx = 0; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 307 | |
Marek Vasut | 0b9aab8 | 2020-04-12 22:58:27 +0200 | [diff] [blame] | 308 | rtl8139_hw_reset(dev); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 309 | |
| 310 | for (i = 0; i < ETH_ALEN; i++) |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 311 | outb(dev->enetaddr[i], ioaddr + RTL_REG_MAC0 + i); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 312 | |
| 313 | /* Must enable Tx/Rx before setting transfer thresholds! */ |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 314 | outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, |
Marek Vasut | a51de2b | 2020-04-12 21:41:56 +0200 | [diff] [blame] | 315 | ioaddr + RTL_REG_CHIPCMD); |
| 316 | |
Marek Vasut | 6e61bf5 | 2020-04-12 21:30:38 +0200 | [diff] [blame] | 317 | /* accept no frames yet! */ |
| 318 | outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG); |
Marek Vasut | a51de2b | 2020-04-12 21:41:56 +0200 | [diff] [blame] | 319 | outl((TX_DMA_BURST << 8) | 0x03000000, ioaddr + RTL_REG_TXCONFIG); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 320 | |
Marek Vasut | a51de2b | 2020-04-12 21:41:56 +0200 | [diff] [blame] | 321 | /* |
| 322 | * The Linux driver changes RTL_REG_CONFIG1 here to use a different |
| 323 | * LED pattern for half duplex or full/autodetect duplex (for |
| 324 | * full/autodetect, the outputs are TX/RX, Link10/100, FULL, while |
| 325 | * for half duplex it uses TX/RX, Link100, Link10). This is messy, |
| 326 | * because it doesn't match the inscription on the mounting bracket. |
| 327 | * It should not be changed from the configuration EEPROM default, |
| 328 | * because the card manufacturer should have set that to match the |
| 329 | * card. |
| 330 | */ |
| 331 | debug_cond(DEBUG_RX, "rx ring address is %p\n", rx_ring); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 332 | |
Shinya Kuribayashi | ec450fe | 2008-01-16 16:12:26 +0900 | [diff] [blame] | 333 | flush_cache((unsigned long)rx_ring, RX_BUF_LEN); |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 334 | outl(phys_to_bus((int)rx_ring), ioaddr + RTL_REG_RXBUF); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 335 | |
Marek Vasut | a51de2b | 2020-04-12 21:41:56 +0200 | [diff] [blame] | 336 | /* |
| 337 | * If we add multicast support, the RTL_REG_MAR0 register would have |
| 338 | * to be initialized to 0xffffffffffffffff (two 32 bit accesses). |
| 339 | * Etherboot only needs broadcast (for ARP/RARP/BOOTP/DHCP) and |
| 340 | * unicast. |
| 341 | */ |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 342 | outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, |
Marek Vasut | a51de2b | 2020-04-12 21:41:56 +0200 | [diff] [blame] | 343 | ioaddr + RTL_REG_CHIPCMD); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 344 | |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 345 | outl(rtl8139_rx_config, ioaddr + RTL_REG_RXCONFIG); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 346 | |
| 347 | /* Start the chip's Tx and Rx process. */ |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 348 | outl(0, ioaddr + RTL_REG_RXMISSED); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 349 | |
Marek Vasut | e07aa6d | 2020-04-12 21:35:12 +0200 | [diff] [blame] | 350 | rtl8139_set_rx_mode(dev); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 351 | |
| 352 | /* Disable all known interrupts by setting the interrupt mask. */ |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 353 | outw(0, ioaddr + RTL_REG_INTRMASK); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 354 | } |
| 355 | |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 356 | static int rtl8139_send(struct eth_device *dev, void *packet, int length) |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 357 | { |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 358 | unsigned int len = length; |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 359 | unsigned long txstatus; |
| 360 | unsigned int status; |
Shinya Kuribayashi | fad82ef | 2008-01-16 16:11:14 +0900 | [diff] [blame] | 361 | int i = 0; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 362 | |
| 363 | ioaddr = dev->iobase; |
| 364 | |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 365 | memcpy(tx_buffer, packet, length); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 366 | |
Wolfgang Denk | d7bffbc | 2011-11-05 05:13:03 +0000 | [diff] [blame] | 367 | debug_cond(DEBUG_TX, "sending %d bytes\n", len); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 368 | |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 369 | /* |
| 370 | * Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 |
| 371 | * bytes are sent automatically for the FCS, totalling to 64 bytes). |
| 372 | */ |
| 373 | while (len < ETH_ZLEN) |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 374 | tx_buffer[len++] = '\0'; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 375 | |
Shinya Kuribayashi | ec450fe | 2008-01-16 16:12:26 +0900 | [diff] [blame] | 376 | flush_cache((unsigned long)tx_buffer, length); |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 377 | outl(phys_to_bus((unsigned long)tx_buffer), |
| 378 | ioaddr + RTL_REG_TXADDR0 + cur_tx * 4); |
| 379 | outl(((TX_FIFO_THRESH << 11) & 0x003f0000) | len, |
| 380 | ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 381 | |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 382 | do { |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 383 | status = inw(ioaddr + RTL_REG_INTRSTATUS); |
| 384 | /* |
| 385 | * Only acknlowledge interrupt sources we can properly |
| 386 | * handle here - the RTL_REG_INTRSTATUS_RXOVERFLOW/ |
| 387 | * RTL_REG_INTRSTATUS_RXFIFOOVER MUST be handled in the |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 388 | * rtl8139_recv() function. |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 389 | */ |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 390 | status &= RTL_REG_INTRSTATUS_TXOK | RTL_REG_INTRSTATUS_TXERR | |
| 391 | RTL_REG_INTRSTATUS_PCIERR; |
| 392 | outw(status, ioaddr + RTL_REG_INTRSTATUS); |
| 393 | if (status) |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 394 | break; |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 395 | |
Shinya Kuribayashi | fad82ef | 2008-01-16 16:11:14 +0900 | [diff] [blame] | 396 | udelay(10); |
| 397 | } while (i++ < RTL_TIMEOUT); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 398 | |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 399 | txstatus = inl(ioaddr + RTL_REG_TXSTATUS0 + cur_tx * 4); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 400 | |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 401 | if (!(status & RTL_REG_INTRSTATUS_TXOK)) { |
Wolfgang Denk | d7bffbc | 2011-11-05 05:13:03 +0000 | [diff] [blame] | 402 | debug_cond(DEBUG_TX, |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 403 | "tx timeout/error (%d usecs), status %hX txstatus %lX\n", |
| 404 | 10 * i, status, txstatus); |
Wolfgang Denk | d7bffbc | 2011-11-05 05:13:03 +0000 | [diff] [blame] | 405 | |
Marek Vasut | a51de2b | 2020-04-12 21:41:56 +0200 | [diff] [blame] | 406 | rtl8139_reset(dev); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 407 | |
| 408 | return 0; |
| 409 | } |
Marek Vasut | fbead9a | 2020-04-12 22:40:45 +0200 | [diff] [blame] | 410 | |
| 411 | cur_tx = (cur_tx + 1) % NUM_TX_DESC; |
| 412 | |
| 413 | debug_cond(DEBUG_TX, "tx done, status %hX txstatus %lX\n", |
| 414 | status, txstatus); |
| 415 | |
| 416 | return length; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 417 | } |
| 418 | |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 419 | static int rtl8139_recv(struct eth_device *dev) |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 420 | { |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 421 | const unsigned int rxstat = RTL_REG_INTRSTATUS_RXFIFOOVER | |
| 422 | RTL_REG_INTRSTATUS_RXOVERFLOW | |
| 423 | RTL_REG_INTRSTATUS_RXOK; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 424 | unsigned int rx_size, rx_status; |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 425 | unsigned int ring_offs; |
| 426 | unsigned int status; |
| 427 | int length = 0; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 428 | |
| 429 | ioaddr = dev->iobase; |
| 430 | |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 431 | if (inb(ioaddr + RTL_REG_CHIPCMD) & RTL_REG_CHIPCMD_RXBUFEMPTY) |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 432 | return 0; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 433 | |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 434 | status = inw(ioaddr + RTL_REG_INTRSTATUS); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 435 | /* See below for the rest of the interrupt acknowledges. */ |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 436 | outw(status & ~rxstat, ioaddr + RTL_REG_INTRSTATUS); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 437 | |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 438 | debug_cond(DEBUG_RX, "%s: int %hX ", __func__, status); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 439 | |
| 440 | ring_offs = cur_rx % RX_BUF_LEN; |
Shinya Kuribayashi | ec450fe | 2008-01-16 16:12:26 +0900 | [diff] [blame] | 441 | /* ring_offs is guaranteed being 4-byte aligned */ |
Shinya Kuribayashi | a466d55 | 2008-01-16 16:13:31 +0900 | [diff] [blame] | 442 | rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs)); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 443 | rx_size = rx_status >> 16; |
| 444 | rx_status &= 0xffff; |
| 445 | |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 446 | if ((rx_status & (RTL_STS_RXBADSYMBOL | RTL_STS_RXRUNT | |
| 447 | RTL_STS_RXTOOLONG | RTL_STS_RXCRCERR | |
| 448 | RTL_STS_RXBADALIGN)) || |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 449 | (rx_size < ETH_ZLEN) || |
| 450 | (rx_size > ETH_FRAME_LEN + 4)) { |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 451 | printf("rx error %hX\n", rx_status); |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 452 | /* this clears all interrupts still pending */ |
| 453 | rtl8139_reset(dev); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 454 | return 0; |
| 455 | } |
| 456 | |
| 457 | /* Received a good packet */ |
| 458 | length = rx_size - 4; /* no one cares about the FCS */ |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 459 | if (ring_offs + 4 + rx_size - 4 > RX_BUF_LEN) { |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 460 | unsigned char rxdata[RX_BUF_LEN]; |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 461 | int semi_count = RX_BUF_LEN - ring_offs - 4; |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 462 | |
| 463 | memcpy(rxdata, rx_ring + ring_offs + 4, semi_count); |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 464 | memcpy(&rxdata[semi_count], rx_ring, |
| 465 | rx_size - 4 - semi_count); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 466 | |
Joe Hershberger | 9f09a36 | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 467 | net_process_received_packet(rxdata, length); |
Wolfgang Denk | d7bffbc | 2011-11-05 05:13:03 +0000 | [diff] [blame] | 468 | debug_cond(DEBUG_RX, "rx packet %d+%d bytes", |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 469 | semi_count, rx_size - 4 - semi_count); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 470 | } else { |
Joe Hershberger | 9f09a36 | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 471 | net_process_received_packet(rx_ring + ring_offs + 4, length); |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 472 | debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size - 4); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 473 | } |
Shinya Kuribayashi | ec450fe | 2008-01-16 16:12:26 +0900 | [diff] [blame] | 474 | flush_cache((unsigned long)rx_ring, RX_BUF_LEN); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 475 | |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 476 | cur_rx = ROUND(cur_rx + rx_size + 4, 4); |
Marek Vasut | 230d982 | 2020-04-12 20:47:26 +0200 | [diff] [blame] | 477 | outw(cur_rx - 16, ioaddr + RTL_REG_RXBUFPTR); |
Marek Vasut | 60992ef | 2020-04-12 22:43:16 +0200 | [diff] [blame] | 478 | /* |
| 479 | * See RTL8139 Programming Guide V0.1 for the official handling of |
| 480 | * Rx overflow situations. The document itself contains basically |
| 481 | * no usable information, except for a few exception handling rules. |
| 482 | */ |
| 483 | outw(status & rxstat, ioaddr + RTL_REG_INTRSTATUS); |
| 484 | |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 485 | return length; |
| 486 | } |
| 487 | |
Marek Vasut | 5cf2585 | 2020-04-12 23:12:11 +0200 | [diff] [blame] | 488 | static int rtl8139_init(struct eth_device *dev, bd_t *bis) |
| 489 | { |
| 490 | unsigned short *ap = (unsigned short *)dev->enetaddr; |
| 491 | int addr_len, i; |
| 492 | u8 reg; |
| 493 | |
| 494 | ioaddr = dev->iobase; |
| 495 | |
| 496 | /* Bring the chip out of low-power mode. */ |
| 497 | outb(0x00, ioaddr + RTL_REG_CONFIG1); |
| 498 | |
| 499 | addr_len = rtl8139_read_eeprom(0, 8) == 0x8129 ? 8 : 6; |
| 500 | for (i = 0; i < 3; i++) |
| 501 | *ap++ = le16_to_cpu(rtl8139_read_eeprom(i + 7, addr_len)); |
| 502 | |
| 503 | rtl8139_reset(dev); |
| 504 | |
| 505 | reg = inb(ioaddr + RTL_REG_MEDIASTATUS); |
| 506 | if (reg & RTL_REG_MEDIASTATUS_MSRLINKFAIL) { |
| 507 | printf("Cable not connected or other link failure\n"); |
| 508 | return -1; |
| 509 | } |
| 510 | |
| 511 | return 0; |
| 512 | } |
| 513 | |
Marek Vasut | 111bcae | 2020-04-12 22:55:40 +0200 | [diff] [blame] | 514 | static void rtl8139_stop(struct eth_device *dev) |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 515 | { |
wdenk | bc01dd5 | 2004-01-02 16:05:07 +0000 | [diff] [blame] | 516 | ioaddr = dev->iobase; |
| 517 | |
Marek Vasut | 0b9aab8 | 2020-04-12 22:58:27 +0200 | [diff] [blame] | 518 | rtl8139_hw_reset(dev); |
wdenk | 0260cd6 | 2004-01-02 15:01:32 +0000 | [diff] [blame] | 519 | } |
Marek Vasut | 5cf2585 | 2020-04-12 23:12:11 +0200 | [diff] [blame] | 520 | |
| 521 | static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, |
| 522 | int join) |
| 523 | { |
| 524 | return 0; |
| 525 | } |
| 526 | |
| 527 | static struct pci_device_id supported[] = { |
| 528 | { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139 }, |
| 529 | { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139 }, |
| 530 | { } |
| 531 | }; |
| 532 | |
| 533 | int rtl8139_initialize(bd_t *bis) |
| 534 | { |
| 535 | struct eth_device *dev; |
| 536 | int card_number = 0; |
| 537 | pci_dev_t devno; |
| 538 | int idx = 0; |
| 539 | u32 iobase; |
| 540 | |
| 541 | while (1) { |
| 542 | /* Find RTL8139 */ |
| 543 | devno = pci_find_devices(supported, idx++); |
| 544 | if (devno < 0) |
| 545 | break; |
| 546 | |
| 547 | pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); |
| 548 | iobase &= ~0xf; |
| 549 | |
| 550 | debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); |
| 551 | |
| 552 | dev = (struct eth_device *)malloc(sizeof(*dev)); |
| 553 | if (!dev) { |
| 554 | printf("Can not allocate memory of rtl8139\n"); |
| 555 | break; |
| 556 | } |
| 557 | memset(dev, 0, sizeof(*dev)); |
| 558 | |
| 559 | sprintf(dev->name, "RTL8139#%d", card_number); |
| 560 | |
| 561 | dev->priv = (void *)devno; |
| 562 | dev->iobase = (int)bus_to_phys(iobase); |
| 563 | dev->init = rtl8139_init; |
| 564 | dev->halt = rtl8139_stop; |
| 565 | dev->send = rtl8139_send; |
| 566 | dev->recv = rtl8139_recv; |
| 567 | dev->mcast = rtl8139_bcast_addr; |
| 568 | |
| 569 | eth_register(dev); |
| 570 | |
| 571 | card_number++; |
| 572 | |
| 573 | pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); |
| 574 | |
| 575 | udelay(10 * 1000); |
| 576 | } |
| 577 | |
| 578 | return card_number; |
| 579 | } |